ia64/linux-2.6.18-xen.hg

changeset 853:711e402bc141

PCI: sync up the SR-IOV changes between Dom0 and upstream kernel

The SR-IOV patches for the upstream kernel are finally in-tree. This
patch backports some minor changes that appeared in the upstream
kernel after the Dom0 patches were checked-in.

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:48:03 2009 +0100 (2009-04-06)
parents 571229e265e2
children 950b9eb27661
files drivers/pci/Kconfig drivers/pci/iov.c drivers/pci/quirks.c
line diff
     1.1 --- a/drivers/pci/Kconfig	Mon Apr 06 13:47:27 2009 +0100
     1.2 +++ b/drivers/pci/Kconfig	Mon Apr 06 13:48:03 2009 +0100
     1.3 @@ -41,8 +41,8 @@ config PCI_IOV
     1.4  	bool "PCI IOV support"
     1.5  	depends on PCI
     1.6  	help
     1.7 -	  PCI-SIG I/O Virtualization (IOV) Specifications support.
     1.8 -	  Single Root IOV: allows the creation of virtual PCI devices
     1.9 -	  that share the physical resources from a real device.
    1.10 +	  I/O Virtualization is a PCI feature supported by some devices
    1.11 +	  which allows them to create virtual devices which share their
    1.12 +	  physical resources.
    1.13  
    1.14 -	  When in doubt, say N.
    1.15 +	  If unsure, say N.
     2.1 --- a/drivers/pci/iov.c	Mon Apr 06 13:47:27 2009 +0100
     2.2 +++ b/drivers/pci/iov.c	Mon Apr 06 13:48:03 2009 +0100
     2.3 @@ -309,16 +309,16 @@ static int sriov_init(struct pci_dev *de
     2.4  	if (!total)
     2.5  		return 0;
     2.6  
     2.7 +	ctrl = 0;
     2.8  	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
     2.9  		if (pdev->is_physfn)
    2.10 -			break;
    2.11 -	if (list_empty(&dev->bus->devices) || !pdev->is_physfn)
    2.12 -		pdev = NULL;
    2.13 +			goto found;
    2.14  
    2.15 -	ctrl = 0;
    2.16 -	if (!pdev && pci_ari_enabled(dev->bus))
    2.17 +	pdev = NULL;
    2.18 +	if (pci_ari_enabled(dev->bus))
    2.19  		ctrl |= PCI_SRIOV_CTRL_ARI;
    2.20  
    2.21 +found:
    2.22  	pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
    2.23  	pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
    2.24  	pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
    2.25 @@ -507,6 +507,7 @@ int pci_iov_bus_range(struct pci_bus *bu
    2.26  /**
    2.27   * pci_enable_sriov - enable the SR-IOV capability
    2.28   * @dev: the PCI device
    2.29 + * @nr_virtfn: number of Virtual Functions to enable
    2.30   *
    2.31   * Returns 0 on success, or negative on failure.
    2.32   */
     3.1 --- a/drivers/pci/quirks.c	Mon Apr 06 13:47:27 2009 +0100
     3.2 +++ b/drivers/pci/quirks.c	Mon Apr 06 13:48:03 2009 +0100
     3.3 @@ -1752,58 +1752,49 @@ EXPORT_SYMBOL(pci_fixup_device);
     3.4  #endif
     3.5  
     3.6  #ifdef CONFIG_PCI_IOV
     3.7 +
     3.8  /*
     3.9 - * If BIOS doesn't allocate resources for SR-IOV BARs, zero Flash BAR
    3.10 - * and program SR-IOV BARs to use the old Flash Memory Space.
    3.11 - * PCI subsystem may try to allocate Memory Space for Flash BAR later,
    3.12 - * that's why we don't clear Flash BAR flags.
    3.13 + * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
    3.14 + * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
    3.15 + * old Flash Memory Space.
    3.16   */
    3.17 -static void __devinit intel_82576_quirk(struct pci_dev *dev)
    3.18 +static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
    3.19  {
    3.20 -	int i, flags;
    3.21 +	int pos, flags;
    3.22  	u32 bar, start, size;
    3.23  
    3.24  	if (PAGE_SIZE > 0x10000)
    3.25  		return;
    3.26  
    3.27 -	if (pci_read_config_dword(dev, 0x184, &bar))
    3.28 +	flags = pci_resource_flags(dev, 0);
    3.29 +	if ((flags & PCI_BASE_ADDRESS_SPACE) !=
    3.30 +			PCI_BASE_ADDRESS_SPACE_MEMORY ||
    3.31 +	    (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
    3.32 +			PCI_BASE_ADDRESS_MEM_TYPE_32)
    3.33  		return;
    3.34  
    3.35 +	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
    3.36 +	if (!pos)
    3.37 +		return;
    3.38 +
    3.39 +	pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
    3.40  	if (bar & PCI_BASE_ADDRESS_MEM_MASK)
    3.41  		return;
    3.42  
    3.43 -	i = 1;
    3.44 -	flags = pci_resource_flags(dev, i);
    3.45 -	if ((flags & PCI_BASE_ADDRESS_SPACE) ==
    3.46 -			PCI_BASE_ADDRESS_SPACE_MEMORY &&
    3.47 -	    (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
    3.48 -			PCI_BASE_ADDRESS_MEM_TYPE_32)
    3.49 -		goto found;
    3.50 -
    3.51 -	i = 2;
    3.52 -	flags = pci_resource_flags(dev, i);
    3.53 -	if ((flags & PCI_BASE_ADDRESS_SPACE) ==
    3.54 -			PCI_BASE_ADDRESS_SPACE_MEMORY &&
    3.55 -	    (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
    3.56 -			PCI_BASE_ADDRESS_MEM_TYPE_64)
    3.57 -		goto found;
    3.58 -
    3.59 -	return;
    3.60 -found:
    3.61 -	start = pci_resource_start(dev, i);
    3.62 -	size = pci_resource_len(dev, i);
    3.63 +	start = pci_resource_start(dev, 1);
    3.64 +	size = pci_resource_len(dev, 1);
    3.65  	if (!start || size != 0x400000 || start & (size - 1))
    3.66  		return;
    3.67  
    3.68 -	pci_write_config_dword(dev, 0x10 + i * 4, 0);
    3.69 -	pci_resource_start(dev, i) = 0;
    3.70 -	pci_resource_end(dev, i) = size - 1;
    3.71 -	pci_write_config_dword(dev, 0x184, start);
    3.72 -	pci_write_config_dword(dev, 0x190, start + size / 2);
    3.73 +	pci_resource_flags(dev, 1) = 0;
    3.74 +	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
    3.75 +	pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
    3.76 +	pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
    3.77  
    3.78  	dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
    3.79  }
    3.80 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, intel_82576_quirk);
    3.81 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, intel_82576_quirk);
    3.82 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, intel_82576_quirk);
    3.83 -#endif /* CONFIG_PCI_IOV */
    3.84 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
    3.85 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
    3.86 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
    3.87 +
    3.88 +#endif	/* CONFIG_PCI_IOV */