ia64/linux-2.6.18-xen.hg

changeset 674:5f3c40a4c214

Dom0 ACPI: handle I/O access width that are not a multiple of 8 bits

Back ported following patch from upstream to support 4-bit access
width which is required by T-state control.
Below are original commit comments from upstream.

commit 49fbabf56dc715bbb51e59742e82ba762790aac0
Author: Zhao Yakui <yakui.zhao@intel.com>
Date: Thu Nov 15 17:01:06 2007 +0800

ACPI: Handle I/O access width requestst that are not a multiple of
8 bits.

We've run into BIOS that hand us 4-bit access width requests
for T-state control when the code expected only multipls of
8-bits.
Round up.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Shaohua <shaohua.li@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Sep 18 10:44:15 2008 +0100 (2008-09-18)
parents 3161879fdf22
children 37802a5c9f53
files drivers/acpi/osl.c
line diff
     1.1 --- a/drivers/acpi/osl.c	Tue Sep 16 21:26:15 2008 +0900
     1.2 +++ b/drivers/acpi/osl.c	Thu Sep 18 10:44:15 2008 +0100
     1.3 @@ -337,17 +337,14 @@ acpi_status acpi_os_read_port(acpi_io_ad
     1.4  	if (!value)
     1.5  		value = &dummy;
     1.6  
     1.7 -	switch (width) {
     1.8 -	case 8:
     1.9 +	*value = 0;
    1.10 +	if (width <= 8) {
    1.11  		*(u8 *) value = inb(port);
    1.12 -		break;
    1.13 -	case 16:
    1.14 +	} else if (width <= 16) {
    1.15  		*(u16 *) value = inw(port);
    1.16 -		break;
    1.17 -	case 32:
    1.18 +	} else if (width <= 32) {
    1.19  		*(u32 *) value = inl(port);
    1.20 -		break;
    1.21 -	default:
    1.22 +	} else {
    1.23  		BUG();
    1.24  	}
    1.25  
    1.26 @@ -358,17 +355,13 @@ EXPORT_SYMBOL(acpi_os_read_port);
    1.27  
    1.28  acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width)
    1.29  {
    1.30 -	switch (width) {
    1.31 -	case 8:
    1.32 +	if (width <= 8) {
    1.33  		outb(value, port);
    1.34 -		break;
    1.35 -	case 16:
    1.36 +	} else if (width <= 16) {
    1.37  		outw(value, port);
    1.38 -		break;
    1.39 -	case 32:
    1.40 +	} else if (width <= 32) {
    1.41  		outl(value, port);
    1.42 -		break;
    1.43 -	default:
    1.44 +	} else {
    1.45  		BUG();
    1.46  	}
    1.47