ia64/linux-2.6.18-xen.hg

changeset 795:2ee6febdd4f9

Add the e1000e driver for dom0

backport the driver from RHEL5.3 and make it work.

signed-off-by: Zhang Yang <yang.zhang@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Feb 17 11:25:22 2009 +0000 (2009-02-17)
parents be85b1d7a52b
children f0db1ac7ca8d
files arch/i386/defconfig arch/ia64/defconfig arch/x86_64/defconfig drivers/net/Kconfig drivers/net/Makefile drivers/net/e1000e/82571.c drivers/net/e1000e/Makefile drivers/net/e1000e/defines.h drivers/net/e1000e/e1000.h drivers/net/e1000e/e1000_compat.h drivers/net/e1000e/es2lan.c drivers/net/e1000e/ethtool.c drivers/net/e1000e/hw.h drivers/net/e1000e/ich8lan.c drivers/net/e1000e/lib.c drivers/net/e1000e/netdev.c drivers/net/e1000e/param.c drivers/net/e1000e/phy.c
line diff
     1.1 --- a/arch/i386/defconfig	Tue Feb 17 11:17:11 2009 +0000
     1.2 +++ b/arch/i386/defconfig	Tue Feb 17 11:25:22 2009 +0000
     1.3 @@ -681,6 +681,7 @@ CONFIG_E100=y
     1.4  # CONFIG_ACENIC is not set
     1.5  # CONFIG_DL2K is not set
     1.6  # CONFIG_E1000 is not set
     1.7 +# CONFIG_E1000E is not set
     1.8  # CONFIG_NS83820 is not set
     1.9  # CONFIG_HAMACHI is not set
    1.10  # CONFIG_YELLOWFIN is not set
     2.1 --- a/arch/ia64/defconfig	Tue Feb 17 11:17:11 2009 +0000
     2.2 +++ b/arch/ia64/defconfig	Tue Feb 17 11:25:22 2009 +0000
     2.3 @@ -594,6 +594,7 @@ CONFIG_E100=m
     2.4  # CONFIG_ACENIC is not set
     2.5  # CONFIG_DL2K is not set
     2.6  CONFIG_E1000=y
     2.7 +CONFIG_E1000E=y
     2.8  # CONFIG_E1000_NAPI is not set
     2.9  # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
    2.10  # CONFIG_NS83820 is not set
     3.1 --- a/arch/x86_64/defconfig	Tue Feb 17 11:17:11 2009 +0000
     3.2 +++ b/arch/x86_64/defconfig	Tue Feb 17 11:25:22 2009 +0000
     3.3 @@ -701,6 +701,7 @@ CONFIG_8139TOO=y
     3.4  # CONFIG_ACENIC is not set
     3.5  # CONFIG_DL2K is not set
     3.6  CONFIG_E1000=y
     3.7 +CONFIG_E1000E=y
     3.8  # CONFIG_E1000_NAPI is not set
     3.9  # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
    3.10  # CONFIG_NS83820 is not set
     4.1 --- a/drivers/net/Kconfig	Tue Feb 17 11:17:11 2009 +0000
     4.2 +++ b/drivers/net/Kconfig	Tue Feb 17 11:25:22 2009 +0000
     4.3 @@ -1960,6 +1960,29 @@ config E1000_DISABLE_PACKET_SPLIT
     4.4  
     4.5  	  If in doubt, say N.
     4.6  
     4.7 +config E1000E
     4.8 +	tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
     4.9 +	depends on PCI
    4.10 +	---help---
    4.11 +	  This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
    4.12 +	  ethernet family of adapters. For PCI or PCI-X e1000 adapters,
    4.13 +	  use the regular e1000 driver For more information on how to
    4.14 +	  identify your adapter, go to the Adapter & Driver ID Guide at:
    4.15 +
    4.16 +	  <http://support.intel.com/support/network/adapter/pro100/21397.htm>
    4.17 +
    4.18 +	  For general information and support, go to the Intel support
    4.19 +	  website at:
    4.20 +
    4.21 +	  <http://support.intel.com>
    4.22 +
    4.23 +	  More specific information on configuring the driver is in
    4.24 +	  <file:Documentation/networking/e1000e.txt>.
    4.25 +
    4.26 +	  To compile this driver as a module, choose M here and read
    4.27 +	  <file:Documentation/networking/net-modules.txt>.  The module
    4.28 +	  will be called e1000e.
    4.29 +
    4.30  source "drivers/net/ixp2000/Kconfig"
    4.31  
    4.32  config MYRI_SBUS
     5.1 --- a/drivers/net/Makefile	Tue Feb 17 11:17:11 2009 +0000
     5.2 +++ b/drivers/net/Makefile	Tue Feb 17 11:25:22 2009 +0000
     5.3 @@ -7,6 +7,7 @@ ifeq ($(CONFIG_ISDN_PPP),y)
     5.4  endif
     5.5  
     5.6  obj-$(CONFIG_E1000) += e1000/
     5.7 +obj-$(CONFIG_E1000E) += e1000e/
     5.8  obj-$(CONFIG_IBM_EMAC) += ibm_emac/
     5.9  obj-$(CONFIG_IXGB) += ixgb/
    5.10  obj-$(CONFIG_IXGBE) += ixgbe/
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/drivers/net/e1000e/82571.c	Tue Feb 17 11:25:22 2009 +0000
     6.3 @@ -0,0 +1,1510 @@
     6.4 +/*******************************************************************************
     6.5 +
     6.6 +  Intel PRO/1000 Linux driver
     6.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
     6.8 +
     6.9 +  This program is free software; you can redistribute it and/or modify it
    6.10 +  under the terms and conditions of the GNU General Public License,
    6.11 +  version 2, as published by the Free Software Foundation.
    6.12 +
    6.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    6.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    6.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    6.16 +  more details.
    6.17 +
    6.18 +  You should have received a copy of the GNU General Public License along with
    6.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    6.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    6.21 +
    6.22 +  The full GNU General Public License is included in this distribution in
    6.23 +  the file called "COPYING".
    6.24 +
    6.25 +  Contact Information:
    6.26 +  Linux NICS <linux.nics@intel.com>
    6.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    6.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    6.29 +
    6.30 +*******************************************************************************/
    6.31 +
    6.32 +/*
    6.33 + * 82571EB Gigabit Ethernet Controller
    6.34 + * 82571EB Gigabit Ethernet Controller (Fiber)
    6.35 + * 82571EB Dual Port Gigabit Mezzanine Adapter
    6.36 + * 82571EB Quad Port Gigabit Mezzanine Adapter
    6.37 + * 82571PT Gigabit PT Quad Port Server ExpressModule
    6.38 + * 82572EI Gigabit Ethernet Controller (Copper)
    6.39 + * 82572EI Gigabit Ethernet Controller (Fiber)
    6.40 + * 82572EI Gigabit Ethernet Controller
    6.41 + * 82573V Gigabit Ethernet Controller (Copper)
    6.42 + * 82573E Gigabit Ethernet Controller (Copper)
    6.43 + * 82573L Gigabit Ethernet Controller
    6.44 + * 82574L Gigabit Network Connection
    6.45 + */
    6.46 +
    6.47 +#include <linux/netdevice.h>
    6.48 +#include <linux/delay.h>
    6.49 +#include <linux/pci.h>
    6.50 +
    6.51 +#include "e1000.h"
    6.52 +
    6.53 +#define ID_LED_RESERVED_F746 0xF746
    6.54 +#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
    6.55 +			      (ID_LED_OFF1_ON2  <<  8) | \
    6.56 +			      (ID_LED_DEF1_DEF2 <<  4) | \
    6.57 +			      (ID_LED_DEF1_DEF2))
    6.58 +
    6.59 +#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
    6.60 +
    6.61 +#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
    6.62 +
    6.63 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
    6.64 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
    6.65 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
    6.66 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
    6.67 +				      u16 words, u16 *data);
    6.68 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
    6.69 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
    6.70 +static s32 e1000_setup_link_82571(struct e1000_hw *hw);
    6.71 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
    6.72 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
    6.73 +static s32 e1000_led_on_82574(struct e1000_hw *hw);
    6.74 +
    6.75 +/**
    6.76 + *  e1000_init_phy_params_82571 - Init PHY func ptrs.
    6.77 + *  @hw: pointer to the HW structure
    6.78 + *
    6.79 + *  This is a function pointer entry point called by the api module.
    6.80 + **/
    6.81 +static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
    6.82 +{
    6.83 +	struct e1000_phy_info *phy = &hw->phy;
    6.84 +	s32 ret_val;
    6.85 +
    6.86 +	if (hw->phy.media_type != e1000_media_type_copper) {
    6.87 +		phy->type = e1000_phy_none;
    6.88 +		return 0;
    6.89 +	}
    6.90 +
    6.91 +	phy->addr			 = 1;
    6.92 +	phy->autoneg_mask		 = AUTONEG_ADVERTISE_SPEED_DEFAULT;
    6.93 +	phy->reset_delay_us		 = 100;
    6.94 +
    6.95 +	switch (hw->mac.type) {
    6.96 +	case e1000_82571:
    6.97 +	case e1000_82572:
    6.98 +		phy->type		 = e1000_phy_igp_2;
    6.99 +		break;
   6.100 +	case e1000_82573:
   6.101 +		phy->type		 = e1000_phy_m88;
   6.102 +		break;
   6.103 +	case e1000_82574:
   6.104 +		phy->type		 = e1000_phy_bm;
   6.105 +		break;
   6.106 +	default:
   6.107 +		return -E1000_ERR_PHY;
   6.108 +		break;
   6.109 +	}
   6.110 +
   6.111 +	/* This can only be done after all function pointers are setup. */
   6.112 +	ret_val = e1000_get_phy_id_82571(hw);
   6.113 +
   6.114 +	/* Verify phy id */
   6.115 +	switch (hw->mac.type) {
   6.116 +	case e1000_82571:
   6.117 +	case e1000_82572:
   6.118 +		if (phy->id != IGP01E1000_I_PHY_ID)
   6.119 +			return -E1000_ERR_PHY;
   6.120 +		break;
   6.121 +	case e1000_82573:
   6.122 +		if (phy->id != M88E1111_I_PHY_ID)
   6.123 +			return -E1000_ERR_PHY;
   6.124 +		break;
   6.125 +	case e1000_82574:
   6.126 +		if (phy->id != BME1000_E_PHY_ID_R2)
   6.127 +			return -E1000_ERR_PHY;
   6.128 +		break;
   6.129 +	default:
   6.130 +		return -E1000_ERR_PHY;
   6.131 +		break;
   6.132 +	}
   6.133 +
   6.134 +	return 0;
   6.135 +}
   6.136 +
   6.137 +/**
   6.138 + *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
   6.139 + *  @hw: pointer to the HW structure
   6.140 + *
   6.141 + *  This is a function pointer entry point called by the api module.
   6.142 + **/
   6.143 +static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
   6.144 +{
   6.145 +	struct e1000_nvm_info *nvm = &hw->nvm;
   6.146 +	u32 eecd = er32(EECD);
   6.147 +	u16 size;
   6.148 +
   6.149 +	nvm->opcode_bits = 8;
   6.150 +	nvm->delay_usec = 1;
   6.151 +	switch (nvm->override) {
   6.152 +	case e1000_nvm_override_spi_large:
   6.153 +		nvm->page_size = 32;
   6.154 +		nvm->address_bits = 16;
   6.155 +		break;
   6.156 +	case e1000_nvm_override_spi_small:
   6.157 +		nvm->page_size = 8;
   6.158 +		nvm->address_bits = 8;
   6.159 +		break;
   6.160 +	default:
   6.161 +		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
   6.162 +		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
   6.163 +		break;
   6.164 +	}
   6.165 +
   6.166 +	switch (hw->mac.type) {
   6.167 +	case e1000_82573:
   6.168 +	case e1000_82574:
   6.169 +		if (((eecd >> 15) & 0x3) == 0x3) {
   6.170 +			nvm->type = e1000_nvm_flash_hw;
   6.171 +			nvm->word_size = 2048;
   6.172 +			/*
   6.173 +			 * Autonomous Flash update bit must be cleared due
   6.174 +			 * to Flash update issue.
   6.175 +			 */
   6.176 +			eecd &= ~E1000_EECD_AUPDEN;
   6.177 +			ew32(EECD, eecd);
   6.178 +			break;
   6.179 +		}
   6.180 +		/* Fall Through */
   6.181 +	default:
   6.182 +		nvm->type = e1000_nvm_eeprom_spi;
   6.183 +		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
   6.184 +				  E1000_EECD_SIZE_EX_SHIFT);
   6.185 +		/*
   6.186 +		 * Added to a constant, "size" becomes the left-shift value
   6.187 +		 * for setting word_size.
   6.188 +		 */
   6.189 +		size += NVM_WORD_SIZE_BASE_SHIFT;
   6.190 +
   6.191 +		/* EEPROM access above 16k is unsupported */
   6.192 +		if (size > 14)
   6.193 +			size = 14;
   6.194 +		nvm->word_size	= 1 << size;
   6.195 +		break;
   6.196 +	}
   6.197 +
   6.198 +	return 0;
   6.199 +}
   6.200 +
   6.201 +/**
   6.202 + *  e1000_init_mac_params_82571 - Init MAC func ptrs.
   6.203 + *  @hw: pointer to the HW structure
   6.204 + *
   6.205 + *  This is a function pointer entry point called by the api module.
   6.206 + **/
   6.207 +static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
   6.208 +{
   6.209 +	struct e1000_hw *hw = &adapter->hw;
   6.210 +	struct e1000_mac_info *mac = &hw->mac;
   6.211 +	struct e1000_mac_operations *func = &mac->ops;
   6.212 +
   6.213 +	/* Set media type */
   6.214 +	switch (adapter->pdev->device) {
   6.215 +	case E1000_DEV_ID_82571EB_FIBER:
   6.216 +	case E1000_DEV_ID_82572EI_FIBER:
   6.217 +	case E1000_DEV_ID_82571EB_QUAD_FIBER:
   6.218 +		hw->phy.media_type = e1000_media_type_fiber;
   6.219 +		break;
   6.220 +	case E1000_DEV_ID_82571EB_SERDES:
   6.221 +	case E1000_DEV_ID_82572EI_SERDES:
   6.222 +	case E1000_DEV_ID_82571EB_SERDES_DUAL:
   6.223 +	case E1000_DEV_ID_82571EB_SERDES_QUAD:
   6.224 +		hw->phy.media_type = e1000_media_type_internal_serdes;
   6.225 +		break;
   6.226 +	default:
   6.227 +		hw->phy.media_type = e1000_media_type_copper;
   6.228 +		break;
   6.229 +	}
   6.230 +
   6.231 +	/* Set mta register count */
   6.232 +	mac->mta_reg_count = 128;
   6.233 +	/* Set rar entry count */
   6.234 +	mac->rar_entry_count = E1000_RAR_ENTRIES;
   6.235 +	/* Set if manageability features are enabled. */
   6.236 +	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
   6.237 +
   6.238 +	/* check for link */
   6.239 +	switch (hw->phy.media_type) {
   6.240 +	case e1000_media_type_copper:
   6.241 +		func->setup_physical_interface = e1000_setup_copper_link_82571;
   6.242 +		func->check_for_link = e1000e_check_for_copper_link;
   6.243 +		func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
   6.244 +		break;
   6.245 +	case e1000_media_type_fiber:
   6.246 +		func->setup_physical_interface =
   6.247 +			e1000_setup_fiber_serdes_link_82571;
   6.248 +		func->check_for_link = e1000e_check_for_fiber_link;
   6.249 +		func->get_link_up_info =
   6.250 +			e1000e_get_speed_and_duplex_fiber_serdes;
   6.251 +		break;
   6.252 +	case e1000_media_type_internal_serdes:
   6.253 +		func->setup_physical_interface =
   6.254 +			e1000_setup_fiber_serdes_link_82571;
   6.255 +		func->check_for_link = e1000e_check_for_serdes_link;
   6.256 +		func->get_link_up_info =
   6.257 +			e1000e_get_speed_and_duplex_fiber_serdes;
   6.258 +		break;
   6.259 +	default:
   6.260 +		return -E1000_ERR_CONFIG;
   6.261 +		break;
   6.262 +	}
   6.263 +
   6.264 +	switch (hw->mac.type) {
   6.265 +	case e1000_82574:
   6.266 +		func->check_mng_mode = e1000_check_mng_mode_82574;
   6.267 +		func->led_on = e1000_led_on_82574;
   6.268 +		break;
   6.269 +	default:
   6.270 +		func->check_mng_mode = e1000e_check_mng_mode_generic;
   6.271 +		func->led_on = e1000e_led_on_generic;
   6.272 +		break;
   6.273 +	}
   6.274 +
   6.275 +	return 0;
   6.276 +}
   6.277 +
   6.278 +static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
   6.279 +{
   6.280 +	struct e1000_hw *hw = &adapter->hw;
   6.281 +	static int global_quad_port_a; /* global port a indication */
   6.282 +	struct pci_dev *pdev = adapter->pdev;
   6.283 +	u16 eeprom_data = 0;
   6.284 +	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
   6.285 +	s32 rc;
   6.286 +
   6.287 +	rc = e1000_init_mac_params_82571(adapter);
   6.288 +	if (rc)
   6.289 +		return rc;
   6.290 +
   6.291 +	rc = e1000_init_nvm_params_82571(hw);
   6.292 +	if (rc)
   6.293 +		return rc;
   6.294 +
   6.295 +	rc = e1000_init_phy_params_82571(hw);
   6.296 +	if (rc)
   6.297 +		return rc;
   6.298 +
   6.299 +	/* tag quad port adapters first, it's used below */
   6.300 +	switch (pdev->device) {
   6.301 +	case E1000_DEV_ID_82571EB_QUAD_COPPER:
   6.302 +	case E1000_DEV_ID_82571EB_QUAD_FIBER:
   6.303 +	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
   6.304 +	case E1000_DEV_ID_82571PT_QUAD_COPPER:
   6.305 +		adapter->flags |= FLAG_IS_QUAD_PORT;
   6.306 +		/* mark the first port */
   6.307 +		if (global_quad_port_a == 0)
   6.308 +			adapter->flags |= FLAG_IS_QUAD_PORT_A;
   6.309 +		/* Reset for multiple quad port adapters */
   6.310 +		global_quad_port_a++;
   6.311 +		if (global_quad_port_a == 4)
   6.312 +			global_quad_port_a = 0;
   6.313 +		break;
   6.314 +	default:
   6.315 +		break;
   6.316 +	}
   6.317 +
   6.318 +	switch (adapter->hw.mac.type) {
   6.319 +	case e1000_82571:
   6.320 +		/* these dual ports don't have WoL on port B at all */
   6.321 +		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
   6.322 +		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
   6.323 +		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
   6.324 +		    (is_port_b))
   6.325 +			adapter->flags &= ~FLAG_HAS_WOL;
   6.326 +		/* quad ports only support WoL on port A */
   6.327 +		if (adapter->flags & FLAG_IS_QUAD_PORT &&
   6.328 +		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
   6.329 +			adapter->flags &= ~FLAG_HAS_WOL;
   6.330 +		/* Does not support WoL on any port */
   6.331 +		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
   6.332 +			adapter->flags &= ~FLAG_HAS_WOL;
   6.333 +		break;
   6.334 +
   6.335 +	case e1000_82573:
   6.336 +		if (pdev->device == E1000_DEV_ID_82573L) {
   6.337 +			e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
   6.338 +				       &eeprom_data);
   6.339 +			if (eeprom_data & NVM_WORD1A_ASPM_MASK)
   6.340 +				adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
   6.341 +		}
   6.342 +		break;
   6.343 +	default:
   6.344 +		break;
   6.345 +	}
   6.346 +
   6.347 +	return 0;
   6.348 +}
   6.349 +
   6.350 +/**
   6.351 + *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
   6.352 + *  @hw: pointer to the HW structure
   6.353 + *
   6.354 + *  Reads the PHY registers and stores the PHY ID and possibly the PHY
   6.355 + *  revision in the hardware structure.
   6.356 + **/
   6.357 +static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
   6.358 +{
   6.359 +	struct e1000_phy_info *phy = &hw->phy;
   6.360 +	s32 ret_val;
   6.361 +	u16 phy_id = 0;
   6.362 +
   6.363 +	switch (hw->mac.type) {
   6.364 +	case e1000_82571:
   6.365 +	case e1000_82572:
   6.366 +		/*
   6.367 +		 * The 82571 firmware may still be configuring the PHY.
   6.368 +		 * In this case, we cannot access the PHY until the
   6.369 +		 * configuration is done.  So we explicitly set the
   6.370 +		 * PHY ID.
   6.371 +		 */
   6.372 +		phy->id = IGP01E1000_I_PHY_ID;
   6.373 +		break;
   6.374 +	case e1000_82573:
   6.375 +		return e1000e_get_phy_id(hw);
   6.376 +		break;
   6.377 +	case e1000_82574:
   6.378 +		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
   6.379 +		if (ret_val)
   6.380 +			return ret_val;
   6.381 +
   6.382 +		phy->id = (u32)(phy_id << 16);
   6.383 +		udelay(20);
   6.384 +		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
   6.385 +		if (ret_val)
   6.386 +			return ret_val;
   6.387 +
   6.388 +		phy->id |= (u32)(phy_id);
   6.389 +		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
   6.390 +		break;
   6.391 +	default:
   6.392 +		return -E1000_ERR_PHY;
   6.393 +		break;
   6.394 +	}
   6.395 +
   6.396 +	return 0;
   6.397 +}
   6.398 +
   6.399 +/**
   6.400 + *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
   6.401 + *  @hw: pointer to the HW structure
   6.402 + *
   6.403 + *  Acquire the HW semaphore to access the PHY or NVM
   6.404 + **/
   6.405 +static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
   6.406 +{
   6.407 +	u32 swsm;
   6.408 +	s32 timeout = hw->nvm.word_size + 1;
   6.409 +	s32 i = 0;
   6.410 +
   6.411 +	/* Get the FW semaphore. */
   6.412 +	for (i = 0; i < timeout; i++) {
   6.413 +		swsm = er32(SWSM);
   6.414 +		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
   6.415 +
   6.416 +		/* Semaphore acquired if bit latched */
   6.417 +		if (er32(SWSM) & E1000_SWSM_SWESMBI)
   6.418 +			break;
   6.419 +
   6.420 +		udelay(50);
   6.421 +	}
   6.422 +
   6.423 +	if (i == timeout) {
   6.424 +		/* Release semaphores */
   6.425 +		e1000e_put_hw_semaphore(hw);
   6.426 +		hw_dbg(hw, "Driver can't access the NVM\n");
   6.427 +		return -E1000_ERR_NVM;
   6.428 +	}
   6.429 +
   6.430 +	return 0;
   6.431 +}
   6.432 +
   6.433 +/**
   6.434 + *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
   6.435 + *  @hw: pointer to the HW structure
   6.436 + *
   6.437 + *  Release hardware semaphore used to access the PHY or NVM
   6.438 + **/
   6.439 +static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
   6.440 +{
   6.441 +	u32 swsm;
   6.442 +
   6.443 +	swsm = er32(SWSM);
   6.444 +
   6.445 +	swsm &= ~E1000_SWSM_SWESMBI;
   6.446 +
   6.447 +	ew32(SWSM, swsm);
   6.448 +}
   6.449 +
   6.450 +/**
   6.451 + *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
   6.452 + *  @hw: pointer to the HW structure
   6.453 + *
   6.454 + *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
   6.455 + *  Then for non-82573 hardware, set the EEPROM access request bit and wait
   6.456 + *  for EEPROM access grant bit.  If the access grant bit is not set, release
   6.457 + *  hardware semaphore.
   6.458 + **/
   6.459 +static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
   6.460 +{
   6.461 +	s32 ret_val;
   6.462 +
   6.463 +	ret_val = e1000_get_hw_semaphore_82571(hw);
   6.464 +	if (ret_val)
   6.465 +		return ret_val;
   6.466 +
   6.467 +	if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
   6.468 +		ret_val = e1000e_acquire_nvm(hw);
   6.469 +
   6.470 +	if (ret_val)
   6.471 +		e1000_put_hw_semaphore_82571(hw);
   6.472 +
   6.473 +	return ret_val;
   6.474 +}
   6.475 +
   6.476 +/**
   6.477 + *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
   6.478 + *  @hw: pointer to the HW structure
   6.479 + *
   6.480 + *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
   6.481 + **/
   6.482 +static void e1000_release_nvm_82571(struct e1000_hw *hw)
   6.483 +{
   6.484 +	e1000e_release_nvm(hw);
   6.485 +	e1000_put_hw_semaphore_82571(hw);
   6.486 +}
   6.487 +
   6.488 +/**
   6.489 + *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
   6.490 + *  @hw: pointer to the HW structure
   6.491 + *  @offset: offset within the EEPROM to be written to
   6.492 + *  @words: number of words to write
   6.493 + *  @data: 16 bit word(s) to be written to the EEPROM
   6.494 + *
   6.495 + *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
   6.496 + *
   6.497 + *  If e1000e_update_nvm_checksum is not called after this function, the
   6.498 + *  EEPROM will most likely contain an invalid checksum.
   6.499 + **/
   6.500 +static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
   6.501 +				 u16 *data)
   6.502 +{
   6.503 +	s32 ret_val;
   6.504 +
   6.505 +	switch (hw->mac.type) {
   6.506 +	case e1000_82573:
   6.507 +	case e1000_82574:
   6.508 +		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
   6.509 +		break;
   6.510 +	case e1000_82571:
   6.511 +	case e1000_82572:
   6.512 +		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
   6.513 +		break;
   6.514 +	default:
   6.515 +		ret_val = -E1000_ERR_NVM;
   6.516 +		break;
   6.517 +	}
   6.518 +
   6.519 +	return ret_val;
   6.520 +}
   6.521 +
   6.522 +/**
   6.523 + *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
   6.524 + *  @hw: pointer to the HW structure
   6.525 + *
   6.526 + *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
   6.527 + *  up to the checksum.  Then calculates the EEPROM checksum and writes the
   6.528 + *  value to the EEPROM.
   6.529 + **/
   6.530 +static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
   6.531 +{
   6.532 +	u32 eecd;
   6.533 +	s32 ret_val;
   6.534 +	u16 i;
   6.535 +
   6.536 +	ret_val = e1000e_update_nvm_checksum_generic(hw);
   6.537 +	if (ret_val)
   6.538 +		return ret_val;
   6.539 +
   6.540 +	/*
   6.541 +	 * If our nvm is an EEPROM, then we're done
   6.542 +	 * otherwise, commit the checksum to the flash NVM.
   6.543 +	 */
   6.544 +	if (hw->nvm.type != e1000_nvm_flash_hw)
   6.545 +		return ret_val;
   6.546 +
   6.547 +	/* Check for pending operations. */
   6.548 +	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
   6.549 +		msleep(1);
   6.550 +		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
   6.551 +			break;
   6.552 +	}
   6.553 +
   6.554 +	if (i == E1000_FLASH_UPDATES)
   6.555 +		return -E1000_ERR_NVM;
   6.556 +
   6.557 +	/* Reset the firmware if using STM opcode. */
   6.558 +	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
   6.559 +		/*
   6.560 +		 * The enabling of and the actual reset must be done
   6.561 +		 * in two write cycles.
   6.562 +		 */
   6.563 +		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
   6.564 +		e1e_flush();
   6.565 +		ew32(HICR, E1000_HICR_FW_RESET);
   6.566 +	}
   6.567 +
   6.568 +	/* Commit the write to flash */
   6.569 +	eecd = er32(EECD) | E1000_EECD_FLUPD;
   6.570 +	ew32(EECD, eecd);
   6.571 +
   6.572 +	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
   6.573 +		msleep(1);
   6.574 +		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
   6.575 +			break;
   6.576 +	}
   6.577 +
   6.578 +	if (i == E1000_FLASH_UPDATES)
   6.579 +		return -E1000_ERR_NVM;
   6.580 +
   6.581 +	return 0;
   6.582 +}
   6.583 +
   6.584 +/**
   6.585 + *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
   6.586 + *  @hw: pointer to the HW structure
   6.587 + *
   6.588 + *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
   6.589 + *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
   6.590 + **/
   6.591 +static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
   6.592 +{
   6.593 +	if (hw->nvm.type == e1000_nvm_flash_hw)
   6.594 +		e1000_fix_nvm_checksum_82571(hw);
   6.595 +
   6.596 +	return e1000e_validate_nvm_checksum_generic(hw);
   6.597 +}
   6.598 +
   6.599 +/**
   6.600 + *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
   6.601 + *  @hw: pointer to the HW structure
   6.602 + *  @offset: offset within the EEPROM to be written to
   6.603 + *  @words: number of words to write
   6.604 + *  @data: 16 bit word(s) to be written to the EEPROM
   6.605 + *
   6.606 + *  After checking for invalid values, poll the EEPROM to ensure the previous
   6.607 + *  command has completed before trying to write the next word.  After write
   6.608 + *  poll for completion.
   6.609 + *
   6.610 + *  If e1000e_update_nvm_checksum is not called after this function, the
   6.611 + *  EEPROM will most likely contain an invalid checksum.
   6.612 + **/
   6.613 +static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
   6.614 +				      u16 words, u16 *data)
   6.615 +{
   6.616 +	struct e1000_nvm_info *nvm = &hw->nvm;
   6.617 +	u32 i;
   6.618 +	u32 eewr = 0;
   6.619 +	s32 ret_val = 0;
   6.620 +
   6.621 +	/*
   6.622 +	 * A check for invalid values:  offset too large, too many words,
   6.623 +	 * and not enough words.
   6.624 +	 */
   6.625 +	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
   6.626 +	    (words == 0)) {
   6.627 +		hw_dbg(hw, "nvm parameter(s) out of bounds\n");
   6.628 +		return -E1000_ERR_NVM;
   6.629 +	}
   6.630 +
   6.631 +	for (i = 0; i < words; i++) {
   6.632 +		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
   6.633 +		       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
   6.634 +		       E1000_NVM_RW_REG_START;
   6.635 +
   6.636 +		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
   6.637 +		if (ret_val)
   6.638 +			break;
   6.639 +
   6.640 +		ew32(EEWR, eewr);
   6.641 +
   6.642 +		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
   6.643 +		if (ret_val)
   6.644 +			break;
   6.645 +	}
   6.646 +
   6.647 +	return ret_val;
   6.648 +}
   6.649 +
   6.650 +/**
   6.651 + *  e1000_get_cfg_done_82571 - Poll for configuration done
   6.652 + *  @hw: pointer to the HW structure
   6.653 + *
   6.654 + *  Reads the management control register for the config done bit to be set.
   6.655 + **/
   6.656 +static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
   6.657 +{
   6.658 +	s32 timeout = PHY_CFG_TIMEOUT;
   6.659 +
   6.660 +	while (timeout) {
   6.661 +		if (er32(EEMNGCTL) &
   6.662 +		    E1000_NVM_CFG_DONE_PORT_0)
   6.663 +			break;
   6.664 +		msleep(1);
   6.665 +		timeout--;
   6.666 +	}
   6.667 +	if (!timeout) {
   6.668 +		hw_dbg(hw, "MNG configuration cycle has not completed.\n");
   6.669 +		return -E1000_ERR_RESET;
   6.670 +	}
   6.671 +
   6.672 +	return 0;
   6.673 +}
   6.674 +
   6.675 +/**
   6.676 + *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
   6.677 + *  @hw: pointer to the HW structure
   6.678 + *  @active: TRUE to enable LPLU, FALSE to disable
   6.679 + *
   6.680 + *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
   6.681 + *  this function also disables smart speed and vice versa.  LPLU will not be
   6.682 + *  activated unless the device autonegotiation advertisement meets standards
   6.683 + *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
   6.684 + *  pointer entry point only called by PHY setup routines.
   6.685 + **/
   6.686 +static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
   6.687 +{
   6.688 +	struct e1000_phy_info *phy = &hw->phy;
   6.689 +	s32 ret_val;
   6.690 +	u16 data;
   6.691 +
   6.692 +	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
   6.693 +	if (ret_val)
   6.694 +		return ret_val;
   6.695 +
   6.696 +	if (active) {
   6.697 +		data |= IGP02E1000_PM_D0_LPLU;
   6.698 +		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
   6.699 +		if (ret_val)
   6.700 +			return ret_val;
   6.701 +
   6.702 +		/* When LPLU is enabled, we should disable SmartSpeed */
   6.703 +		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
   6.704 +		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
   6.705 +		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
   6.706 +		if (ret_val)
   6.707 +			return ret_val;
   6.708 +	} else {
   6.709 +		data &= ~IGP02E1000_PM_D0_LPLU;
   6.710 +		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
   6.711 +		/*
   6.712 +		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
   6.713 +		 * during Dx states where the power conservation is most
   6.714 +		 * important.  During driver activity we should enable
   6.715 +		 * SmartSpeed, so performance is maintained.
   6.716 +		 */
   6.717 +		if (phy->smart_speed == e1000_smart_speed_on) {
   6.718 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
   6.719 +					   &data);
   6.720 +			if (ret_val)
   6.721 +				return ret_val;
   6.722 +
   6.723 +			data |= IGP01E1000_PSCFR_SMART_SPEED;
   6.724 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
   6.725 +					   data);
   6.726 +			if (ret_val)
   6.727 +				return ret_val;
   6.728 +		} else if (phy->smart_speed == e1000_smart_speed_off) {
   6.729 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
   6.730 +					   &data);
   6.731 +			if (ret_val)
   6.732 +				return ret_val;
   6.733 +
   6.734 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
   6.735 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
   6.736 +					   data);
   6.737 +			if (ret_val)
   6.738 +				return ret_val;
   6.739 +		}
   6.740 +	}
   6.741 +
   6.742 +	return 0;
   6.743 +}
   6.744 +
   6.745 +/**
   6.746 + *  e1000_reset_hw_82571 - Reset hardware
   6.747 + *  @hw: pointer to the HW structure
   6.748 + *
   6.749 + *  This resets the hardware into a known state.  This is a
   6.750 + *  function pointer entry point called by the api module.
   6.751 + **/
   6.752 +static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
   6.753 +{
   6.754 +	u32 ctrl;
   6.755 +	u32 extcnf_ctrl;
   6.756 +	u32 ctrl_ext;
   6.757 +	u32 icr;
   6.758 +	s32 ret_val;
   6.759 +	u16 i = 0;
   6.760 +
   6.761 +	/*
   6.762 +	 * Prevent the PCI-E bus from sticking if there is no TLP connection
   6.763 +	 * on the last TLP read/write transaction when MAC is reset.
   6.764 +	 */
   6.765 +	ret_val = e1000e_disable_pcie_master(hw);
   6.766 +	if (ret_val)
   6.767 +		hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
   6.768 +
   6.769 +	hw_dbg(hw, "Masking off all interrupts\n");
   6.770 +	ew32(IMC, 0xffffffff);
   6.771 +
   6.772 +	ew32(RCTL, 0);
   6.773 +	ew32(TCTL, E1000_TCTL_PSP);
   6.774 +	e1e_flush();
   6.775 +
   6.776 +	msleep(10);
   6.777 +
   6.778 +	/*
   6.779 +	 * Must acquire the MDIO ownership before MAC reset.
   6.780 +	 * Ownership defaults to firmware after a reset.
   6.781 +	 */
   6.782 +	if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
   6.783 +		extcnf_ctrl = er32(EXTCNF_CTRL);
   6.784 +		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
   6.785 +
   6.786 +		do {
   6.787 +			ew32(EXTCNF_CTRL, extcnf_ctrl);
   6.788 +			extcnf_ctrl = er32(EXTCNF_CTRL);
   6.789 +
   6.790 +			if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
   6.791 +				break;
   6.792 +
   6.793 +			extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
   6.794 +
   6.795 +			msleep(2);
   6.796 +			i++;
   6.797 +		} while (i < MDIO_OWNERSHIP_TIMEOUT);
   6.798 +	}
   6.799 +
   6.800 +	ctrl = er32(CTRL);
   6.801 +
   6.802 +	hw_dbg(hw, "Issuing a global reset to MAC\n");
   6.803 +	ew32(CTRL, ctrl | E1000_CTRL_RST);
   6.804 +
   6.805 +	if (hw->nvm.type == e1000_nvm_flash_hw) {
   6.806 +		udelay(10);
   6.807 +		ctrl_ext = er32(CTRL_EXT);
   6.808 +		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
   6.809 +		ew32(CTRL_EXT, ctrl_ext);
   6.810 +		e1e_flush();
   6.811 +	}
   6.812 +
   6.813 +	ret_val = e1000e_get_auto_rd_done(hw);
   6.814 +	if (ret_val)
   6.815 +		/* We don't want to continue accessing MAC registers. */
   6.816 +		return ret_val;
   6.817 +
   6.818 +	/*
   6.819 +	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
   6.820 +	 * Need to wait for Phy configuration completion before accessing
   6.821 +	 * NVM and Phy.
   6.822 +	 */
   6.823 +	if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
   6.824 +		msleep(25);
   6.825 +
   6.826 +	/* Clear any pending interrupt events. */
   6.827 +	ew32(IMC, 0xffffffff);
   6.828 +	icr = er32(ICR);
   6.829 +
   6.830 +	if (hw->mac.type == e1000_82571 &&
   6.831 +		hw->dev_spec.e82571.alt_mac_addr_is_present)
   6.832 +			e1000e_set_laa_state_82571(hw, 1);
   6.833 +
   6.834 +	return 0;
   6.835 +}
   6.836 +
   6.837 +/**
   6.838 + *  e1000_init_hw_82571 - Initialize hardware
   6.839 + *  @hw: pointer to the HW structure
   6.840 + *
   6.841 + *  This inits the hardware readying it for operation.
   6.842 + **/
   6.843 +static s32 e1000_init_hw_82571(struct e1000_hw *hw)
   6.844 +{
   6.845 +	struct e1000_mac_info *mac = &hw->mac;
   6.846 +	u32 reg_data;
   6.847 +	s32 ret_val;
   6.848 +	u16 i;
   6.849 +	u16 rar_count = mac->rar_entry_count;
   6.850 +
   6.851 +	e1000_initialize_hw_bits_82571(hw);
   6.852 +
   6.853 +	/* Initialize identification LED */
   6.854 +	ret_val = e1000e_id_led_init(hw);
   6.855 +	if (ret_val) {
   6.856 +		hw_dbg(hw, "Error initializing identification LED\n");
   6.857 +		return ret_val;
   6.858 +	}
   6.859 +
   6.860 +	/* Disabling VLAN filtering */
   6.861 +	hw_dbg(hw, "Initializing the IEEE VLAN\n");
   6.862 +	e1000e_clear_vfta(hw);
   6.863 +
   6.864 +	/* Setup the receive address. */
   6.865 +	/*
   6.866 +	 * If, however, a locally administered address was assigned to the
   6.867 +	 * 82571, we must reserve a RAR for it to work around an issue where
   6.868 +	 * resetting one port will reload the MAC on the other port.
   6.869 +	 */
   6.870 +	if (e1000e_get_laa_state_82571(hw))
   6.871 +		rar_count--;
   6.872 +	e1000e_init_rx_addrs(hw, rar_count);
   6.873 +
   6.874 +	/* Zero out the Multicast HASH table */
   6.875 +	hw_dbg(hw, "Zeroing the MTA\n");
   6.876 +	for (i = 0; i < mac->mta_reg_count; i++)
   6.877 +		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
   6.878 +
   6.879 +	/* Setup link and flow control */
   6.880 +	ret_val = e1000_setup_link_82571(hw);
   6.881 +
   6.882 +	/* Set the transmit descriptor write-back policy */
   6.883 +	reg_data = er32(TXDCTL(0));
   6.884 +	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
   6.885 +		   E1000_TXDCTL_FULL_TX_DESC_WB |
   6.886 +		   E1000_TXDCTL_COUNT_DESC;
   6.887 +	ew32(TXDCTL(0), reg_data);
   6.888 +
   6.889 +	/* ...for both queues. */
   6.890 +	if (mac->type != e1000_82573 && mac->type != e1000_82574) {
   6.891 +		reg_data = er32(TXDCTL(1));
   6.892 +		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
   6.893 +			   E1000_TXDCTL_FULL_TX_DESC_WB |
   6.894 +			   E1000_TXDCTL_COUNT_DESC;
   6.895 +		ew32(TXDCTL(1), reg_data);
   6.896 +	} else {
   6.897 +		e1000e_enable_tx_pkt_filtering(hw);
   6.898 +		reg_data = er32(GCR);
   6.899 +		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
   6.900 +		ew32(GCR, reg_data);
   6.901 +	}
   6.902 +
   6.903 +	/*
   6.904 +	 * Clear all of the statistics registers (clear on read).  It is
   6.905 +	 * important that we do this after we have tried to establish link
   6.906 +	 * because the symbol error count will increment wildly if there
   6.907 +	 * is no link.
   6.908 +	 */
   6.909 +	e1000_clear_hw_cntrs_82571(hw);
   6.910 +
   6.911 +	return ret_val;
   6.912 +}
   6.913 +
   6.914 +/**
   6.915 + *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
   6.916 + *  @hw: pointer to the HW structure
   6.917 + *
   6.918 + *  Initializes required hardware-dependent bits needed for normal operation.
   6.919 + **/
   6.920 +static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
   6.921 +{
   6.922 +	u32 reg;
   6.923 +
   6.924 +	/* Transmit Descriptor Control 0 */
   6.925 +	reg = er32(TXDCTL(0));
   6.926 +	reg |= (1 << 22);
   6.927 +	ew32(TXDCTL(0), reg);
   6.928 +
   6.929 +	/* Transmit Descriptor Control 1 */
   6.930 +	reg = er32(TXDCTL(1));
   6.931 +	reg |= (1 << 22);
   6.932 +	ew32(TXDCTL(1), reg);
   6.933 +
   6.934 +	/* Transmit Arbitration Control 0 */
   6.935 +	reg = er32(TARC(0));
   6.936 +	reg &= ~(0xF << 27); /* 30:27 */
   6.937 +	switch (hw->mac.type) {
   6.938 +	case e1000_82571:
   6.939 +	case e1000_82572:
   6.940 +		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
   6.941 +		break;
   6.942 +	default:
   6.943 +		break;
   6.944 +	}
   6.945 +	ew32(TARC(0), reg);
   6.946 +
   6.947 +	/* Transmit Arbitration Control 1 */
   6.948 +	reg = er32(TARC(1));
   6.949 +	switch (hw->mac.type) {
   6.950 +	case e1000_82571:
   6.951 +	case e1000_82572:
   6.952 +		reg &= ~((1 << 29) | (1 << 30));
   6.953 +		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
   6.954 +		if (er32(TCTL) & E1000_TCTL_MULR)
   6.955 +			reg &= ~(1 << 28);
   6.956 +		else
   6.957 +			reg |= (1 << 28);
   6.958 +		ew32(TARC(1), reg);
   6.959 +		break;
   6.960 +	default:
   6.961 +		break;
   6.962 +	}
   6.963 +
   6.964 +	/* Device Control */
   6.965 +	if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
   6.966 +		reg = er32(CTRL);
   6.967 +		reg &= ~(1 << 29);
   6.968 +		ew32(CTRL, reg);
   6.969 +	}
   6.970 +
   6.971 +	/* Extended Device Control */
   6.972 +	if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
   6.973 +		reg = er32(CTRL_EXT);
   6.974 +		reg &= ~(1 << 23);
   6.975 +		reg |= (1 << 22);
   6.976 +		ew32(CTRL_EXT, reg);
   6.977 +	}
   6.978 +
   6.979 +	if (hw->mac.type == e1000_82571) {
   6.980 +		reg = er32(PBA_ECC);
   6.981 +		reg |= E1000_PBA_ECC_CORR_EN;
   6.982 +		ew32(PBA_ECC, reg);
   6.983 +	}
   6.984 +
   6.985 +	/* PCI-Ex Control Register */
   6.986 +	if (hw->mac.type == e1000_82574) {
   6.987 +		reg = er32(GCR);
   6.988 +		reg |= (1 << 22);
   6.989 +		ew32(GCR, reg);
   6.990 +	}
   6.991 +
   6.992 +	return;
   6.993 +}
   6.994 +
   6.995 +/**
   6.996 + *  e1000e_clear_vfta - Clear VLAN filter table
   6.997 + *  @hw: pointer to the HW structure
   6.998 + *
   6.999 + *  Clears the register array which contains the VLAN filter table by
  6.1000 + *  setting all the values to 0.
  6.1001 + **/
  6.1002 +void e1000e_clear_vfta(struct e1000_hw *hw)
  6.1003 +{
  6.1004 +	u32 offset;
  6.1005 +	u32 vfta_value = 0;
  6.1006 +	u32 vfta_offset = 0;
  6.1007 +	u32 vfta_bit_in_reg = 0;
  6.1008 +
  6.1009 +	if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
  6.1010 +		if (hw->mng_cookie.vlan_id != 0) {
  6.1011 +			/*
  6.1012 +			 * The VFTA is a 4096b bit-field, each identifying
  6.1013 +			 * a single VLAN ID.  The following operations
  6.1014 +			 * determine which 32b entry (i.e. offset) into the
  6.1015 +			 * array we want to set the VLAN ID (i.e. bit) of
  6.1016 +			 * the manageability unit.
  6.1017 +			 */
  6.1018 +			vfta_offset = (hw->mng_cookie.vlan_id >>
  6.1019 +				       E1000_VFTA_ENTRY_SHIFT) &
  6.1020 +				      E1000_VFTA_ENTRY_MASK;
  6.1021 +			vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
  6.1022 +					       E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
  6.1023 +		}
  6.1024 +	}
  6.1025 +	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
  6.1026 +		/*
  6.1027 +		 * If the offset we want to clear is the same offset of the
  6.1028 +		 * manageability VLAN ID, then clear all bits except that of
  6.1029 +		 * the manageability unit.
  6.1030 +		 */
  6.1031 +		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
  6.1032 +		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
  6.1033 +		e1e_flush();
  6.1034 +	}
  6.1035 +}
  6.1036 +
  6.1037 +/**
  6.1038 + *  e1000_check_mng_mode_82574 - Check manageability is enabled
  6.1039 + *  @hw: pointer to the HW structure
  6.1040 + *
  6.1041 + *  Reads the NVM Initialization Control Word 2 and returns true
  6.1042 + *  (>0) if any manageability is enabled, else false (0).
  6.1043 + **/
  6.1044 +static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
  6.1045 +{
  6.1046 +	u16 data;
  6.1047 +
  6.1048 +	e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
  6.1049 +	return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
  6.1050 +}
  6.1051 +
  6.1052 +/**
  6.1053 + *  e1000_led_on_82574 - Turn LED on
  6.1054 + *  @hw: pointer to the HW structure
  6.1055 + *
  6.1056 + *  Turn LED on.
  6.1057 + **/
  6.1058 +static s32 e1000_led_on_82574(struct e1000_hw *hw)
  6.1059 +{
  6.1060 +	u32 ctrl;
  6.1061 +	u32 i;
  6.1062 +
  6.1063 +	ctrl = hw->mac.ledctl_mode2;
  6.1064 +	if (!(E1000_STATUS_LU & er32(STATUS))) {
  6.1065 +		/*
  6.1066 +		 * If no link, then turn LED on by setting the invert bit
  6.1067 +		 * for each LED that's "on" (0x0E) in ledctl_mode2.
  6.1068 +		 */
  6.1069 +		for (i = 0; i < 4; i++)
  6.1070 +			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
  6.1071 +			    E1000_LEDCTL_MODE_LED_ON)
  6.1072 +				ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
  6.1073 +	}
  6.1074 +	ew32(LEDCTL, ctrl);
  6.1075 +
  6.1076 +	return 0;
  6.1077 +}
  6.1078 +
  6.1079 +/**
  6.1080 + *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
  6.1081 + *  @hw: pointer to the HW structure
  6.1082 + *  @mc_addr_list: array of multicast addresses to program
  6.1083 + *  @mc_addr_count: number of multicast addresses to program
  6.1084 + *  @rar_used_count: the first RAR register free to program
  6.1085 + *  @rar_count: total number of supported Receive Address Registers
  6.1086 + *
  6.1087 + *  Updates the Receive Address Registers and Multicast Table Array.
  6.1088 + *  The caller must have a packed mc_addr_list of multicast addresses.
  6.1089 + *  The parameter rar_count will usually be hw->mac.rar_entry_count
  6.1090 + *  unless there are workarounds that change this.
  6.1091 + **/
  6.1092 +static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
  6.1093 +					    u8 *mc_addr_list,
  6.1094 +					    u32 mc_addr_count,
  6.1095 +					    u32 rar_used_count,
  6.1096 +					    u32 rar_count)
  6.1097 +{
  6.1098 +	if (e1000e_get_laa_state_82571(hw))
  6.1099 +		rar_count--;
  6.1100 +
  6.1101 +	e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
  6.1102 +					   rar_used_count, rar_count);
  6.1103 +}
  6.1104 +
  6.1105 +/**
  6.1106 + *  e1000_setup_link_82571 - Setup flow control and link settings
  6.1107 + *  @hw: pointer to the HW structure
  6.1108 + *
  6.1109 + *  Determines which flow control settings to use, then configures flow
  6.1110 + *  control.  Calls the appropriate media-specific link configuration
  6.1111 + *  function.  Assuming the adapter has a valid link partner, a valid link
  6.1112 + *  should be established.  Assumes the hardware has previously been reset
  6.1113 + *  and the transmitter and receiver are not enabled.
  6.1114 + **/
  6.1115 +static s32 e1000_setup_link_82571(struct e1000_hw *hw)
  6.1116 +{
  6.1117 +	/*
  6.1118 +	 * 82573 does not have a word in the NVM to determine
  6.1119 +	 * the default flow control setting, so we explicitly
  6.1120 +	 * set it to full.
  6.1121 +	 */
  6.1122 +	if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
  6.1123 +	    hw->fc.type == e1000_fc_default)
  6.1124 +		hw->fc.type = e1000_fc_full;
  6.1125 +
  6.1126 +	return e1000e_setup_link(hw);
  6.1127 +}
  6.1128 +
  6.1129 +/**
  6.1130 + *  e1000_setup_copper_link_82571 - Configure copper link settings
  6.1131 + *  @hw: pointer to the HW structure
  6.1132 + *
  6.1133 + *  Configures the link for auto-neg or forced speed and duplex.  Then we check
  6.1134 + *  for link, once link is established calls to configure collision distance
  6.1135 + *  and flow control are called.
  6.1136 + **/
  6.1137 +static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
  6.1138 +{
  6.1139 +	u32 ctrl;
  6.1140 +	u32 led_ctrl;
  6.1141 +	s32 ret_val;
  6.1142 +
  6.1143 +	ctrl = er32(CTRL);
  6.1144 +	ctrl |= E1000_CTRL_SLU;
  6.1145 +	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  6.1146 +	ew32(CTRL, ctrl);
  6.1147 +
  6.1148 +	switch (hw->phy.type) {
  6.1149 +	case e1000_phy_m88:
  6.1150 +	case e1000_phy_bm:
  6.1151 +		ret_val = e1000e_copper_link_setup_m88(hw);
  6.1152 +		break;
  6.1153 +	case e1000_phy_igp_2:
  6.1154 +		ret_val = e1000e_copper_link_setup_igp(hw);
  6.1155 +		/* Setup activity LED */
  6.1156 +		led_ctrl = er32(LEDCTL);
  6.1157 +		led_ctrl &= IGP_ACTIVITY_LED_MASK;
  6.1158 +		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  6.1159 +		ew32(LEDCTL, led_ctrl);
  6.1160 +		break;
  6.1161 +	default:
  6.1162 +		return -E1000_ERR_PHY;
  6.1163 +		break;
  6.1164 +	}
  6.1165 +
  6.1166 +	if (ret_val)
  6.1167 +		return ret_val;
  6.1168 +
  6.1169 +	ret_val = e1000e_setup_copper_link(hw);
  6.1170 +
  6.1171 +	return ret_val;
  6.1172 +}
  6.1173 +
  6.1174 +/**
  6.1175 + *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
  6.1176 + *  @hw: pointer to the HW structure
  6.1177 + *
  6.1178 + *  Configures collision distance and flow control for fiber and serdes links.
  6.1179 + *  Upon successful setup, poll for link.
  6.1180 + **/
  6.1181 +static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
  6.1182 +{
  6.1183 +	switch (hw->mac.type) {
  6.1184 +	case e1000_82571:
  6.1185 +	case e1000_82572:
  6.1186 +		/*
  6.1187 +		 * If SerDes loopback mode is entered, there is no form
  6.1188 +		 * of reset to take the adapter out of that mode.  So we
  6.1189 +		 * have to explicitly take the adapter out of loopback
  6.1190 +		 * mode.  This prevents drivers from twiddling their thumbs
  6.1191 +		 * if another tool failed to take it out of loopback mode.
  6.1192 +		 */
  6.1193 +		ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
  6.1194 +		break;
  6.1195 +	default:
  6.1196 +		break;
  6.1197 +	}
  6.1198 +
  6.1199 +	return e1000e_setup_fiber_serdes_link(hw);
  6.1200 +}
  6.1201 +
  6.1202 +/**
  6.1203 + *  e1000_valid_led_default_82571 - Verify a valid default LED config
  6.1204 + *  @hw: pointer to the HW structure
  6.1205 + *  @data: pointer to the NVM (EEPROM)
  6.1206 + *
  6.1207 + *  Read the EEPROM for the current default LED configuration.  If the
  6.1208 + *  LED configuration is not valid, set to a valid LED configuration.
  6.1209 + **/
  6.1210 +static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
  6.1211 +{
  6.1212 +	s32 ret_val;
  6.1213 +
  6.1214 +	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
  6.1215 +	if (ret_val) {
  6.1216 +		hw_dbg(hw, "NVM Read Error\n");
  6.1217 +		return ret_val;
  6.1218 +	}
  6.1219 +
  6.1220 +	if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
  6.1221 +	    *data == ID_LED_RESERVED_F746)
  6.1222 +		*data = ID_LED_DEFAULT_82573;
  6.1223 +	else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
  6.1224 +		*data = ID_LED_DEFAULT;
  6.1225 +
  6.1226 +	return 0;
  6.1227 +}
  6.1228 +
  6.1229 +/**
  6.1230 + *  e1000e_get_laa_state_82571 - Get locally administered address state
  6.1231 + *  @hw: pointer to the HW structure
  6.1232 + *
  6.1233 + *  Retrieve and return the current locally administered address state.
  6.1234 + **/
  6.1235 +bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
  6.1236 +{
  6.1237 +	if (hw->mac.type != e1000_82571)
  6.1238 +		return 0;
  6.1239 +
  6.1240 +	return hw->dev_spec.e82571.laa_is_present;
  6.1241 +}
  6.1242 +
  6.1243 +/**
  6.1244 + *  e1000e_set_laa_state_82571 - Set locally administered address state
  6.1245 + *  @hw: pointer to the HW structure
  6.1246 + *  @state: enable/disable locally administered address
  6.1247 + *
  6.1248 + *  Enable/Disable the current locally administers address state.
  6.1249 + **/
  6.1250 +void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
  6.1251 +{
  6.1252 +	if (hw->mac.type != e1000_82571)
  6.1253 +		return;
  6.1254 +
  6.1255 +	hw->dev_spec.e82571.laa_is_present = state;
  6.1256 +
  6.1257 +	/* If workaround is activated... */
  6.1258 +	if (state)
  6.1259 +		/*
  6.1260 +		 * Hold a copy of the LAA in RAR[14] This is done so that
  6.1261 +		 * between the time RAR[0] gets clobbered and the time it
  6.1262 +		 * gets fixed, the actual LAA is in one of the RARs and no
  6.1263 +		 * incoming packets directed to this port are dropped.
  6.1264 +		 * Eventually the LAA will be in RAR[0] and RAR[14].
  6.1265 +		 */
  6.1266 +		e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
  6.1267 +}
  6.1268 +
  6.1269 +/**
  6.1270 + *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
  6.1271 + *  @hw: pointer to the HW structure
  6.1272 + *
  6.1273 + *  Verifies that the EEPROM has completed the update.  After updating the
  6.1274 + *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
  6.1275 + *  the checksum fix is not implemented, we need to set the bit and update
  6.1276 + *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
  6.1277 + *  we need to return bad checksum.
  6.1278 + **/
  6.1279 +static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
  6.1280 +{
  6.1281 +	struct e1000_nvm_info *nvm = &hw->nvm;
  6.1282 +	s32 ret_val;
  6.1283 +	u16 data;
  6.1284 +
  6.1285 +	if (nvm->type != e1000_nvm_flash_hw)
  6.1286 +		return 0;
  6.1287 +
  6.1288 +	/*
  6.1289 +	 * Check bit 4 of word 10h.  If it is 0, firmware is done updating
  6.1290 +	 * 10h-12h.  Checksum may need to be fixed.
  6.1291 +	 */
  6.1292 +	ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
  6.1293 +	if (ret_val)
  6.1294 +		return ret_val;
  6.1295 +
  6.1296 +	if (!(data & 0x10)) {
  6.1297 +		/*
  6.1298 +		 * Read 0x23 and check bit 15.  This bit is a 1
  6.1299 +		 * when the checksum has already been fixed.  If
  6.1300 +		 * the checksum is still wrong and this bit is a
  6.1301 +		 * 1, we need to return bad checksum.  Otherwise,
  6.1302 +		 * we need to set this bit to a 1 and update the
  6.1303 +		 * checksum.
  6.1304 +		 */
  6.1305 +		ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
  6.1306 +		if (ret_val)
  6.1307 +			return ret_val;
  6.1308 +
  6.1309 +		if (!(data & 0x8000)) {
  6.1310 +			data |= 0x8000;
  6.1311 +			ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
  6.1312 +			if (ret_val)
  6.1313 +				return ret_val;
  6.1314 +			ret_val = e1000e_update_nvm_checksum(hw);
  6.1315 +		}
  6.1316 +	}
  6.1317 +
  6.1318 +	return 0;
  6.1319 +}
  6.1320 +
  6.1321 +/**
  6.1322 + *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
  6.1323 + *  @hw: pointer to the HW structure
  6.1324 + *
  6.1325 + *  Clears the hardware counters by reading the counter registers.
  6.1326 + **/
  6.1327 +static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
  6.1328 +{
  6.1329 +	u32 temp;
  6.1330 +
  6.1331 +	e1000e_clear_hw_cntrs_base(hw);
  6.1332 +
  6.1333 +	temp = er32(PRC64);
  6.1334 +	temp = er32(PRC127);
  6.1335 +	temp = er32(PRC255);
  6.1336 +	temp = er32(PRC511);
  6.1337 +	temp = er32(PRC1023);
  6.1338 +	temp = er32(PRC1522);
  6.1339 +	temp = er32(PTC64);
  6.1340 +	temp = er32(PTC127);
  6.1341 +	temp = er32(PTC255);
  6.1342 +	temp = er32(PTC511);
  6.1343 +	temp = er32(PTC1023);
  6.1344 +	temp = er32(PTC1522);
  6.1345 +
  6.1346 +	temp = er32(ALGNERRC);
  6.1347 +	temp = er32(RXERRC);
  6.1348 +	temp = er32(TNCRS);
  6.1349 +	temp = er32(CEXTERR);
  6.1350 +	temp = er32(TSCTC);
  6.1351 +	temp = er32(TSCTFC);
  6.1352 +
  6.1353 +	temp = er32(MGTPRC);
  6.1354 +	temp = er32(MGTPDC);
  6.1355 +	temp = er32(MGTPTC);
  6.1356 +
  6.1357 +	temp = er32(IAC);
  6.1358 +	temp = er32(ICRXOC);
  6.1359 +
  6.1360 +	temp = er32(ICRXPTC);
  6.1361 +	temp = er32(ICRXATC);
  6.1362 +	temp = er32(ICTXPTC);
  6.1363 +	temp = er32(ICTXATC);
  6.1364 +	temp = er32(ICTXQEC);
  6.1365 +	temp = er32(ICTXQMTC);
  6.1366 +	temp = er32(ICRXDMTC);
  6.1367 +}
  6.1368 +
  6.1369 +static struct e1000_mac_operations e82571_mac_ops = {
  6.1370 +	/* .check_mng_mode: mac type dependent */
  6.1371 +	/* .check_for_link: media type dependent */
  6.1372 +	.cleanup_led		= e1000e_cleanup_led_generic,
  6.1373 +	.clear_hw_cntrs		= e1000_clear_hw_cntrs_82571,
  6.1374 +	.get_bus_info		= e1000e_get_bus_info_pcie,
  6.1375 +	/* .get_link_up_info: media type dependent */
  6.1376 +	/* .led_on: mac type dependent */
  6.1377 +	.led_off		= e1000e_led_off_generic,
  6.1378 +	.update_mc_addr_list	= e1000_update_mc_addr_list_82571,
  6.1379 +	.reset_hw		= e1000_reset_hw_82571,
  6.1380 +	.init_hw		= e1000_init_hw_82571,
  6.1381 +	.setup_link		= e1000_setup_link_82571,
  6.1382 +	/* .setup_physical_interface: media type dependent */
  6.1383 +};
  6.1384 +
  6.1385 +static struct e1000_phy_operations e82_phy_ops_igp = {
  6.1386 +	.acquire_phy		= e1000_get_hw_semaphore_82571,
  6.1387 +	.check_reset_block	= e1000e_check_reset_block_generic,
  6.1388 +	.commit_phy		= NULL,
  6.1389 +	.force_speed_duplex	= e1000e_phy_force_speed_duplex_igp,
  6.1390 +	.get_cfg_done		= e1000_get_cfg_done_82571,
  6.1391 +	.get_cable_length	= e1000e_get_cable_length_igp_2,
  6.1392 +	.get_phy_info		= e1000e_get_phy_info_igp,
  6.1393 +	.read_phy_reg		= e1000e_read_phy_reg_igp,
  6.1394 +	.release_phy		= e1000_put_hw_semaphore_82571,
  6.1395 +	.reset_phy		= e1000e_phy_hw_reset_generic,
  6.1396 +	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
  6.1397 +	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
  6.1398 +	.write_phy_reg		= e1000e_write_phy_reg_igp,
  6.1399 +};
  6.1400 +
  6.1401 +static struct e1000_phy_operations e82_phy_ops_m88 = {
  6.1402 +	.acquire_phy		= e1000_get_hw_semaphore_82571,
  6.1403 +	.check_reset_block	= e1000e_check_reset_block_generic,
  6.1404 +	.commit_phy		= e1000e_phy_sw_reset,
  6.1405 +	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
  6.1406 +	.get_cfg_done		= e1000e_get_cfg_done,
  6.1407 +	.get_cable_length	= e1000e_get_cable_length_m88,
  6.1408 +	.get_phy_info		= e1000e_get_phy_info_m88,
  6.1409 +	.read_phy_reg		= e1000e_read_phy_reg_m88,
  6.1410 +	.release_phy		= e1000_put_hw_semaphore_82571,
  6.1411 +	.reset_phy		= e1000e_phy_hw_reset_generic,
  6.1412 +	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
  6.1413 +	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
  6.1414 +	.write_phy_reg		= e1000e_write_phy_reg_m88,
  6.1415 +};
  6.1416 +
  6.1417 +static struct e1000_phy_operations e82_phy_ops_bm = {
  6.1418 +	.acquire_phy		= e1000_get_hw_semaphore_82571,
  6.1419 +	.check_reset_block	= e1000e_check_reset_block_generic,
  6.1420 +	.commit_phy		= e1000e_phy_sw_reset,
  6.1421 +	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
  6.1422 +	.get_cfg_done		= e1000e_get_cfg_done,
  6.1423 +	.get_cable_length	= e1000e_get_cable_length_m88,
  6.1424 +	.get_phy_info		= e1000e_get_phy_info_m88,
  6.1425 +	.read_phy_reg		= e1000e_read_phy_reg_bm2,
  6.1426 +	.release_phy		= e1000_put_hw_semaphore_82571,
  6.1427 +	.reset_phy		= e1000e_phy_hw_reset_generic,
  6.1428 +	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
  6.1429 +	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
  6.1430 +	.write_phy_reg		= e1000e_write_phy_reg_bm2,
  6.1431 +};
  6.1432 +
  6.1433 +static struct e1000_nvm_operations e82571_nvm_ops = {
  6.1434 +	.acquire_nvm		= e1000_acquire_nvm_82571,
  6.1435 +	.read_nvm		= e1000e_read_nvm_eerd,
  6.1436 +	.release_nvm		= e1000_release_nvm_82571,
  6.1437 +	.update_nvm		= e1000_update_nvm_checksum_82571,
  6.1438 +	.valid_led_default	= e1000_valid_led_default_82571,
  6.1439 +	.validate_nvm		= e1000_validate_nvm_checksum_82571,
  6.1440 +	.write_nvm		= e1000_write_nvm_82571,
  6.1441 +};
  6.1442 +
  6.1443 +struct e1000_info e1000_82571_info = {
  6.1444 +	.mac			= e1000_82571,
  6.1445 +	.flags			= FLAG_HAS_HW_VLAN_FILTER
  6.1446 +				  | FLAG_HAS_JUMBO_FRAMES
  6.1447 +				  | FLAG_HAS_WOL
  6.1448 +				  | FLAG_APME_IN_CTRL3
  6.1449 +				  | FLAG_RX_CSUM_ENABLED
  6.1450 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
  6.1451 +				  | FLAG_HAS_SMART_POWER_DOWN
  6.1452 +				  | FLAG_RESET_OVERWRITES_LAA /* errata */
  6.1453 +				  | FLAG_TARC_SPEED_MODE_BIT /* errata */
  6.1454 +				  | FLAG_APME_CHECK_PORT_B,
  6.1455 +	.pba			= 38,
  6.1456 +	.get_variants		= e1000_get_variants_82571,
  6.1457 +	.mac_ops		= &e82571_mac_ops,
  6.1458 +	.phy_ops		= &e82_phy_ops_igp,
  6.1459 +	.nvm_ops		= &e82571_nvm_ops,
  6.1460 +};
  6.1461 +
  6.1462 +struct e1000_info e1000_82572_info = {
  6.1463 +	.mac			= e1000_82572,
  6.1464 +	.flags			= FLAG_HAS_HW_VLAN_FILTER
  6.1465 +				  | FLAG_HAS_JUMBO_FRAMES
  6.1466 +				  | FLAG_HAS_WOL
  6.1467 +				  | FLAG_APME_IN_CTRL3
  6.1468 +				  | FLAG_RX_CSUM_ENABLED
  6.1469 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
  6.1470 +				  | FLAG_TARC_SPEED_MODE_BIT, /* errata */
  6.1471 +	.pba			= 38,
  6.1472 +	.get_variants		= e1000_get_variants_82571,
  6.1473 +	.mac_ops		= &e82571_mac_ops,
  6.1474 +	.phy_ops		= &e82_phy_ops_igp,
  6.1475 +	.nvm_ops		= &e82571_nvm_ops,
  6.1476 +};
  6.1477 +
  6.1478 +struct e1000_info e1000_82573_info = {
  6.1479 +	.mac			= e1000_82573,
  6.1480 +	.flags			= FLAG_HAS_HW_VLAN_FILTER
  6.1481 +				  | FLAG_HAS_JUMBO_FRAMES
  6.1482 +				  | FLAG_HAS_WOL
  6.1483 +				  | FLAG_APME_IN_CTRL3
  6.1484 +				  | FLAG_RX_CSUM_ENABLED
  6.1485 +				  | FLAG_HAS_SMART_POWER_DOWN
  6.1486 +				  | FLAG_HAS_AMT
  6.1487 +				  | FLAG_HAS_ERT
  6.1488 +				  | FLAG_HAS_SWSM_ON_LOAD,
  6.1489 +	.pba			= 20,
  6.1490 +	.get_variants		= e1000_get_variants_82571,
  6.1491 +	.mac_ops		= &e82571_mac_ops,
  6.1492 +	.phy_ops		= &e82_phy_ops_m88,
  6.1493 +	.nvm_ops		= &e82571_nvm_ops,
  6.1494 +};
  6.1495 +
  6.1496 +struct e1000_info e1000_82574_info = {
  6.1497 +	.mac			= e1000_82574,
  6.1498 +	.flags			= FLAG_HAS_HW_VLAN_FILTER
  6.1499 +				  | FLAG_HAS_MSIX
  6.1500 +				  | FLAG_HAS_JUMBO_FRAMES
  6.1501 +				  | FLAG_HAS_WOL
  6.1502 +				  | FLAG_APME_IN_CTRL3
  6.1503 +				  | FLAG_RX_CSUM_ENABLED
  6.1504 +				  | FLAG_HAS_SMART_POWER_DOWN
  6.1505 +				  | FLAG_HAS_AMT
  6.1506 +				  | FLAG_HAS_CTRLEXT_ON_LOAD,
  6.1507 +	.pba			= 20,
  6.1508 +	.get_variants		= e1000_get_variants_82571,
  6.1509 +	.mac_ops		= &e82571_mac_ops,
  6.1510 +	.phy_ops		= &e82_phy_ops_bm,
  6.1511 +	.nvm_ops		= &e82571_nvm_ops,
  6.1512 +};
  6.1513 +
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/drivers/net/e1000e/Makefile	Tue Feb 17 11:25:22 2009 +0000
     7.3 @@ -0,0 +1,37 @@
     7.4 +################################################################################
     7.5 +#
     7.6 +# Intel PRO/1000 Linux driver
     7.7 +# Copyright(c) 1999 - 2008 Intel Corporation.
     7.8 +#
     7.9 +# This program is free software; you can redistribute it and/or modify it
    7.10 +# under the terms and conditions of the GNU General Public License,
    7.11 +# version 2, as published by the Free Software Foundation.
    7.12 +#
    7.13 +# This program is distributed in the hope it will be useful, but WITHOUT
    7.14 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    7.15 +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    7.16 +# more details.
    7.17 +#
    7.18 +# You should have received a copy of the GNU General Public License along with
    7.19 +# this program; if not, write to the Free Software Foundation, Inc.,
    7.20 +# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    7.21 +#
    7.22 +# The full GNU General Public License is included in this distribution in
    7.23 +# the file called "COPYING".
    7.24 +#
    7.25 +# Contact Information:
    7.26 +# Linux NICS <linux.nics@intel.com>
    7.27 +# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    7.28 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    7.29 +#
    7.30 +################################################################################
    7.31 +
    7.32 +#
    7.33 +# Makefile for the Intel(R) PRO/1000 ethernet driver
    7.34 +#
    7.35 +
    7.36 +obj-$(CONFIG_E1000E) += e1000e.o
    7.37 +
    7.38 +e1000e-objs := 82571.o ich8lan.o es2lan.o \
    7.39 +	       lib.o phy.o param.o ethtool.o netdev.o
    7.40 +
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/drivers/net/e1000e/defines.h	Tue Feb 17 11:25:22 2009 +0000
     8.3 @@ -0,0 +1,784 @@
     8.4 +/*******************************************************************************
     8.5 +
     8.6 +  Intel PRO/1000 Linux driver
     8.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
     8.8 +
     8.9 +  This program is free software; you can redistribute it and/or modify it
    8.10 +  under the terms and conditions of the GNU General Public License,
    8.11 +  version 2, as published by the Free Software Foundation.
    8.12 +
    8.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    8.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    8.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    8.16 +  more details.
    8.17 +
    8.18 +  You should have received a copy of the GNU General Public License along with
    8.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    8.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    8.21 +
    8.22 +  The full GNU General Public License is included in this distribution in
    8.23 +  the file called "COPYING".
    8.24 +
    8.25 +  Contact Information:
    8.26 +  Linux NICS <linux.nics@intel.com>
    8.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    8.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    8.29 +
    8.30 +*******************************************************************************/
    8.31 +
    8.32 +#ifndef _E1000_DEFINES_H_
    8.33 +#define _E1000_DEFINES_H_
    8.34 +
    8.35 +#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
    8.36 +#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
    8.37 +#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
    8.38 +#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
    8.39 +#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
    8.40 +#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
    8.41 +#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
    8.42 +#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
    8.43 +#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
    8.44 +#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
    8.45 +#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
    8.46 +#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
    8.47 +#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
    8.48 +#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
    8.49 +#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
    8.50 +#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
    8.51 +#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
    8.52 +#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
    8.53 +
    8.54 +/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
    8.55 +#define REQ_TX_DESCRIPTOR_MULTIPLE  8
    8.56 +#define REQ_RX_DESCRIPTOR_MULTIPLE  8
    8.57 +
    8.58 +/* Definitions for power management and wakeup registers */
    8.59 +/* Wake Up Control */
    8.60 +#define E1000_WUC_APME       0x00000001 /* APM Enable */
    8.61 +#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
    8.62 +
    8.63 +/* Wake Up Filter Control */
    8.64 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
    8.65 +#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
    8.66 +#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
    8.67 +#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
    8.68 +#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
    8.69 +#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
    8.70 +
    8.71 +/* Extended Device Control */
    8.72 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
    8.73 +#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
    8.74 +#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
    8.75 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
    8.76 +#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
    8.77 +#define E1000_CTRL_EXT_EIAME          0x01000000
    8.78 +#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
    8.79 +#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */
    8.80 +#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers after IMS clear */
    8.81 +#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
    8.82 +
    8.83 +/* Receive Descriptor bit definitions */
    8.84 +#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
    8.85 +#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
    8.86 +#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
    8.87 +#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
    8.88 +#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
    8.89 +#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
    8.90 +#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
    8.91 +#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
    8.92 +#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
    8.93 +#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
    8.94 +#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
    8.95 +#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
    8.96 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
    8.97 +
    8.98 +#define E1000_RXDEXT_STATERR_CE    0x01000000
    8.99 +#define E1000_RXDEXT_STATERR_SE    0x02000000
   8.100 +#define E1000_RXDEXT_STATERR_SEQ   0x04000000
   8.101 +#define E1000_RXDEXT_STATERR_CXE   0x10000000
   8.102 +#define E1000_RXDEXT_STATERR_RXE   0x80000000
   8.103 +
   8.104 +/* mask to determine if packets should be dropped due to frame errors */
   8.105 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
   8.106 +    E1000_RXD_ERR_CE  |                \
   8.107 +    E1000_RXD_ERR_SE  |                \
   8.108 +    E1000_RXD_ERR_SEQ |                \
   8.109 +    E1000_RXD_ERR_CXE |                \
   8.110 +    E1000_RXD_ERR_RXE)
   8.111 +
   8.112 +/* Same mask, but for extended and packet split descriptors */
   8.113 +#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
   8.114 +    E1000_RXDEXT_STATERR_CE  |            \
   8.115 +    E1000_RXDEXT_STATERR_SE  |            \
   8.116 +    E1000_RXDEXT_STATERR_SEQ |            \
   8.117 +    E1000_RXDEXT_STATERR_CXE |            \
   8.118 +    E1000_RXDEXT_STATERR_RXE)
   8.119 +
   8.120 +#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
   8.121 +
   8.122 +/* Management Control */
   8.123 +#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
   8.124 +#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
   8.125 +#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
   8.126 +#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
   8.127 +#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
   8.128 +/* Enable MAC address filtering */
   8.129 +#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
   8.130 +/* Enable MNG packets to host memory */
   8.131 +#define E1000_MANC_EN_MNG2HOST   0x00200000
   8.132 +
   8.133 +/* Receive Control */
   8.134 +#define E1000_RCTL_EN             0x00000002    /* enable */
   8.135 +#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
   8.136 +#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
   8.137 +#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
   8.138 +#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
   8.139 +#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
   8.140 +#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
   8.141 +#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
   8.142 +#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
   8.143 +#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min threshold size */
   8.144 +#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
   8.145 +#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
   8.146 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
   8.147 +#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */
   8.148 +#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */
   8.149 +#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */
   8.150 +#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */
   8.151 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
   8.152 +#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */
   8.153 +#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */
   8.154 +#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */
   8.155 +#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
   8.156 +#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
   8.157 +#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
   8.158 +#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
   8.159 +#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
   8.160 +
   8.161 +/*
   8.162 + * Use byte values for the following shift parameters
   8.163 + * Usage:
   8.164 + *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
   8.165 + *                  E1000_PSRCTL_BSIZE0_MASK) |
   8.166 + *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
   8.167 + *                  E1000_PSRCTL_BSIZE1_MASK) |
   8.168 + *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
   8.169 + *                  E1000_PSRCTL_BSIZE2_MASK) |
   8.170 + *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
   8.171 + *                  E1000_PSRCTL_BSIZE3_MASK))
   8.172 + * where value0 = [128..16256],  default=256
   8.173 + *       value1 = [1024..64512], default=4096
   8.174 + *       value2 = [0..64512],    default=4096
   8.175 + *       value3 = [0..64512],    default=0
   8.176 + */
   8.177 +
   8.178 +#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
   8.179 +#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
   8.180 +#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
   8.181 +#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
   8.182 +
   8.183 +#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
   8.184 +#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
   8.185 +#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
   8.186 +#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
   8.187 +
   8.188 +/* SWFW_SYNC Definitions */
   8.189 +#define E1000_SWFW_EEP_SM   0x1
   8.190 +#define E1000_SWFW_PHY0_SM  0x2
   8.191 +#define E1000_SWFW_PHY1_SM  0x4
   8.192 +#define E1000_SWFW_CSR_SM   0x8
   8.193 +
   8.194 +/* Device Control */
   8.195 +#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
   8.196 +#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
   8.197 +#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
   8.198 +#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
   8.199 +#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
   8.200 +#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
   8.201 +#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
   8.202 +#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
   8.203 +#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
   8.204 +#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
   8.205 +#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
   8.206 +#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
   8.207 +#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
   8.208 +#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
   8.209 +#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
   8.210 +#define E1000_CTRL_RST      0x04000000  /* Global reset */
   8.211 +#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
   8.212 +#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
   8.213 +#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
   8.214 +#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
   8.215 +
   8.216 +/*
   8.217 + * Bit definitions for the Management Data IO (MDIO) and Management Data
   8.218 + * Clock (MDC) pins in the Device Control Register.
   8.219 + */
   8.220 +
   8.221 +/* Device Status */
   8.222 +#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
   8.223 +#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
   8.224 +#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
   8.225 +#define E1000_STATUS_FUNC_SHIFT 2
   8.226 +#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
   8.227 +#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
   8.228 +#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
   8.229 +#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
   8.230 +#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
   8.231 +#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */
   8.232 +#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
   8.233 +
   8.234 +/* Constants used to interpret the masked PCI-X bus speed. */
   8.235 +
   8.236 +#define HALF_DUPLEX 1
   8.237 +#define FULL_DUPLEX 2
   8.238 +
   8.239 +
   8.240 +#define ADVERTISE_10_HALF                 0x0001
   8.241 +#define ADVERTISE_10_FULL                 0x0002
   8.242 +#define ADVERTISE_100_HALF                0x0004
   8.243 +#define ADVERTISE_100_FULL                0x0008
   8.244 +#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
   8.245 +#define ADVERTISE_1000_FULL               0x0020
   8.246 +
   8.247 +/* 1000/H is not supported, nor spec-compliant. */
   8.248 +#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
   8.249 +				ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
   8.250 +						     ADVERTISE_1000_FULL)
   8.251 +#define E1000_ALL_NOT_GIG      ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
   8.252 +				ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
   8.253 +#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
   8.254 +#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
   8.255 +#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
   8.256 +
   8.257 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
   8.258 +
   8.259 +/* LED Control */
   8.260 +#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
   8.261 +#define E1000_LEDCTL_LED0_MODE_SHIFT      0
   8.262 +#define E1000_LEDCTL_LED0_IVRT            0x00000040
   8.263 +#define E1000_LEDCTL_LED0_BLINK           0x00000080
   8.264 +
   8.265 +#define E1000_LEDCTL_MODE_LED_ON        0xE
   8.266 +#define E1000_LEDCTL_MODE_LED_OFF       0xF
   8.267 +
   8.268 +/* Transmit Descriptor bit definitions */
   8.269 +#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
   8.270 +#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
   8.271 +#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
   8.272 +#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
   8.273 +#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
   8.274 +#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
   8.275 +#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
   8.276 +#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
   8.277 +#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
   8.278 +#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
   8.279 +#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
   8.280 +#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
   8.281 +#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
   8.282 +#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
   8.283 +#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
   8.284 +#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
   8.285 +#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
   8.286 +#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
   8.287 +#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
   8.288 +
   8.289 +/* Transmit Control */
   8.290 +#define E1000_TCTL_EN     0x00000002    /* enable Tx */
   8.291 +#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
   8.292 +#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
   8.293 +#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
   8.294 +#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
   8.295 +#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
   8.296 +
   8.297 +/* Transmit Arbitration Count */
   8.298 +
   8.299 +/* SerDes Control */
   8.300 +#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
   8.301 +
   8.302 +/* Receive Checksum Control */
   8.303 +#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
   8.304 +#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
   8.305 +
   8.306 +/* Header split receive */
   8.307 +#define E1000_RFCTL_ACK_DIS             0x00001000
   8.308 +#define E1000_RFCTL_EXTEN               0x00008000
   8.309 +#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
   8.310 +#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
   8.311 +
   8.312 +/* Collision related configuration parameters */
   8.313 +#define E1000_COLLISION_THRESHOLD       15
   8.314 +#define E1000_CT_SHIFT                  4
   8.315 +#define E1000_COLLISION_DISTANCE        63
   8.316 +#define E1000_COLD_SHIFT                12
   8.317 +
   8.318 +/* Default values for the transmit IPG register */
   8.319 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
   8.320 +
   8.321 +#define E1000_TIPG_IPGT_MASK  0x000003FF
   8.322 +
   8.323 +#define DEFAULT_82543_TIPG_IPGR1 8
   8.324 +#define E1000_TIPG_IPGR1_SHIFT  10
   8.325 +
   8.326 +#define DEFAULT_82543_TIPG_IPGR2 6
   8.327 +#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
   8.328 +#define E1000_TIPG_IPGR2_SHIFT  20
   8.329 +
   8.330 +#define MAX_JUMBO_FRAME_SIZE    0x3F00
   8.331 +
   8.332 +/* Extended Configuration Control and Size */
   8.333 +#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
   8.334 +#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
   8.335 +#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
   8.336 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
   8.337 +#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
   8.338 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
   8.339 +#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
   8.340 +
   8.341 +#define E1000_PHY_CTRL_D0A_LPLU           0x00000002
   8.342 +#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
   8.343 +#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
   8.344 +#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
   8.345 +
   8.346 +#define E1000_KABGTXD_BGSQLBIAS           0x00050000
   8.347 +
   8.348 +/* PBA constants */
   8.349 +#define E1000_PBA_8K  0x0008    /* 8KB */
   8.350 +#define E1000_PBA_16K 0x0010    /* 16KB */
   8.351 +
   8.352 +#define E1000_PBS_16K E1000_PBA_16K
   8.353 +
   8.354 +#define IFS_MAX       80
   8.355 +#define IFS_MIN       40
   8.356 +#define IFS_RATIO     4
   8.357 +#define IFS_STEP      10
   8.358 +#define MIN_NUM_XMITS 1000
   8.359 +
   8.360 +/* SW Semaphore Register */
   8.361 +#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
   8.362 +#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
   8.363 +#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
   8.364 +
   8.365 +/* Interrupt Cause Read */
   8.366 +#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
   8.367 +#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
   8.368 +#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */
   8.369 +#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
   8.370 +#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
   8.371 +#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */
   8.372 +#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
   8.373 +#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
   8.374 +#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
   8.375 +#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
   8.376 +#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
   8.377 +
   8.378 +/* PBA ECC Register */
   8.379 +#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
   8.380 +#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
   8.381 +#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */
   8.382 +#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
   8.383 +#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
   8.384 +
   8.385 +/*
   8.386 + * This defines the bits that are set in the Interrupt Mask
   8.387 + * Set/Read Register.  Each bit is documented below:
   8.388 + *   o RXT0   = Receiver Timer Interrupt (ring 0)
   8.389 + *   o TXDW   = Transmit Descriptor Written Back
   8.390 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
   8.391 + *   o RXSEQ  = Receive Sequence Error
   8.392 + *   o LSC    = Link Status Change
   8.393 + */
   8.394 +#define IMS_ENABLE_MASK ( \
   8.395 +    E1000_IMS_RXT0   |    \
   8.396 +    E1000_IMS_TXDW   |    \
   8.397 +    E1000_IMS_RXDMT0 |    \
   8.398 +    E1000_IMS_RXSEQ  |    \
   8.399 +    E1000_IMS_LSC)
   8.400 +
   8.401 +/* Interrupt Mask Set */
   8.402 +#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
   8.403 +#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
   8.404 +#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
   8.405 +#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
   8.406 +#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
   8.407 +#define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */
   8.408 +#define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */
   8.409 +#define E1000_IMS_TXQ0      E1000_ICR_TXQ0      /* Tx Queue 0 Interrupt */
   8.410 +#define E1000_IMS_TXQ1      E1000_ICR_TXQ1      /* Tx Queue 1 Interrupt */
   8.411 +#define E1000_IMS_OTHER     E1000_ICR_OTHER     /* Other Interrupts */
   8.412 +
   8.413 +/* Interrupt Cause Set */
   8.414 +#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
   8.415 +#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
   8.416 +#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
   8.417 +#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
   8.418 +
   8.419 +/* Transmit Descriptor Control */
   8.420 +#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
   8.421 +#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
   8.422 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
   8.423 +#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
   8.424 +/* Enable the counting of desc. still to be processed. */
   8.425 +#define E1000_TXDCTL_COUNT_DESC 0x00400000
   8.426 +
   8.427 +/* Flow Control Constants */
   8.428 +#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
   8.429 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
   8.430 +#define FLOW_CONTROL_TYPE         0x8808
   8.431 +
   8.432 +/* 802.1q VLAN Packet Size */
   8.433 +#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
   8.434 +
   8.435 +/* Receive Address */
   8.436 +/*
   8.437 + * Number of high/low register pairs in the RAR. The RAR (Receive Address
   8.438 + * Registers) holds the directed and multicast addresses that we monitor.
   8.439 + * Technically, we have 16 spots.  However, we reserve one of these spots
   8.440 + * (RAR[15]) for our directed address used by controllers with
   8.441 + * manageability enabled, allowing us room for 15 multicast addresses.
   8.442 + */
   8.443 +#define E1000_RAR_ENTRIES     15
   8.444 +#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
   8.445 +
   8.446 +/* Error Codes */
   8.447 +#define E1000_ERR_NVM      1
   8.448 +#define E1000_ERR_PHY      2
   8.449 +#define E1000_ERR_CONFIG   3
   8.450 +#define E1000_ERR_PARAM    4
   8.451 +#define E1000_ERR_MAC_INIT 5
   8.452 +#define E1000_ERR_PHY_TYPE 6
   8.453 +#define E1000_ERR_RESET   9
   8.454 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10
   8.455 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11
   8.456 +#define E1000_BLK_PHY_RESET   12
   8.457 +#define E1000_ERR_SWFW_SYNC 13
   8.458 +#define E1000_NOT_IMPLEMENTED 14
   8.459 +
   8.460 +/* Loop limit on how long we wait for auto-negotiation to complete */
   8.461 +#define FIBER_LINK_UP_LIMIT               50
   8.462 +#define COPPER_LINK_UP_LIMIT              10
   8.463 +#define PHY_AUTO_NEG_LIMIT                45
   8.464 +#define PHY_FORCE_LIMIT                   20
   8.465 +/* Number of 100 microseconds we wait for PCI Express master disable */
   8.466 +#define MASTER_DISABLE_TIMEOUT      800
   8.467 +/* Number of milliseconds we wait for PHY configuration done after MAC reset */
   8.468 +#define PHY_CFG_TIMEOUT             100
   8.469 +/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
   8.470 +#define MDIO_OWNERSHIP_TIMEOUT      10
   8.471 +/* Number of milliseconds for NVM auto read done after MAC reset. */
   8.472 +#define AUTO_READ_DONE_TIMEOUT      10
   8.473 +
   8.474 +/* Flow Control */
   8.475 +#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
   8.476 +
   8.477 +/* Transmit Configuration Word */
   8.478 +#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
   8.479 +#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
   8.480 +#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
   8.481 +#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
   8.482 +#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
   8.483 +
   8.484 +/* Receive Configuration Word */
   8.485 +#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
   8.486 +#define E1000_RXCW_C          0x20000000        /* Receive config */
   8.487 +#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
   8.488 +
   8.489 +/* PCI Express Control */
   8.490 +#define E1000_GCR_RXD_NO_SNOOP          0x00000001
   8.491 +#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
   8.492 +#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
   8.493 +#define E1000_GCR_TXD_NO_SNOOP          0x00000008
   8.494 +#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
   8.495 +#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
   8.496 +
   8.497 +#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
   8.498 +			   E1000_GCR_RXDSCW_NO_SNOOP      | \
   8.499 +			   E1000_GCR_RXDSCR_NO_SNOOP      | \
   8.500 +			   E1000_GCR_TXD_NO_SNOOP         | \
   8.501 +			   E1000_GCR_TXDSCW_NO_SNOOP      | \
   8.502 +			   E1000_GCR_TXDSCR_NO_SNOOP)
   8.503 +
   8.504 +/* PHY Control Register */
   8.505 +#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
   8.506 +#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
   8.507 +#define MII_CR_POWER_DOWN       0x0800  /* Power down */
   8.508 +#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
   8.509 +#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
   8.510 +#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
   8.511 +#define MII_CR_SPEED_1000       0x0040
   8.512 +#define MII_CR_SPEED_100        0x2000
   8.513 +#define MII_CR_SPEED_10         0x0000
   8.514 +
   8.515 +/* PHY Status Register */
   8.516 +#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
   8.517 +#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
   8.518 +
   8.519 +/* Autoneg Advertisement Register */
   8.520 +#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
   8.521 +#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
   8.522 +#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
   8.523 +#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
   8.524 +#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
   8.525 +#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
   8.526 +
   8.527 +/* Link Partner Ability Register (Base Page) */
   8.528 +#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
   8.529 +#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
   8.530 +
   8.531 +/* Autoneg Expansion Register */
   8.532 +#define NWAY_ER_LP_NWAY_CAPS     0x0001 /* LP has Auto Neg Capability */
   8.533 +
   8.534 +/* 1000BASE-T Control Register */
   8.535 +#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
   8.536 +#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
   8.537 +					/* 0=DTE device */
   8.538 +#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
   8.539 +					/* 0=Configure PHY as Slave */
   8.540 +#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
   8.541 +					/* 0=Automatic Master/Slave config */
   8.542 +
   8.543 +/* 1000BASE-T Status Register */
   8.544 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
   8.545 +#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
   8.546 +
   8.547 +
   8.548 +/* PHY 1000 MII Register/Bit Definitions */
   8.549 +/* PHY Registers defined by IEEE */
   8.550 +#define PHY_CONTROL      0x00 /* Control Register */
   8.551 +#define PHY_STATUS       0x01 /* Status Register */
   8.552 +#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
   8.553 +#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
   8.554 +#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
   8.555 +#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
   8.556 +#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
   8.557 +#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
   8.558 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
   8.559 +#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
   8.560 +
   8.561 +/* NVM Control */
   8.562 +#define E1000_EECD_SK        0x00000001 /* NVM Clock */
   8.563 +#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
   8.564 +#define E1000_EECD_DI        0x00000004 /* NVM Data In */
   8.565 +#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
   8.566 +#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
   8.567 +#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
   8.568 +#define E1000_EECD_PRES      0x00000100 /* NVM Present */
   8.569 +#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
   8.570 +/* NVM Addressing bits based on type (0-small, 1-large) */
   8.571 +#define E1000_EECD_ADDR_BITS 0x00000400
   8.572 +#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
   8.573 +#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
   8.574 +#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
   8.575 +#define E1000_EECD_SIZE_EX_SHIFT     11
   8.576 +#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
   8.577 +#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
   8.578 +#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
   8.579 +
   8.580 +#define E1000_NVM_RW_REG_DATA   16   /* Offset to data in NVM read/write registers */
   8.581 +#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
   8.582 +#define E1000_NVM_RW_REG_START  1    /* Start operation */
   8.583 +#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
   8.584 +#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
   8.585 +#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
   8.586 +#define E1000_FLASH_UPDATES  2000
   8.587 +
   8.588 +/* NVM Word Offsets */
   8.589 +#define NVM_ID_LED_SETTINGS        0x0004
   8.590 +#define NVM_INIT_CONTROL2_REG      0x000F
   8.591 +#define NVM_INIT_CONTROL3_PORT_B   0x0014
   8.592 +#define NVM_INIT_3GIO_3            0x001A
   8.593 +#define NVM_INIT_CONTROL3_PORT_A   0x0024
   8.594 +#define NVM_CFG                    0x0012
   8.595 +#define NVM_ALT_MAC_ADDR_PTR       0x0037
   8.596 +#define NVM_CHECKSUM_REG           0x003F
   8.597 +
   8.598 +#define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
   8.599 +#define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
   8.600 +
   8.601 +/* Mask bits for fields in Word 0x0f of the NVM */
   8.602 +#define NVM_WORD0F_PAUSE_MASK       0x3000
   8.603 +#define NVM_WORD0F_PAUSE            0x1000
   8.604 +#define NVM_WORD0F_ASM_DIR          0x2000
   8.605 +
   8.606 +/* Mask bits for fields in Word 0x1a of the NVM */
   8.607 +#define NVM_WORD1A_ASPM_MASK  0x000C
   8.608 +
   8.609 +/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
   8.610 +#define NVM_SUM                    0xBABA
   8.611 +
   8.612 +/* PBA (printed board assembly) number words */
   8.613 +#define NVM_PBA_OFFSET_0           8
   8.614 +#define NVM_PBA_OFFSET_1           9
   8.615 +
   8.616 +#define NVM_WORD_SIZE_BASE_SHIFT   6
   8.617 +
   8.618 +/* NVM Commands - SPI */
   8.619 +#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
   8.620 +#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
   8.621 +#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
   8.622 +#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
   8.623 +#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
   8.624 +#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
   8.625 +
   8.626 +/* SPI NVM Status Register */
   8.627 +#define NVM_STATUS_RDY_SPI         0x01
   8.628 +
   8.629 +/* Word definitions for ID LED Settings */
   8.630 +#define ID_LED_RESERVED_0000 0x0000
   8.631 +#define ID_LED_RESERVED_FFFF 0xFFFF
   8.632 +#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
   8.633 +			      (ID_LED_OFF1_OFF2 <<  8) | \
   8.634 +			      (ID_LED_DEF1_DEF2 <<  4) | \
   8.635 +			      (ID_LED_DEF1_DEF2))
   8.636 +#define ID_LED_DEF1_DEF2     0x1
   8.637 +#define ID_LED_DEF1_ON2      0x2
   8.638 +#define ID_LED_DEF1_OFF2     0x3
   8.639 +#define ID_LED_ON1_DEF2      0x4
   8.640 +#define ID_LED_ON1_ON2       0x5
   8.641 +#define ID_LED_ON1_OFF2      0x6
   8.642 +#define ID_LED_OFF1_DEF2     0x7
   8.643 +#define ID_LED_OFF1_ON2      0x8
   8.644 +#define ID_LED_OFF1_OFF2     0x9
   8.645 +
   8.646 +#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
   8.647 +#define IGP_ACTIVITY_LED_ENABLE 0x0300
   8.648 +#define IGP_LED3_MODE           0x07000000
   8.649 +
   8.650 +/* PCI/PCI-X/PCI-EX Config space */
   8.651 +#define PCI_HEADER_TYPE_REGISTER     0x0E
   8.652 +#define PCIE_LINK_STATUS             0x12
   8.653 +
   8.654 +#define PCI_HEADER_TYPE_MULTIFUNC    0x80
   8.655 +#define PCIE_LINK_WIDTH_MASK         0x3F0
   8.656 +#define PCIE_LINK_WIDTH_SHIFT        4
   8.657 +
   8.658 +#define PHY_REVISION_MASK      0xFFFFFFF0
   8.659 +#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
   8.660 +#define MAX_PHY_MULTI_PAGE_REG 0xF
   8.661 +
   8.662 +/* Bit definitions for valid PHY IDs. */
   8.663 +/*
   8.664 + * I = Integrated
   8.665 + * E = External
   8.666 + */
   8.667 +#define M88E1000_E_PHY_ID    0x01410C50
   8.668 +#define M88E1000_I_PHY_ID    0x01410C30
   8.669 +#define M88E1011_I_PHY_ID    0x01410C20
   8.670 +#define IGP01E1000_I_PHY_ID  0x02A80380
   8.671 +#define M88E1111_I_PHY_ID    0x01410CC0
   8.672 +#define GG82563_E_PHY_ID     0x01410CA0
   8.673 +#define IGP03E1000_E_PHY_ID  0x02A80390
   8.674 +#define IFE_E_PHY_ID         0x02A80330
   8.675 +#define IFE_PLUS_E_PHY_ID    0x02A80320
   8.676 +#define IFE_C_E_PHY_ID       0x02A80310
   8.677 +#define BME1000_E_PHY_ID     0x01410CB0
   8.678 +#define BME1000_E_PHY_ID_R2  0x01410CB1
   8.679 +
   8.680 +/* M88E1000 Specific Registers */
   8.681 +#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
   8.682 +#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
   8.683 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
   8.684 +
   8.685 +#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
   8.686 +#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
   8.687 +
   8.688 +/* M88E1000 PHY Specific Control Register */
   8.689 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
   8.690 +#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
   8.691 +					       /* Manual MDI configuration */
   8.692 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
   8.693 +/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
   8.694 +#define M88E1000_PSCR_AUTO_X_1000T     0x0040
   8.695 +/* Auto crossover enabled all speeds */
   8.696 +#define M88E1000_PSCR_AUTO_X_MODE      0x0060
   8.697 +/*
   8.698 + * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
   8.699 + * 0=Normal 10BASE-T Rx Threshold
   8.700 + */
   8.701 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
   8.702 +
   8.703 +/* M88E1000 PHY Specific Status Register */
   8.704 +#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
   8.705 +#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
   8.706 +#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
   8.707 +/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
   8.708 +#define M88E1000_PSSR_CABLE_LENGTH       0x0380
   8.709 +#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
   8.710 +#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
   8.711 +
   8.712 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
   8.713 +
   8.714 +/*
   8.715 + * Number of times we will attempt to autonegotiate before downshifting if we
   8.716 + * are the master
   8.717 + */
   8.718 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
   8.719 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
   8.720 +/*
   8.721 + * Number of times we will attempt to autonegotiate before downshifting if we
   8.722 + * are the slave
   8.723 + */
   8.724 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
   8.725 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
   8.726 +#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
   8.727 +
   8.728 +/* M88EC018 Rev 2 specific DownShift settings */
   8.729 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
   8.730 +#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
   8.731 +
   8.732 +/* BME1000 PHY Specific Control Register */
   8.733 +#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
   8.734 +
   8.735 +
   8.736 +#define PHY_PAGE_SHIFT 5
   8.737 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
   8.738 +                           ((reg) & MAX_PHY_REG_ADDRESS))
   8.739 +
   8.740 +/*
   8.741 + * Bits...
   8.742 + * 15-5: page
   8.743 + * 4-0: register offset
   8.744 + */
   8.745 +#define GG82563_PAGE_SHIFT        5
   8.746 +#define GG82563_REG(page, reg)    \
   8.747 +	(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
   8.748 +#define GG82563_MIN_ALT_REG       30
   8.749 +
   8.750 +/* GG82563 Specific Registers */
   8.751 +#define GG82563_PHY_SPEC_CTRL           \
   8.752 +	GG82563_REG(0, 16) /* PHY Specific Control */
   8.753 +#define GG82563_PHY_PAGE_SELECT         \
   8.754 +	GG82563_REG(0, 22) /* Page Select */
   8.755 +#define GG82563_PHY_SPEC_CTRL_2         \
   8.756 +	GG82563_REG(0, 26) /* PHY Specific Control 2 */
   8.757 +#define GG82563_PHY_PAGE_SELECT_ALT     \
   8.758 +	GG82563_REG(0, 29) /* Alternate Page Select */
   8.759 +
   8.760 +#define GG82563_PHY_MAC_SPEC_CTRL       \
   8.761 +	GG82563_REG(2, 21) /* MAC Specific Control Register */
   8.762 +
   8.763 +#define GG82563_PHY_DSP_DISTANCE    \
   8.764 +	GG82563_REG(5, 26) /* DSP Distance */
   8.765 +
   8.766 +/* Page 193 - Port Control Registers */
   8.767 +#define GG82563_PHY_KMRN_MODE_CTRL   \
   8.768 +	GG82563_REG(193, 16) /* Kumeran Mode Control */
   8.769 +#define GG82563_PHY_PWR_MGMT_CTRL       \
   8.770 +	GG82563_REG(193, 20) /* Power Management Control */
   8.771 +
   8.772 +/* Page 194 - KMRN Registers */
   8.773 +#define GG82563_PHY_INBAND_CTRL         \
   8.774 +	GG82563_REG(194, 18) /* Inband Control */
   8.775 +
   8.776 +/* MDI Control */
   8.777 +#define E1000_MDIC_REG_SHIFT 16
   8.778 +#define E1000_MDIC_PHY_SHIFT 21
   8.779 +#define E1000_MDIC_OP_WRITE  0x04000000
   8.780 +#define E1000_MDIC_OP_READ   0x08000000
   8.781 +#define E1000_MDIC_READY     0x10000000
   8.782 +#define E1000_MDIC_ERROR     0x40000000
   8.783 +
   8.784 +/* SerDes Control */
   8.785 +#define E1000_GEN_POLL_TIMEOUT          640
   8.786 +
   8.787 +#endif /* _E1000_DEFINES_H_ */
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/drivers/net/e1000e/e1000.h	Tue Feb 17 11:25:22 2009 +0000
     9.3 @@ -0,0 +1,567 @@
     9.4 +/*******************************************************************************
     9.5 +
     9.6 +  Intel PRO/1000 Linux driver
     9.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
     9.8 +
     9.9 +  This program is free software; you can redistribute it and/or modify it
    9.10 +  under the terms and conditions of the GNU General Public License,
    9.11 +  version 2, as published by the Free Software Foundation.
    9.12 +
    9.13 +  This program is distributed in the hope it will be useful, but WITHOUT
    9.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    9.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    9.16 +  more details.
    9.17 +
    9.18 +  You should have received a copy of the GNU General Public License along with
    9.19 +  this program; if not, write to the Free Software Foundation, Inc.,
    9.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
    9.21 +
    9.22 +  The full GNU General Public License is included in this distribution in
    9.23 +  the file called "COPYING".
    9.24 +
    9.25 +  Contact Information:
    9.26 +  Linux NICS <linux.nics@intel.com>
    9.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
    9.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    9.29 +
    9.30 +*******************************************************************************/
    9.31 +
    9.32 +/* Linux PRO/1000 Ethernet Driver main header file */
    9.33 +
    9.34 +#ifndef _E1000_H_
    9.35 +#define _E1000_H_
    9.36 +
    9.37 +#include <linux/types.h>
    9.38 +#include <linux/timer.h>
    9.39 +#include <linux/workqueue.h>
    9.40 +#include <linux/io.h>
    9.41 +#include <linux/netdevice.h>
    9.42 +
    9.43 +#include "e1000_compat.h"
    9.44 +#include "hw.h"
    9.45 +
    9.46 +struct e1000_info;
    9.47 +
    9.48 +#define e_printk(level, adapter, format, arg...) \
    9.49 +	printk(level "%s: " format, \
    9.50 +	       adapter->netdev->name, ## arg)
    9.51 +
    9.52 +#ifdef DEBUG
    9.53 +#define e_dbg(format, arg...) \
    9.54 +	e_printk(KERN_DEBUG , adapter, format, ## arg)
    9.55 +#else
    9.56 +#define e_dbg(format, arg...) do { (void)(adapter); } while (0)
    9.57 +#endif
    9.58 +
    9.59 +#define e_err(format, arg...) \
    9.60 +	e_printk(KERN_ERR, adapter, format, ## arg)
    9.61 +#define e_info(format, arg...) \
    9.62 +	e_printk(KERN_INFO, adapter, format, ## arg)
    9.63 +#define e_warn(format, arg...) \
    9.64 +	e_printk(KERN_WARNING, adapter, format, ## arg)
    9.65 +#define e_notice(format, arg...) \
    9.66 +	e_printk(KERN_NOTICE, adapter, format, ## arg)
    9.67 +
    9.68 +
    9.69 +/* Interrupt modes, as used by the IntMode paramter */
    9.70 +#define E1000E_INT_MODE_LEGACY		0
    9.71 +#define E1000E_INT_MODE_MSI		1
    9.72 +#define E1000E_INT_MODE_MSIX		2
    9.73 +
    9.74 +/* Tx/Rx descriptor defines */
    9.75 +#define E1000_DEFAULT_TXD		256
    9.76 +#define E1000_MAX_TXD			4096
    9.77 +#define E1000_MIN_TXD			64
    9.78 +
    9.79 +#define E1000_DEFAULT_RXD		256
    9.80 +#define E1000_MAX_RXD			4096
    9.81 +#define E1000_MIN_RXD			64
    9.82 +
    9.83 +#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
    9.84 +#define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
    9.85 +
    9.86 +/* Early Receive defines */
    9.87 +#define E1000_ERT_2048			0x100
    9.88 +
    9.89 +#define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
    9.90 +
    9.91 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
    9.92 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
    9.93 +#define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
    9.94 +
    9.95 +#define AUTO_ALL_MODES			0
    9.96 +#define E1000_EEPROM_APME		0x0400
    9.97 +
    9.98 +#define E1000_MNG_VLAN_NONE		(-1)
    9.99 +
   9.100 +/* Number of packet split data buffers (not including the header buffer) */
   9.101 +#define PS_PAGE_BUFFERS			(MAX_PS_BUFFERS - 1)
   9.102 +
   9.103 +enum e1000_boards {
   9.104 +	board_82571,
   9.105 +	board_82572,
   9.106 +	board_82573,
   9.107 +	board_82574,
   9.108 +	board_80003es2lan,
   9.109 +	board_ich8lan,
   9.110 +	board_ich9lan,
   9.111 +	board_ich10lan,
   9.112 +};
   9.113 +
   9.114 +struct e1000_queue_stats {
   9.115 +	u64 packets;
   9.116 +	u64 bytes;
   9.117 +};
   9.118 +
   9.119 +struct e1000_ps_page {
   9.120 +	struct page *page;
   9.121 +	u64 dma; /* must be u64 - written to hw */
   9.122 +};
   9.123 +
   9.124 +/*
   9.125 + * wrappers around a pointer to a socket buffer,
   9.126 + * so a DMA handle can be stored along with the buffer
   9.127 + */
   9.128 +struct e1000_buffer {
   9.129 +	dma_addr_t dma;
   9.130 +	struct sk_buff *skb;
   9.131 +	union {
   9.132 +		/* Tx */
   9.133 +		struct {
   9.134 +			unsigned long time_stamp;
   9.135 +			u16 length;
   9.136 +			u16 next_to_watch;
   9.137 +		};
   9.138 +		/* Rx */
   9.139 +		/* arrays of page information for packet split */
   9.140 +		struct e1000_ps_page *ps_pages;
   9.141 +	};
   9.142 +	struct page *page;
   9.143 +};
   9.144 +
   9.145 +struct e1000_ring {
   9.146 +	void *desc;			/* pointer to ring memory  */
   9.147 +	dma_addr_t dma;			/* phys address of ring    */
   9.148 +	unsigned int size;		/* length of ring in bytes */
   9.149 +	unsigned int count;		/* number of desc. in ring */
   9.150 +
   9.151 +	u16 next_to_use;
   9.152 +	u16 next_to_clean;
   9.153 +
   9.154 +	u16 head;
   9.155 +	u16 tail;
   9.156 +
   9.157 +	/* array of buffer information structs */
   9.158 +	struct e1000_buffer *buffer_info;
   9.159 +
   9.160 +	char name[IFNAMSIZ + 5];
   9.161 +	u32 ims_val;
   9.162 +	u32 itr_val;
   9.163 +	u16 itr_register;
   9.164 +	int set_itr;
   9.165 +
   9.166 +	struct sk_buff *rx_skb_top;
   9.167 +
   9.168 +	struct e1000_queue_stats stats;
   9.169 +};
   9.170 +
   9.171 +/* PHY register snapshot values */
   9.172 +struct e1000_phy_regs {
   9.173 +	u16 bmcr;		/* basic mode control register    */
   9.174 +	u16 bmsr;		/* basic mode status register     */
   9.175 +	u16 advertise;		/* auto-negotiation advertisement */
   9.176 +	u16 lpa;		/* link partner ability register  */
   9.177 +	u16 expansion;		/* auto-negotiation expansion reg */
   9.178 +	u16 ctrl1000;		/* 1000BASE-T control register    */
   9.179 +	u16 stat1000;		/* 1000BASE-T status register     */
   9.180 +	u16 estatus;		/* extended status register       */
   9.181 +};
   9.182 +
   9.183 +/* board specific private data structure */
   9.184 +struct e1000_adapter {
   9.185 +	struct timer_list watchdog_timer;
   9.186 +	struct timer_list phy_info_timer;
   9.187 +	struct timer_list blink_timer;
   9.188 +
   9.189 +	struct work_struct reset_task;
   9.190 +	struct work_struct watchdog_task;
   9.191 +
   9.192 +	const struct e1000_info *ei;
   9.193 +
   9.194 +	struct vlan_group *vlgrp;
   9.195 +	u32 bd_number;
   9.196 +	u32 rx_buffer_len;
   9.197 +	u16 mng_vlan_id;
   9.198 +	u16 link_speed;
   9.199 +	u16 link_duplex;
   9.200 +
   9.201 +	spinlock_t tx_queue_lock; /* prevent concurrent tail updates */
   9.202 +
   9.203 +	/* track device up/down/testing state */
   9.204 +	unsigned long state;
   9.205 +
   9.206 +	/* Interrupt Throttle Rate */
   9.207 +	u32 itr;
   9.208 +	u32 itr_setting;
   9.209 +	u16 tx_itr;
   9.210 +	u16 rx_itr;
   9.211 +
   9.212 +	/*
   9.213 +	 * Tx
   9.214 +	 */
   9.215 +	struct e1000_ring *tx_ring /* One per active queue */
   9.216 +						____cacheline_aligned_in_smp;
   9.217 +
   9.218 +	unsigned long tx_queue_len;
   9.219 +	unsigned int restart_queue;
   9.220 +	u32 txd_cmd;
   9.221 +
   9.222 +	bool detect_tx_hung;
   9.223 +	u8 tx_timeout_factor;
   9.224 +
   9.225 +	u32 tx_int_delay;
   9.226 +	u32 tx_abs_int_delay;
   9.227 +
   9.228 +	unsigned int total_tx_bytes;
   9.229 +	unsigned int total_tx_packets;
   9.230 +	unsigned int total_rx_bytes;
   9.231 +	unsigned int total_rx_packets;
   9.232 +
   9.233 +	/* Tx stats */
   9.234 +	u64 tpt_old;
   9.235 +	u64 colc_old;
   9.236 +	u32 gotc;
   9.237 +	u64 gotc_old;
   9.238 +	u32 tx_timeout_count;
   9.239 +	u32 tx_fifo_head;
   9.240 +	u32 tx_head_addr;
   9.241 +	u32 tx_fifo_size;
   9.242 +	u32 tx_dma_failed;
   9.243 +
   9.244 +	/*
   9.245 +	 * Rx
   9.246 +	 */
   9.247 +	bool (*clean_rx) (struct e1000_adapter *adapter,
   9.248 +			  int *work_done, int work_to_do)
   9.249 +						____cacheline_aligned_in_smp;
   9.250 +	void (*alloc_rx_buf) (struct e1000_adapter *adapter,
   9.251 +			      int cleaned_count);
   9.252 +	struct e1000_ring *rx_ring;
   9.253 +
   9.254 +	u32 rx_int_delay;
   9.255 +	u32 rx_abs_int_delay;
   9.256 +
   9.257 +	/* Rx stats */
   9.258 +	u64 hw_csum_err;
   9.259 +	u64 hw_csum_good;
   9.260 +	u64 rx_hdr_split;
   9.261 +	u32 gorc;
   9.262 +	u64 gorc_old;
   9.263 +	u32 alloc_rx_buff_failed;
   9.264 +	u32 rx_dma_failed;
   9.265 +
   9.266 +	unsigned int rx_ps_pages;
   9.267 +	u16 rx_ps_bsize0;
   9.268 +	u32 max_frame_size;
   9.269 +	u32 min_frame_size;
   9.270 +
   9.271 +	/* OS defined structs */
   9.272 +	struct net_device *netdev;
   9.273 +	struct pci_dev *pdev;
   9.274 +	struct net_device_stats net_stats;
   9.275 +	spinlock_t stats_lock;      /* prevent concurrent stats updates */
   9.276 +
   9.277 +	/* structs defined in e1000_hw.h */
   9.278 +	struct e1000_hw hw;
   9.279 +
   9.280 +	struct e1000_hw_stats stats;
   9.281 +	struct e1000_phy_info phy_info;
   9.282 +	struct e1000_phy_stats phy_stats;
   9.283 +
   9.284 +	/* Snapshot of PHY registers */
   9.285 +	struct e1000_phy_regs phy_regs;
   9.286 +
   9.287 +	struct e1000_ring test_tx_ring;
   9.288 +	struct e1000_ring test_rx_ring;
   9.289 +	u32 test_icr;
   9.290 +
   9.291 +	u32 msg_enable;
   9.292 +	struct msix_entry *msix_entries;
   9.293 +	int int_mode;
   9.294 +	u32 eiac_mask;
   9.295 +
   9.296 +	u32 eeprom_wol;
   9.297 +	u32 wol;
   9.298 +	u32 pba;
   9.299 +
   9.300 +	bool fc_autoneg;
   9.301 +
   9.302 +	unsigned long led_status;
   9.303 +
   9.304 +	unsigned int flags;
   9.305 +};
   9.306 +
   9.307 +struct e1000_info {
   9.308 +	enum e1000_mac_type	mac;
   9.309 +	unsigned int		flags;
   9.310 +	u32			pba;
   9.311 +	s32			(*get_variants)(struct e1000_adapter *);
   9.312 +	struct e1000_mac_operations *mac_ops;
   9.313 +	struct e1000_phy_operations *phy_ops;
   9.314 +	struct e1000_nvm_operations *nvm_ops;
   9.315 +};
   9.316 +
   9.317 +/* hardware capability, feature, and workaround flags */
   9.318 +#define FLAG_HAS_AMT                      (1 << 0)
   9.319 +#define FLAG_HAS_FLASH                    (1 << 1)
   9.320 +#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
   9.321 +#define FLAG_HAS_WOL                      (1 << 3)
   9.322 +#define FLAG_HAS_ERT                      (1 << 4)
   9.323 +#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
   9.324 +#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
   9.325 +#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
   9.326 +#define FLAG_READ_ONLY_NVM                (1 << 8)
   9.327 +#define FLAG_IS_ICH                       (1 << 9)
   9.328 +#define FLAG_HAS_MSIX                     (1 << 10)
   9.329 +#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
   9.330 +#define FLAG_IS_QUAD_PORT_A               (1 << 12)
   9.331 +#define FLAG_IS_QUAD_PORT                 (1 << 13)
   9.332 +#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)
   9.333 +#define FLAG_APME_IN_WUC                  (1 << 15)
   9.334 +#define FLAG_APME_IN_CTRL3                (1 << 16)
   9.335 +#define FLAG_APME_CHECK_PORT_B            (1 << 17)
   9.336 +#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
   9.337 +#define FLAG_NO_WAKE_UCAST                (1 << 19)
   9.338 +#define FLAG_MNG_PT_ENABLED               (1 << 20)
   9.339 +#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
   9.340 +#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
   9.341 +#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
   9.342 +#define FLAG_RX_NEEDS_RESTART             (1 << 24)
   9.343 +#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
   9.344 +#define FLAG_SMART_POWER_DOWN             (1 << 26)
   9.345 +#define FLAG_MSI_ENABLED                  (1 << 27)
   9.346 +#define FLAG_RX_CSUM_ENABLED              (1 << 28)
   9.347 +#define FLAG_TSO_FORCE                    (1 << 29)
   9.348 +#define FLAG_MSI_TEST_FAILED              (1 << 30)
   9.349 +#define FLAG_RX_RESTART_NOW               (1 << 31)
   9.350 +
   9.351 +#define E1000_RX_DESC_PS(R, i)	    \
   9.352 +	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
   9.353 +#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
   9.354 +#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
   9.355 +#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
   9.356 +#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
   9.357 +
   9.358 +enum e1000_state_t {
   9.359 +	__E1000_TESTING,
   9.360 +	__E1000_RESETTING,
   9.361 +	__E1000_DOWN
   9.362 +};
   9.363 +
   9.364 +enum latency_range {
   9.365 +	lowest_latency = 0,
   9.366 +	low_latency = 1,
   9.367 +	bulk_latency = 2,
   9.368 +	latency_invalid = 255
   9.369 +};
   9.370 +
   9.371 +extern char e1000e_driver_name[];
   9.372 +extern const char e1000e_driver_version[];
   9.373 +
   9.374 +extern void e1000e_check_options(struct e1000_adapter *adapter);
   9.375 +extern void e1000e_set_ethtool_ops(struct net_device *netdev);
   9.376 +
   9.377 +extern int e1000e_up(struct e1000_adapter *adapter);
   9.378 +extern void e1000e_down(struct e1000_adapter *adapter);
   9.379 +extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
   9.380 +extern void e1000e_reset(struct e1000_adapter *adapter);
   9.381 +extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
   9.382 +extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
   9.383 +extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
   9.384 +extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
   9.385 +extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
   9.386 +extern void e1000e_update_stats(struct e1000_adapter *adapter);
   9.387 +extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
   9.388 +extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
   9.389 +
   9.390 +extern unsigned int copybreak;
   9.391 +
   9.392 +extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
   9.393 +
   9.394 +extern struct e1000_info e1000_82571_info;
   9.395 +extern struct e1000_info e1000_82572_info;
   9.396 +extern struct e1000_info e1000_82573_info;
   9.397 +extern struct e1000_info e1000_82574_info;
   9.398 +extern struct e1000_info e1000_ich8_info;
   9.399 +extern struct e1000_info e1000_ich9_info;
   9.400 +extern struct e1000_info e1000_ich10_info;
   9.401 +extern struct e1000_info e1000_es2_info;
   9.402 +
   9.403 +extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
   9.404 +
   9.405 +extern s32  e1000e_commit_phy(struct e1000_hw *hw);
   9.406 +
   9.407 +extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
   9.408 +
   9.409 +extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
   9.410 +extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
   9.411 +
   9.412 +extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
   9.413 +extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
   9.414 +						 bool state);
   9.415 +extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
   9.416 +extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
   9.417 +extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
   9.418 +
   9.419 +extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
   9.420 +extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
   9.421 +extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
   9.422 +extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
   9.423 +extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
   9.424 +extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
   9.425 +extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
   9.426 +extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
   9.427 +extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
   9.428 +extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
   9.429 +extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
   9.430 +extern s32 e1000e_id_led_init(struct e1000_hw *hw);
   9.431 +extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
   9.432 +extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
   9.433 +extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
   9.434 +extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
   9.435 +extern s32 e1000e_setup_link(struct e1000_hw *hw);
   9.436 +extern void e1000e_clear_vfta(struct e1000_hw *hw);
   9.437 +extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
   9.438 +extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
   9.439 +					       u8 *mc_addr_list,
   9.440 +					       u32 mc_addr_count,
   9.441 +					       u32 rar_used_count,
   9.442 +					       u32 rar_count);
   9.443 +extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
   9.444 +extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
   9.445 +extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
   9.446 +extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
   9.447 +extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
   9.448 +extern void e1000e_config_collision_dist(struct e1000_hw *hw);
   9.449 +extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
   9.450 +extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
   9.451 +extern s32 e1000e_blink_led(struct e1000_hw *hw);
   9.452 +extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
   9.453 +extern void e1000e_reset_adaptive(struct e1000_hw *hw);
   9.454 +extern void e1000e_update_adaptive(struct e1000_hw *hw);
   9.455 +
   9.456 +extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
   9.457 +extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
   9.458 +extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
   9.459 +extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
   9.460 +extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
   9.461 +extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
   9.462 +extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
   9.463 +extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
   9.464 +extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
   9.465 +extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
   9.466 +extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
   9.467 +extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
   9.468 +extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
   9.469 +extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
   9.470 +extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
   9.471 +extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
   9.472 +extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
   9.473 +extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
   9.474 +extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
   9.475 +extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
   9.476 +extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
   9.477 +extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
   9.478 +extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
   9.479 +extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
   9.480 +extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
   9.481 +extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
   9.482 +extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
   9.483 +extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
   9.484 +extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
   9.485 +			       u32 usec_interval, bool *success);
   9.486 +extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
   9.487 +extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
   9.488 +extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
   9.489 +extern s32 e1000e_check_downshift(struct e1000_hw *hw);
   9.490 +
   9.491 +static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
   9.492 +{
   9.493 +	return hw->phy.ops.reset_phy(hw);
   9.494 +}
   9.495 +
   9.496 +static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
   9.497 +{
   9.498 +	return hw->phy.ops.check_reset_block(hw);
   9.499 +}
   9.500 +
   9.501 +static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
   9.502 +{
   9.503 +	return hw->phy.ops.read_phy_reg(hw, offset, data);
   9.504 +}
   9.505 +
   9.506 +static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
   9.507 +{
   9.508 +	return hw->phy.ops.write_phy_reg(hw, offset, data);
   9.509 +}
   9.510 +
   9.511 +static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
   9.512 +{
   9.513 +	return hw->phy.ops.get_cable_length(hw);
   9.514 +}
   9.515 +
   9.516 +extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
   9.517 +extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
   9.518 +extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
   9.519 +extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
   9.520 +extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
   9.521 +extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
   9.522 +extern void e1000e_release_nvm(struct e1000_hw *hw);
   9.523 +extern void e1000e_reload_nvm(struct e1000_hw *hw);
   9.524 +extern s32 e1000e_read_mac_addr(struct e1000_hw *hw);
   9.525 +
   9.526 +static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
   9.527 +{
   9.528 +	return hw->nvm.ops.validate_nvm(hw);
   9.529 +}
   9.530 +
   9.531 +static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
   9.532 +{
   9.533 +	return hw->nvm.ops.update_nvm(hw);
   9.534 +}
   9.535 +
   9.536 +static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
   9.537 +{
   9.538 +	return hw->nvm.ops.read_nvm(hw, offset, words, data);
   9.539 +}
   9.540 +
   9.541 +static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
   9.542 +{
   9.543 +	return hw->nvm.ops.write_nvm(hw, offset, words, data);
   9.544 +}
   9.545 +
   9.546 +static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
   9.547 +{
   9.548 +	return hw->phy.ops.get_phy_info(hw);
   9.549 +}
   9.550 +
   9.551 +static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
   9.552 +{
   9.553 +	return hw->mac.ops.check_mng_mode(hw);
   9.554 +}
   9.555 +
   9.556 +extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
   9.557 +extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
   9.558 +extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
   9.559 +
   9.560 +static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
   9.561 +{
   9.562 +	return readl(hw->hw_addr + reg);
   9.563 +}
   9.564 +
   9.565 +static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
   9.566 +{
   9.567 +	writel(val, hw->hw_addr + reg);
   9.568 +}
   9.569 +
   9.570 +#endif /* _E1000_H_ */
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/drivers/net/e1000e/e1000_compat.h	Tue Feb 17 11:25:22 2009 +0000
    10.3 @@ -0,0 +1,69 @@
    10.4 +#ifndef __E1000E_COMPAT_H__
    10.5 +#define __E1000E_COMPAT_H__
    10.6 +
    10.7 +#include <linux/if_vlan.h>
    10.8 +#include <linux/pci.h>
    10.9 +
   10.10 +typedef unsigned int bool;
   10.11 +
   10.12 +#define ETH_FCS_LEN               4
   10.13 +
   10.14 +static inline struct net_device *vlan_group_get_device(struct vlan_group *vg,
   10.15 +						       int vlan_id)
   10.16 +{
   10.17 +	return vg->vlan_devices[vlan_id];
   10.18 +}
   10.19 +
   10.20 +static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id,
   10.21 +					 struct net_device *dev)
   10.22 +{
   10.23 +	vg->vlan_devices[vlan_id] = NULL;
   10.24 +}
   10.25 +/* generic boolean compatibility */
   10.26 +#define true 1
   10.27 +#define false 0
   10.28 +
   10.29 +/*
   10.30 + * backport csum_unfold and datatypes from 2.6.25
   10.31 + */
   10.32 +typedef __u16 __bitwise __sum16;
   10.33 +typedef __u32 __bitwise __wsum;
   10.34 +
   10.35 +static inline __wsum csum_unfold(__sum16 n)
   10.36 +{
   10.37 +    return (__force __wsum)n;
   10.38 +};
   10.39 +
   10.40 +#ifndef CHECKSUM_PARTIAL
   10.41 +#define CHECKSUM_PARTIAL CHECKSUM_HW
   10.42 +#define CHECKSUM_COMPLETE CHECKSUM_HW
   10.43 +#endif
   10.44 +
   10.45 +#define skb_tail_pointer(skb) skb->tail
   10.46 +#define skb_copy_to_linear_data_offset(skb, offset, from, len) \
   10.47 +    memcpy(skb->data + offset, from, len)
   10.48 +
   10.49 +
   10.50 +static inline int pci_channel_offline(struct pci_dev *pdev)
   10.51 +{
   10.52 +    return (pdev->error_state != pci_channel_io_normal);
   10.53 +}
   10.54 +#ifndef round_jiffies
   10.55 +#define round_jiffies(x) x
   10.56 +#endif
   10.57 +
   10.58 +#define tcp_hdr(skb) (skb->h.th)
   10.59 +#define tcp_hdrlen(skb) (skb->h.th->doff << 2)
   10.60 +#define skb_transport_offset(skb) (skb->h.raw - skb->data)
   10.61 +#define skb_transport_header(skb) (skb->h.raw)
   10.62 +#define ipv6_hdr(skb) (skb->nh.ipv6h)
   10.63 +#define ip_hdr(skb) (skb->nh.iph)
   10.64 +#define skb_network_offset(skb) (skb->nh.raw - skb->data)
   10.65 +
   10.66 +#ifndef PCI_VDEVICE
   10.67 +#define PCI_VDEVICE(ven, dev)        \
   10.68 +    PCI_VENDOR_ID_##ven, (dev),  \
   10.69 +    PCI_ANY_ID, PCI_ANY_ID, 0, 0
   10.70 +#endif
   10.71 +
   10.72 +#endif 
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/drivers/net/e1000e/es2lan.c	Tue Feb 17 11:25:22 2009 +0000
    11.3 @@ -0,0 +1,1310 @@
    11.4 +/*******************************************************************************
    11.5 +
    11.6 +  Intel PRO/1000 Linux driver
    11.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
    11.8 +
    11.9 +  This program is free software; you can redistribute it and/or modify it
   11.10 +  under the terms and conditions of the GNU General Public License,
   11.11 +  version 2, as published by the Free Software Foundation.
   11.12 +
   11.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   11.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   11.16 +  more details.
   11.17 +
   11.18 +  You should have received a copy of the GNU General Public License along with
   11.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   11.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   11.21 +
   11.22 +  The full GNU General Public License is included in this distribution in
   11.23 +  the file called "COPYING".
   11.24 +
   11.25 +  Contact Information:
   11.26 +  Linux NICS <linux.nics@intel.com>
   11.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   11.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   11.29 +
   11.30 +*******************************************************************************/
   11.31 +
   11.32 +/*
   11.33 + * 80003ES2LAN Gigabit Ethernet Controller (Copper)
   11.34 + * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
   11.35 + */
   11.36 +
   11.37 +#include <linux/netdevice.h>
   11.38 +#include <linux/ethtool.h>
   11.39 +#include <linux/delay.h>
   11.40 +#include <linux/pci.h>
   11.41 +
   11.42 +#include "e1000.h"
   11.43 +
   11.44 +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	 0x00
   11.45 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	 0x02
   11.46 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	 0x10
   11.47 +#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	 0x1F
   11.48 +
   11.49 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	 0x0008
   11.50 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	 0x0800
   11.51 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	 0x0010
   11.52 +
   11.53 +#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
   11.54 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	 0x0000
   11.55 +#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		 0x2000
   11.56 +
   11.57 +#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
   11.58 +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	 0x00010000
   11.59 +
   11.60 +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	 0x8
   11.61 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	 0x9
   11.62 +
   11.63 +/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
   11.64 +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	 0x0002 /* 1=Reversal Disab. */
   11.65 +#define GG82563_PSCR_CROSSOVER_MODE_MASK	 0x0060
   11.66 +#define GG82563_PSCR_CROSSOVER_MODE_MDI		 0x0000 /* 00=Manual MDI */
   11.67 +#define GG82563_PSCR_CROSSOVER_MODE_MDIX	 0x0020 /* 01=Manual MDIX */
   11.68 +#define GG82563_PSCR_CROSSOVER_MODE_AUTO	 0x0060 /* 11=Auto crossover */
   11.69 +
   11.70 +/* PHY Specific Control Register 2 (Page 0, Register 26) */
   11.71 +#define GG82563_PSCR2_REVERSE_AUTO_NEG		 0x2000
   11.72 +						/* 1=Reverse Auto-Negotiation */
   11.73 +
   11.74 +/* MAC Specific Control Register (Page 2, Register 21) */
   11.75 +/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
   11.76 +#define GG82563_MSCR_TX_CLK_MASK		 0x0007
   11.77 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5		 0x0004
   11.78 +#define GG82563_MSCR_TX_CLK_100MBPS_25		 0x0005
   11.79 +#define GG82563_MSCR_TX_CLK_1000MBPS_25		 0x0007
   11.80 +
   11.81 +#define GG82563_MSCR_ASSERT_CRS_ON_TX		 0x0010 /* 1=Assert */
   11.82 +
   11.83 +/* DSP Distance Register (Page 5, Register 26) */
   11.84 +#define GG82563_DSPD_CABLE_LENGTH		 0x0007 /* 0 = <50M
   11.85 +							   1 = 50-80M
   11.86 +							   2 = 80-110M
   11.87 +							   3 = 110-140M
   11.88 +							   4 = >140M */
   11.89 +
   11.90 +/* Kumeran Mode Control Register (Page 193, Register 16) */
   11.91 +#define GG82563_KMCR_PASS_FALSE_CARRIER		 0x0800
   11.92 +
   11.93 +/* Max number of times Kumeran read/write should be validated */
   11.94 +#define GG82563_MAX_KMRN_RETRY  0x5
   11.95 +
   11.96 +/* Power Management Control Register (Page 193, Register 20) */
   11.97 +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	 0x0001
   11.98 +					   /* 1=Enable SERDES Electrical Idle */
   11.99 +
  11.100 +/* In-Band Control Register (Page 194, Register 18) */
  11.101 +#define GG82563_ICR_DIS_PADDING			 0x0010 /* Disable Padding */
  11.102 +
  11.103 +/*
  11.104 + * A table for the GG82563 cable length where the range is defined
  11.105 + * with a lower bound at "index" and the upper bound at
  11.106 + * "index + 5".
  11.107 + */
  11.108 +static const u16 e1000_gg82563_cable_length_table[] =
  11.109 +	 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  11.110 +
  11.111 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  11.112 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  11.113 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  11.114 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  11.115 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  11.116 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  11.117 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  11.118 +
  11.119 +/**
  11.120 + *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  11.121 + *  @hw: pointer to the HW structure
  11.122 + *
  11.123 + *  This is a function pointer entry point called by the api module.
  11.124 + **/
  11.125 +static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  11.126 +{
  11.127 +	struct e1000_phy_info *phy = &hw->phy;
  11.128 +	s32 ret_val;
  11.129 +
  11.130 +	if (hw->phy.media_type != e1000_media_type_copper) {
  11.131 +		phy->type	= e1000_phy_none;
  11.132 +		return 0;
  11.133 +	}
  11.134 +
  11.135 +	phy->addr		= 1;
  11.136 +	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  11.137 +	phy->reset_delay_us      = 100;
  11.138 +	phy->type		= e1000_phy_gg82563;
  11.139 +
  11.140 +	/* This can only be done after all function pointers are setup. */
  11.141 +	ret_val = e1000e_get_phy_id(hw);
  11.142 +
  11.143 +	/* Verify phy id */
  11.144 +	if (phy->id != GG82563_E_PHY_ID)
  11.145 +		return -E1000_ERR_PHY;
  11.146 +
  11.147 +	return ret_val;
  11.148 +}
  11.149 +
  11.150 +/**
  11.151 + *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  11.152 + *  @hw: pointer to the HW structure
  11.153 + *
  11.154 + *  This is a function pointer entry point called by the api module.
  11.155 + **/
  11.156 +static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  11.157 +{
  11.158 +	struct e1000_nvm_info *nvm = &hw->nvm;
  11.159 +	u32 eecd = er32(EECD);
  11.160 +	u16 size;
  11.161 +
  11.162 +	nvm->opcode_bits	= 8;
  11.163 +	nvm->delay_usec	 = 1;
  11.164 +	switch (nvm->override) {
  11.165 +	case e1000_nvm_override_spi_large:
  11.166 +		nvm->page_size    = 32;
  11.167 +		nvm->address_bits = 16;
  11.168 +		break;
  11.169 +	case e1000_nvm_override_spi_small:
  11.170 +		nvm->page_size    = 8;
  11.171 +		nvm->address_bits = 8;
  11.172 +		break;
  11.173 +	default:
  11.174 +		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
  11.175 +		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
  11.176 +		break;
  11.177 +	}
  11.178 +
  11.179 +	nvm->type = e1000_nvm_eeprom_spi;
  11.180 +
  11.181 +	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
  11.182 +			  E1000_EECD_SIZE_EX_SHIFT);
  11.183 +
  11.184 +	/*
  11.185 +	 * Added to a constant, "size" becomes the left-shift value
  11.186 +	 * for setting word_size.
  11.187 +	 */
  11.188 +	size += NVM_WORD_SIZE_BASE_SHIFT;
  11.189 +
  11.190 +	/* EEPROM access above 16k is unsupported */
  11.191 +	if (size > 14)
  11.192 +		size = 14;
  11.193 +	nvm->word_size	= 1 << size;
  11.194 +
  11.195 +	return 0;
  11.196 +}
  11.197 +
  11.198 +/**
  11.199 + *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
  11.200 + *  @hw: pointer to the HW structure
  11.201 + *
  11.202 + *  This is a function pointer entry point called by the api module.
  11.203 + **/
  11.204 +static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
  11.205 +{
  11.206 +	struct e1000_hw *hw = &adapter->hw;
  11.207 +	struct e1000_mac_info *mac = &hw->mac;
  11.208 +	struct e1000_mac_operations *func = &mac->ops;
  11.209 +
  11.210 +	/* Set media type */
  11.211 +	switch (adapter->pdev->device) {
  11.212 +	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  11.213 +		hw->phy.media_type = e1000_media_type_internal_serdes;
  11.214 +		break;
  11.215 +	default:
  11.216 +		hw->phy.media_type = e1000_media_type_copper;
  11.217 +		break;
  11.218 +	}
  11.219 +
  11.220 +	/* Set mta register count */
  11.221 +	mac->mta_reg_count = 128;
  11.222 +	/* Set rar entry count */
  11.223 +	mac->rar_entry_count = E1000_RAR_ENTRIES;
  11.224 +	/* Set if manageability features are enabled. */
  11.225 +	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
  11.226 +
  11.227 +	/* check for link */
  11.228 +	switch (hw->phy.media_type) {
  11.229 +	case e1000_media_type_copper:
  11.230 +		func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
  11.231 +		func->check_for_link = e1000e_check_for_copper_link;
  11.232 +		break;
  11.233 +	case e1000_media_type_fiber:
  11.234 +		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
  11.235 +		func->check_for_link = e1000e_check_for_fiber_link;
  11.236 +		break;
  11.237 +	case e1000_media_type_internal_serdes:
  11.238 +		func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
  11.239 +		func->check_for_link = e1000e_check_for_serdes_link;
  11.240 +		break;
  11.241 +	default:
  11.242 +		return -E1000_ERR_CONFIG;
  11.243 +		break;
  11.244 +	}
  11.245 +
  11.246 +	return 0;
  11.247 +}
  11.248 +
  11.249 +static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
  11.250 +{
  11.251 +	struct e1000_hw *hw = &adapter->hw;
  11.252 +	s32 rc;
  11.253 +
  11.254 +	rc = e1000_init_mac_params_80003es2lan(adapter);
  11.255 +	if (rc)
  11.256 +		return rc;
  11.257 +
  11.258 +	rc = e1000_init_nvm_params_80003es2lan(hw);
  11.259 +	if (rc)
  11.260 +		return rc;
  11.261 +
  11.262 +	rc = e1000_init_phy_params_80003es2lan(hw);
  11.263 +	if (rc)
  11.264 +		return rc;
  11.265 +
  11.266 +	return 0;
  11.267 +}
  11.268 +
  11.269 +/**
  11.270 + *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
  11.271 + *  @hw: pointer to the HW structure
  11.272 + *
  11.273 + *  A wrapper to acquire access rights to the correct PHY.  This is a
  11.274 + *  function pointer entry point called by the api module.
  11.275 + **/
  11.276 +static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
  11.277 +{
  11.278 +	u16 mask;
  11.279 +
  11.280 +	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
  11.281 +	mask |= E1000_SWFW_CSR_SM;
  11.282 +
  11.283 +	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
  11.284 +}
  11.285 +
  11.286 +/**
  11.287 + *  e1000_release_phy_80003es2lan - Release rights to access PHY
  11.288 + *  @hw: pointer to the HW structure
  11.289 + *
  11.290 + *  A wrapper to release access rights to the correct PHY.  This is a
  11.291 + *  function pointer entry point called by the api module.
  11.292 + **/
  11.293 +static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
  11.294 +{
  11.295 +	u16 mask;
  11.296 +
  11.297 +	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
  11.298 +	mask |= E1000_SWFW_CSR_SM;
  11.299 +
  11.300 +	e1000_release_swfw_sync_80003es2lan(hw, mask);
  11.301 +}
  11.302 +
  11.303 +/**
  11.304 + *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
  11.305 + *  @hw: pointer to the HW structure
  11.306 + *
  11.307 + *  Acquire the semaphore to access the EEPROM.  This is a function
  11.308 + *  pointer entry point called by the api module.
  11.309 + **/
  11.310 +static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
  11.311 +{
  11.312 +	s32 ret_val;
  11.313 +
  11.314 +	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  11.315 +	if (ret_val)
  11.316 +		return ret_val;
  11.317 +
  11.318 +	ret_val = e1000e_acquire_nvm(hw);
  11.319 +
  11.320 +	if (ret_val)
  11.321 +		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  11.322 +
  11.323 +	return ret_val;
  11.324 +}
  11.325 +
  11.326 +/**
  11.327 + *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
  11.328 + *  @hw: pointer to the HW structure
  11.329 + *
  11.330 + *  Release the semaphore used to access the EEPROM.  This is a
  11.331 + *  function pointer entry point called by the api module.
  11.332 + **/
  11.333 +static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
  11.334 +{
  11.335 +	e1000e_release_nvm(hw);
  11.336 +	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  11.337 +}
  11.338 +
  11.339 +/**
  11.340 + *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
  11.341 + *  @hw: pointer to the HW structure
  11.342 + *  @mask: specifies which semaphore to acquire
  11.343 + *
  11.344 + *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
  11.345 + *  will also specify which port we're acquiring the lock for.
  11.346 + **/
  11.347 +static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
  11.348 +{
  11.349 +	u32 swfw_sync;
  11.350 +	u32 swmask = mask;
  11.351 +	u32 fwmask = mask << 16;
  11.352 +	s32 i = 0;
  11.353 +	s32 timeout = 200;
  11.354 +
  11.355 +	while (i < timeout) {
  11.356 +		if (e1000e_get_hw_semaphore(hw))
  11.357 +			return -E1000_ERR_SWFW_SYNC;
  11.358 +
  11.359 +		swfw_sync = er32(SW_FW_SYNC);
  11.360 +		if (!(swfw_sync & (fwmask | swmask)))
  11.361 +			break;
  11.362 +
  11.363 +		/*
  11.364 +		 * Firmware currently using resource (fwmask)
  11.365 +		 * or other software thread using resource (swmask)
  11.366 +		 */
  11.367 +		e1000e_put_hw_semaphore(hw);
  11.368 +		mdelay(5);
  11.369 +		i++;
  11.370 +	}
  11.371 +
  11.372 +	if (i == timeout) {
  11.373 +		hw_dbg(hw,
  11.374 +		       "Driver can't access resource, SW_FW_SYNC timeout.\n");
  11.375 +		return -E1000_ERR_SWFW_SYNC;
  11.376 +	}
  11.377 +
  11.378 +	swfw_sync |= swmask;
  11.379 +	ew32(SW_FW_SYNC, swfw_sync);
  11.380 +
  11.381 +	e1000e_put_hw_semaphore(hw);
  11.382 +
  11.383 +	return 0;
  11.384 +}
  11.385 +
  11.386 +/**
  11.387 + *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
  11.388 + *  @hw: pointer to the HW structure
  11.389 + *  @mask: specifies which semaphore to acquire
  11.390 + *
  11.391 + *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
  11.392 + *  will also specify which port we're releasing the lock for.
  11.393 + **/
  11.394 +static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
  11.395 +{
  11.396 +	u32 swfw_sync;
  11.397 +
  11.398 +	while (e1000e_get_hw_semaphore(hw) != 0);
  11.399 +	/* Empty */
  11.400 +
  11.401 +	swfw_sync = er32(SW_FW_SYNC);
  11.402 +	swfw_sync &= ~mask;
  11.403 +	ew32(SW_FW_SYNC, swfw_sync);
  11.404 +
  11.405 +	e1000e_put_hw_semaphore(hw);
  11.406 +}
  11.407 +
  11.408 +/**
  11.409 + *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
  11.410 + *  @hw: pointer to the HW structure
  11.411 + *  @offset: offset of the register to read
  11.412 + *  @data: pointer to the data returned from the operation
  11.413 + *
  11.414 + *  Read the GG82563 PHY register.  This is a function pointer entry
  11.415 + *  point called by the api module.
  11.416 + **/
  11.417 +static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  11.418 +						  u32 offset, u16 *data)
  11.419 +{
  11.420 +	s32 ret_val;
  11.421 +	u32 page_select;
  11.422 +	u16 temp;
  11.423 +
  11.424 +	ret_val = e1000_acquire_phy_80003es2lan(hw);
  11.425 +	if (ret_val)
  11.426 +		return ret_val;
  11.427 +
  11.428 +	/* Select Configuration Page */
  11.429 +	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  11.430 +		page_select = GG82563_PHY_PAGE_SELECT;
  11.431 +	} else {
  11.432 +		/*
  11.433 +		 * Use Alternative Page Select register to access
  11.434 +		 * registers 30 and 31
  11.435 +		 */
  11.436 +		page_select = GG82563_PHY_PAGE_SELECT_ALT;
  11.437 +	}
  11.438 +
  11.439 +	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
  11.440 +	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
  11.441 +	if (ret_val) {
  11.442 +		e1000_release_phy_80003es2lan(hw);
  11.443 +		return ret_val;
  11.444 +	}
  11.445 +
  11.446 +	/*
  11.447 +	 * The "ready" bit in the MDIC register may be incorrectly set
  11.448 +	 * before the device has completed the "Page Select" MDI
  11.449 +	 * transaction.  So we wait 200us after each MDI command...
  11.450 +	 */
  11.451 +	udelay(200);
  11.452 +
  11.453 +	/* ...and verify the command was successful. */
  11.454 +	ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
  11.455 +
  11.456 +	if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
  11.457 +		ret_val = -E1000_ERR_PHY;
  11.458 +		e1000_release_phy_80003es2lan(hw);
  11.459 +		return ret_val;
  11.460 +	}
  11.461 +
  11.462 +	udelay(200);
  11.463 +
  11.464 +	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  11.465 +					   data);
  11.466 +
  11.467 +	udelay(200);
  11.468 +	e1000_release_phy_80003es2lan(hw);
  11.469 +
  11.470 +	return ret_val;
  11.471 +}
  11.472 +
  11.473 +/**
  11.474 + *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
  11.475 + *  @hw: pointer to the HW structure
  11.476 + *  @offset: offset of the register to read
  11.477 + *  @data: value to write to the register
  11.478 + *
  11.479 + *  Write to the GG82563 PHY register.  This is a function pointer entry
  11.480 + *  point called by the api module.
  11.481 + **/
  11.482 +static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  11.483 +						   u32 offset, u16 data)
  11.484 +{
  11.485 +	s32 ret_val;
  11.486 +	u32 page_select;
  11.487 +	u16 temp;
  11.488 +
  11.489 +	ret_val = e1000_acquire_phy_80003es2lan(hw);
  11.490 +	if (ret_val)
  11.491 +		return ret_val;
  11.492 +
  11.493 +	/* Select Configuration Page */
  11.494 +	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  11.495 +		page_select = GG82563_PHY_PAGE_SELECT;
  11.496 +	} else {
  11.497 +		/*
  11.498 +		 * Use Alternative Page Select register to access
  11.499 +		 * registers 30 and 31
  11.500 +		 */
  11.501 +		page_select = GG82563_PHY_PAGE_SELECT_ALT;
  11.502 +	}
  11.503 +
  11.504 +	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
  11.505 +	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
  11.506 +	if (ret_val) {
  11.507 +		e1000_release_phy_80003es2lan(hw);
  11.508 +		return ret_val;
  11.509 +	}
  11.510 +
  11.511 +
  11.512 +	/*
  11.513 +	 * The "ready" bit in the MDIC register may be incorrectly set
  11.514 +	 * before the device has completed the "Page Select" MDI
  11.515 +	 * transaction.  So we wait 200us after each MDI command...
  11.516 +	 */
  11.517 +	udelay(200);
  11.518 +
  11.519 +	/* ...and verify the command was successful. */
  11.520 +	ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
  11.521 +
  11.522 +	if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
  11.523 +		e1000_release_phy_80003es2lan(hw);
  11.524 +		return -E1000_ERR_PHY;
  11.525 +	}
  11.526 +
  11.527 +	udelay(200);
  11.528 +
  11.529 +	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  11.530 +					    data);
  11.531 +
  11.532 +	udelay(200);
  11.533 +	e1000_release_phy_80003es2lan(hw);
  11.534 +
  11.535 +	return ret_val;
  11.536 +}
  11.537 +
  11.538 +/**
  11.539 + *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
  11.540 + *  @hw: pointer to the HW structure
  11.541 + *  @offset: offset of the register to read
  11.542 + *  @words: number of words to write
  11.543 + *  @data: buffer of data to write to the NVM
  11.544 + *
  11.545 + *  Write "words" of data to the ESB2 NVM.  This is a function
  11.546 + *  pointer entry point called by the api module.
  11.547 + **/
  11.548 +static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
  11.549 +				       u16 words, u16 *data)
  11.550 +{
  11.551 +	return e1000e_write_nvm_spi(hw, offset, words, data);
  11.552 +}
  11.553 +
  11.554 +/**
  11.555 + *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
  11.556 + *  @hw: pointer to the HW structure
  11.557 + *
  11.558 + *  Wait a specific amount of time for manageability processes to complete.
  11.559 + *  This is a function pointer entry point called by the phy module.
  11.560 + **/
  11.561 +static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
  11.562 +{
  11.563 +	s32 timeout = PHY_CFG_TIMEOUT;
  11.564 +	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
  11.565 +
  11.566 +	if (hw->bus.func == 1)
  11.567 +		mask = E1000_NVM_CFG_DONE_PORT_1;
  11.568 +
  11.569 +	while (timeout) {
  11.570 +		if (er32(EEMNGCTL) & mask)
  11.571 +			break;
  11.572 +		msleep(1);
  11.573 +		timeout--;
  11.574 +	}
  11.575 +	if (!timeout) {
  11.576 +		hw_dbg(hw, "MNG configuration cycle has not completed.\n");
  11.577 +		return -E1000_ERR_RESET;
  11.578 +	}
  11.579 +
  11.580 +	return 0;
  11.581 +}
  11.582 +
  11.583 +/**
  11.584 + *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
  11.585 + *  @hw: pointer to the HW structure
  11.586 + *
  11.587 + *  Force the speed and duplex settings onto the PHY.  This is a
  11.588 + *  function pointer entry point called by the phy module.
  11.589 + **/
  11.590 +static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
  11.591 +{
  11.592 +	s32 ret_val;
  11.593 +	u16 phy_data;
  11.594 +	bool link;
  11.595 +
  11.596 +	/*
  11.597 +	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
  11.598 +	 * forced whenever speed and duplex are forced.
  11.599 +	 */
  11.600 +	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  11.601 +	if (ret_val)
  11.602 +		return ret_val;
  11.603 +
  11.604 +	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
  11.605 +	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
  11.606 +	if (ret_val)
  11.607 +		return ret_val;
  11.608 +
  11.609 +	hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
  11.610 +
  11.611 +	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
  11.612 +	if (ret_val)
  11.613 +		return ret_val;
  11.614 +
  11.615 +	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
  11.616 +
  11.617 +	/* Reset the phy to commit changes. */
  11.618 +	phy_data |= MII_CR_RESET;
  11.619 +
  11.620 +	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
  11.621 +	if (ret_val)
  11.622 +		return ret_val;
  11.623 +
  11.624 +	udelay(1);
  11.625 +
  11.626 +	if (hw->phy.autoneg_wait_to_complete) {
  11.627 +		hw_dbg(hw, "Waiting for forced speed/duplex link "
  11.628 +			 "on GG82563 phy.\n");
  11.629 +
  11.630 +		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
  11.631 +						     100000, &link);
  11.632 +		if (ret_val)
  11.633 +			return ret_val;
  11.634 +
  11.635 +		if (!link) {
  11.636 +			/*
  11.637 +			 * We didn't get link.
  11.638 +			 * Reset the DSP and cross our fingers.
  11.639 +			 */
  11.640 +			ret_val = e1000e_phy_reset_dsp(hw);
  11.641 +			if (ret_val)
  11.642 +				return ret_val;
  11.643 +		}
  11.644 +
  11.645 +		/* Try once more */
  11.646 +		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
  11.647 +						     100000, &link);
  11.648 +		if (ret_val)
  11.649 +			return ret_val;
  11.650 +	}
  11.651 +
  11.652 +	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  11.653 +	if (ret_val)
  11.654 +		return ret_val;
  11.655 +
  11.656 +	/*
  11.657 +	 * Resetting the phy means we need to verify the TX_CLK corresponds
  11.658 +	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
  11.659 +	 */
  11.660 +	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
  11.661 +	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
  11.662 +		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
  11.663 +	else
  11.664 +		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
  11.665 +
  11.666 +	/*
  11.667 +	 * In addition, we must re-enable CRS on Tx for both half and full
  11.668 +	 * duplex.
  11.669 +	 */
  11.670 +	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  11.671 +	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  11.672 +
  11.673 +	return ret_val;
  11.674 +}
  11.675 +
  11.676 +/**
  11.677 + *  e1000_get_cable_length_80003es2lan - Set approximate cable length
  11.678 + *  @hw: pointer to the HW structure
  11.679 + *
  11.680 + *  Find the approximate cable length as measured by the GG82563 PHY.
  11.681 + *  This is a function pointer entry point called by the phy module.
  11.682 + **/
  11.683 +static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
  11.684 +{
  11.685 +	struct e1000_phy_info *phy = &hw->phy;
  11.686 +	s32 ret_val;
  11.687 +	u16 phy_data;
  11.688 +	u16 index;
  11.689 +
  11.690 +	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
  11.691 +	if (ret_val)
  11.692 +		return ret_val;
  11.693 +
  11.694 +	index = phy_data & GG82563_DSPD_CABLE_LENGTH;
  11.695 +	phy->min_cable_length = e1000_gg82563_cable_length_table[index];
  11.696 +	phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
  11.697 +
  11.698 +	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
  11.699 +
  11.700 +	return 0;
  11.701 +}
  11.702 +
  11.703 +/**
  11.704 + *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
  11.705 + *  @hw: pointer to the HW structure
  11.706 + *  @speed: pointer to speed buffer
  11.707 + *  @duplex: pointer to duplex buffer
  11.708 + *
  11.709 + *  Retrieve the current speed and duplex configuration.
  11.710 + *  This is a function pointer entry point called by the api module.
  11.711 + **/
  11.712 +static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  11.713 +					      u16 *duplex)
  11.714 +{
  11.715 +	s32 ret_val;
  11.716 +
  11.717 +	if (hw->phy.media_type == e1000_media_type_copper) {
  11.718 +		ret_val = e1000e_get_speed_and_duplex_copper(hw,
  11.719 +								    speed,
  11.720 +								    duplex);
  11.721 +		if (ret_val)
  11.722 +			return ret_val;
  11.723 +		if (*speed == SPEED_1000)
  11.724 +			ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
  11.725 +		else
  11.726 +			ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
  11.727 +							      *duplex);
  11.728 +	} else {
  11.729 +		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
  11.730 +								  speed,
  11.731 +								  duplex);
  11.732 +	}
  11.733 +
  11.734 +	return ret_val;
  11.735 +}
  11.736 +
  11.737 +/**
  11.738 + *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
  11.739 + *  @hw: pointer to the HW structure
  11.740 + *
  11.741 + *  Perform a global reset to the ESB2 controller.
  11.742 + *  This is a function pointer entry point called by the api module.
  11.743 + **/
  11.744 +static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
  11.745 +{
  11.746 +	u32 ctrl;
  11.747 +	u32 icr;
  11.748 +	s32 ret_val;
  11.749 +
  11.750 +	/*
  11.751 +	 * Prevent the PCI-E bus from sticking if there is no TLP connection
  11.752 +	 * on the last TLP read/write transaction when MAC is reset.
  11.753 +	 */
  11.754 +	ret_val = e1000e_disable_pcie_master(hw);
  11.755 +	if (ret_val)
  11.756 +		hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
  11.757 +
  11.758 +	hw_dbg(hw, "Masking off all interrupts\n");
  11.759 +	ew32(IMC, 0xffffffff);
  11.760 +
  11.761 +	ew32(RCTL, 0);
  11.762 +	ew32(TCTL, E1000_TCTL_PSP);
  11.763 +	e1e_flush();
  11.764 +
  11.765 +	msleep(10);
  11.766 +
  11.767 +	ctrl = er32(CTRL);
  11.768 +
  11.769 +	hw_dbg(hw, "Issuing a global reset to MAC\n");
  11.770 +	ew32(CTRL, ctrl | E1000_CTRL_RST);
  11.771 +
  11.772 +	ret_val = e1000e_get_auto_rd_done(hw);
  11.773 +	if (ret_val)
  11.774 +		/* We don't want to continue accessing MAC registers. */
  11.775 +		return ret_val;
  11.776 +
  11.777 +	/* Clear any pending interrupt events. */
  11.778 +	ew32(IMC, 0xffffffff);
  11.779 +	icr = er32(ICR);
  11.780 +
  11.781 +	return 0;
  11.782 +}
  11.783 +
  11.784 +/**
  11.785 + *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
  11.786 + *  @hw: pointer to the HW structure
  11.787 + *
  11.788 + *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
  11.789 + *  This is a function pointer entry point called by the api module.
  11.790 + **/
  11.791 +static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
  11.792 +{
  11.793 +	struct e1000_mac_info *mac = &hw->mac;
  11.794 +	u32 reg_data;
  11.795 +	s32 ret_val;
  11.796 +	u16 i;
  11.797 +
  11.798 +	e1000_initialize_hw_bits_80003es2lan(hw);
  11.799 +
  11.800 +	/* Initialize identification LED */
  11.801 +	ret_val = e1000e_id_led_init(hw);
  11.802 +	if (ret_val) {
  11.803 +		hw_dbg(hw, "Error initializing identification LED\n");
  11.804 +		return ret_val;
  11.805 +	}
  11.806 +
  11.807 +	/* Disabling VLAN filtering */
  11.808 +	hw_dbg(hw, "Initializing the IEEE VLAN\n");
  11.809 +	e1000e_clear_vfta(hw);
  11.810 +
  11.811 +	/* Setup the receive address. */
  11.812 +	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
  11.813 +
  11.814 +	/* Zero out the Multicast HASH table */
  11.815 +	hw_dbg(hw, "Zeroing the MTA\n");
  11.816 +	for (i = 0; i < mac->mta_reg_count; i++)
  11.817 +		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
  11.818 +
  11.819 +	/* Setup link and flow control */
  11.820 +	ret_val = e1000e_setup_link(hw);
  11.821 +
  11.822 +	/* Set the transmit descriptor write-back policy */
  11.823 +	reg_data = er32(TXDCTL(0));
  11.824 +	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
  11.825 +		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
  11.826 +	ew32(TXDCTL(0), reg_data);
  11.827 +
  11.828 +	/* ...for both queues. */
  11.829 +	reg_data = er32(TXDCTL(1));
  11.830 +	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
  11.831 +		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
  11.832 +	ew32(TXDCTL(1), reg_data);
  11.833 +
  11.834 +	/* Enable retransmit on late collisions */
  11.835 +	reg_data = er32(TCTL);
  11.836 +	reg_data |= E1000_TCTL_RTLC;
  11.837 +	ew32(TCTL, reg_data);
  11.838 +
  11.839 +	/* Configure Gigabit Carry Extend Padding */
  11.840 +	reg_data = er32(TCTL_EXT);
  11.841 +	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  11.842 +	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
  11.843 +	ew32(TCTL_EXT, reg_data);
  11.844 +
  11.845 +	/* Configure Transmit Inter-Packet Gap */
  11.846 +	reg_data = er32(TIPG);
  11.847 +	reg_data &= ~E1000_TIPG_IPGT_MASK;
  11.848 +	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
  11.849 +	ew32(TIPG, reg_data);
  11.850 +
  11.851 +	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
  11.852 +	reg_data &= ~0x00100000;
  11.853 +	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
  11.854 +
  11.855 +	/*
  11.856 +	 * Clear all of the statistics registers (clear on read).  It is
  11.857 +	 * important that we do this after we have tried to establish link
  11.858 +	 * because the symbol error count will increment wildly if there
  11.859 +	 * is no link.
  11.860 +	 */
  11.861 +	e1000_clear_hw_cntrs_80003es2lan(hw);
  11.862 +
  11.863 +	return ret_val;
  11.864 +}
  11.865 +
  11.866 +/**
  11.867 + *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
  11.868 + *  @hw: pointer to the HW structure
  11.869 + *
  11.870 + *  Initializes required hardware-dependent bits needed for normal operation.
  11.871 + **/
  11.872 +static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
  11.873 +{
  11.874 +	u32 reg;
  11.875 +
  11.876 +	/* Transmit Descriptor Control 0 */
  11.877 +	reg = er32(TXDCTL(0));
  11.878 +	reg |= (1 << 22);
  11.879 +	ew32(TXDCTL(0), reg);
  11.880 +
  11.881 +	/* Transmit Descriptor Control 1 */
  11.882 +	reg = er32(TXDCTL(1));
  11.883 +	reg |= (1 << 22);
  11.884 +	ew32(TXDCTL(1), reg);
  11.885 +
  11.886 +	/* Transmit Arbitration Control 0 */
  11.887 +	reg = er32(TARC(0));
  11.888 +	reg &= ~(0xF << 27); /* 30:27 */
  11.889 +	if (hw->phy.media_type != e1000_media_type_copper)
  11.890 +		reg &= ~(1 << 20);
  11.891 +	ew32(TARC(0), reg);
  11.892 +
  11.893 +	/* Transmit Arbitration Control 1 */
  11.894 +	reg = er32(TARC(1));
  11.895 +	if (er32(TCTL) & E1000_TCTL_MULR)
  11.896 +		reg &= ~(1 << 28);
  11.897 +	else
  11.898 +		reg |= (1 << 28);
  11.899 +	ew32(TARC(1), reg);
  11.900 +}
  11.901 +
  11.902 +/**
  11.903 + *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
  11.904 + *  @hw: pointer to the HW structure
  11.905 + *
  11.906 + *  Setup some GG82563 PHY registers for obtaining link
  11.907 + **/
  11.908 +static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
  11.909 +{
  11.910 +	struct e1000_phy_info *phy = &hw->phy;
  11.911 +	s32 ret_val;
  11.912 +	u32 ctrl_ext;
  11.913 +	u32 i = 0;
  11.914 +	u16 data, data2;
  11.915 +
  11.916 +	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
  11.917 +	if (ret_val)
  11.918 +		return ret_val;
  11.919 +
  11.920 +	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  11.921 +	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
  11.922 +	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
  11.923 +
  11.924 +	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
  11.925 +	if (ret_val)
  11.926 +		return ret_val;
  11.927 +
  11.928 +	/*
  11.929 +	 * Options:
  11.930 +	 *   MDI/MDI-X = 0 (default)
  11.931 +	 *   0 - Auto for all speeds
  11.932 +	 *   1 - MDI mode
  11.933 +	 *   2 - MDI-X mode
  11.934 +	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  11.935 +	 */
  11.936 +	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
  11.937 +	if (ret_val)
  11.938 +		return ret_val;
  11.939 +
  11.940 +	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  11.941 +
  11.942 +	switch (phy->mdix) {
  11.943 +	case 1:
  11.944 +		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  11.945 +		break;
  11.946 +	case 2:
  11.947 +		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  11.948 +		break;
  11.949 +	case 0:
  11.950 +	default:
  11.951 +		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  11.952 +		break;
  11.953 +	}
  11.954 +
  11.955 +	/*
  11.956 +	 * Options:
  11.957 +	 *   disable_polarity_correction = 0 (default)
  11.958 +	 *       Automatic Correction for Reversed Cable Polarity
  11.959 +	 *   0 - Disabled
  11.960 +	 *   1 - Enabled
  11.961 +	 */
  11.962 +	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  11.963 +	if (phy->disable_polarity_correction)
  11.964 +		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  11.965 +
  11.966 +	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
  11.967 +	if (ret_val)
  11.968 +		return ret_val;
  11.969 +
  11.970 +	/* SW Reset the PHY so all changes take effect */
  11.971 +	ret_val = e1000e_commit_phy(hw);
  11.972 +	if (ret_val) {
  11.973 +		hw_dbg(hw, "Error Resetting the PHY\n");
  11.974 +		return ret_val;
  11.975 +	}
  11.976 +
  11.977 +	/* Bypass Rx and Tx FIFO's */
  11.978 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
  11.979 +					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
  11.980 +					E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
  11.981 +	if (ret_val)
  11.982 +		return ret_val;
  11.983 +
  11.984 +	ret_val = e1000e_read_kmrn_reg(hw,
  11.985 +				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
  11.986 +				       &data);
  11.987 +	if (ret_val)
  11.988 +		return ret_val;
  11.989 +	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
  11.990 +	ret_val = e1000e_write_kmrn_reg(hw,
  11.991 +					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
  11.992 +					data);
  11.993 +	if (ret_val)
  11.994 +		return ret_val;
  11.995 +
  11.996 +	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
  11.997 +	if (ret_val)
  11.998 +		return ret_val;
  11.999 +
 11.1000 +	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 11.1001 +	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 11.1002 +	if (ret_val)
 11.1003 +		return ret_val;
 11.1004 +
 11.1005 +	ctrl_ext = er32(CTRL_EXT);
 11.1006 +	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
 11.1007 +	ew32(CTRL_EXT, ctrl_ext);
 11.1008 +
 11.1009 +	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 11.1010 +	if (ret_val)
 11.1011 +		return ret_val;
 11.1012 +
 11.1013 +	/*
 11.1014 +	 * Do not init these registers when the HW is in IAMT mode, since the
 11.1015 +	 * firmware will have already initialized them.  We only initialize
 11.1016 +	 * them if the HW is not in IAMT mode.
 11.1017 +	 */
 11.1018 +	if (!e1000e_check_mng_mode(hw)) {
 11.1019 +		/* Enable Electrical Idle on the PHY */
 11.1020 +		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 11.1021 +		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 11.1022 +		if (ret_val)
 11.1023 +			return ret_val;
 11.1024 +
 11.1025 +		do {
 11.1026 +			ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
 11.1027 +					   &data);
 11.1028 +			if (ret_val)
 11.1029 +				return ret_val;
 11.1030 +
 11.1031 +			ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
 11.1032 +					   &data2);
 11.1033 +			if (ret_val)
 11.1034 +				return ret_val;
 11.1035 +			i++;
 11.1036 +		} while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY));
 11.1037 +
 11.1038 +		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 11.1039 +		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
 11.1040 +		if (ret_val)
 11.1041 +			return ret_val;
 11.1042 +	}
 11.1043 +
 11.1044 +	/*
 11.1045 +	 * Workaround: Disable padding in Kumeran interface in the MAC
 11.1046 +	 * and in the PHY to avoid CRC errors.
 11.1047 +	 */
 11.1048 +	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
 11.1049 +	if (ret_val)
 11.1050 +		return ret_val;
 11.1051 +
 11.1052 +	data |= GG82563_ICR_DIS_PADDING;
 11.1053 +	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
 11.1054 +	if (ret_val)
 11.1055 +		return ret_val;
 11.1056 +
 11.1057 +	return 0;
 11.1058 +}
 11.1059 +
 11.1060 +/**
 11.1061 + *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
 11.1062 + *  @hw: pointer to the HW structure
 11.1063 + *
 11.1064 + *  Essentially a wrapper for setting up all things "copper" related.
 11.1065 + *  This is a function pointer entry point called by the mac module.
 11.1066 + **/
 11.1067 +static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
 11.1068 +{
 11.1069 +	u32 ctrl;
 11.1070 +	s32 ret_val;
 11.1071 +	u16 reg_data;
 11.1072 +
 11.1073 +	ctrl = er32(CTRL);
 11.1074 +	ctrl |= E1000_CTRL_SLU;
 11.1075 +	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 11.1076 +	ew32(CTRL, ctrl);
 11.1077 +
 11.1078 +	/*
 11.1079 +	 * Set the mac to wait the maximum time between each
 11.1080 +	 * iteration and increase the max iterations when
 11.1081 +	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
 11.1082 +	 */
 11.1083 +	ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
 11.1084 +	if (ret_val)
 11.1085 +		return ret_val;
 11.1086 +	ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
 11.1087 +	if (ret_val)
 11.1088 +		return ret_val;
 11.1089 +	reg_data |= 0x3F;
 11.1090 +	ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
 11.1091 +	if (ret_val)
 11.1092 +		return ret_val;
 11.1093 +	ret_val = e1000e_read_kmrn_reg(hw,
 11.1094 +				      E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
 11.1095 +				      &reg_data);
 11.1096 +	if (ret_val)
 11.1097 +		return ret_val;
 11.1098 +	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
 11.1099 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
 11.1100 +					reg_data);
 11.1101 +	if (ret_val)
 11.1102 +		return ret_val;
 11.1103 +
 11.1104 +	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
 11.1105 +	if (ret_val)
 11.1106 +		return ret_val;
 11.1107 +
 11.1108 +	ret_val = e1000e_setup_copper_link(hw);
 11.1109 +
 11.1110 +	return 0;
 11.1111 +}
 11.1112 +
 11.1113 +/**
 11.1114 + *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
 11.1115 + *  @hw: pointer to the HW structure
 11.1116 + *  @duplex: current duplex setting
 11.1117 + *
 11.1118 + *  Configure the KMRN interface by applying last minute quirks for
 11.1119 + *  10/100 operation.
 11.1120 + **/
 11.1121 +static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
 11.1122 +{
 11.1123 +	s32 ret_val;
 11.1124 +	u32 tipg;
 11.1125 +	u32 i = 0;
 11.1126 +	u16 reg_data, reg_data2;
 11.1127 +
 11.1128 +	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
 11.1129 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
 11.1130 +					reg_data);
 11.1131 +	if (ret_val)
 11.1132 +		return ret_val;
 11.1133 +
 11.1134 +	/* Configure Transmit Inter-Packet Gap */
 11.1135 +	tipg = er32(TIPG);
 11.1136 +	tipg &= ~E1000_TIPG_IPGT_MASK;
 11.1137 +	tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
 11.1138 +	ew32(TIPG, tipg);
 11.1139 +
 11.1140 +	do {
 11.1141 +		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
 11.1142 +		if (ret_val)
 11.1143 +			return ret_val;
 11.1144 +
 11.1145 +		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
 11.1146 +		if (ret_val)
 11.1147 +			return ret_val;
 11.1148 +		i++;
 11.1149 +	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
 11.1150 +
 11.1151 +	if (duplex == HALF_DUPLEX)
 11.1152 +		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
 11.1153 +	else
 11.1154 +		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 11.1155 +
 11.1156 +	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
 11.1157 +
 11.1158 +	return 0;
 11.1159 +}
 11.1160 +
 11.1161 +/**
 11.1162 + *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
 11.1163 + *  @hw: pointer to the HW structure
 11.1164 + *
 11.1165 + *  Configure the KMRN interface by applying last minute quirks for
 11.1166 + *  gigabit operation.
 11.1167 + **/
 11.1168 +static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
 11.1169 +{
 11.1170 +	s32 ret_val;
 11.1171 +	u16 reg_data, reg_data2;
 11.1172 +	u32 tipg;
 11.1173 +	u32 i = 0;
 11.1174 +
 11.1175 +	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
 11.1176 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
 11.1177 +					reg_data);
 11.1178 +	if (ret_val)
 11.1179 +		return ret_val;
 11.1180 +
 11.1181 +	/* Configure Transmit Inter-Packet Gap */
 11.1182 +	tipg = er32(TIPG);
 11.1183 +	tipg &= ~E1000_TIPG_IPGT_MASK;
 11.1184 +	tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 11.1185 +	ew32(TIPG, tipg);
 11.1186 +
 11.1187 +	do {
 11.1188 +		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
 11.1189 +		if (ret_val)
 11.1190 +			return ret_val;
 11.1191 +
 11.1192 +		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
 11.1193 +		if (ret_val)
 11.1194 +			return ret_val;
 11.1195 +		i++;
 11.1196 +	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
 11.1197 +
 11.1198 +	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 11.1199 +	ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
 11.1200 +
 11.1201 +	return ret_val;
 11.1202 +}
 11.1203 +
 11.1204 +/**
 11.1205 + *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
 11.1206 + *  @hw: pointer to the HW structure
 11.1207 + *
 11.1208 + *  Clears the hardware counters by reading the counter registers.
 11.1209 + **/
 11.1210 +static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
 11.1211 +{
 11.1212 +	u32 temp;
 11.1213 +
 11.1214 +	e1000e_clear_hw_cntrs_base(hw);
 11.1215 +
 11.1216 +	temp = er32(PRC64);
 11.1217 +	temp = er32(PRC127);
 11.1218 +	temp = er32(PRC255);
 11.1219 +	temp = er32(PRC511);
 11.1220 +	temp = er32(PRC1023);
 11.1221 +	temp = er32(PRC1522);
 11.1222 +	temp = er32(PTC64);
 11.1223 +	temp = er32(PTC127);
 11.1224 +	temp = er32(PTC255);
 11.1225 +	temp = er32(PTC511);
 11.1226 +	temp = er32(PTC1023);
 11.1227 +	temp = er32(PTC1522);
 11.1228 +
 11.1229 +	temp = er32(ALGNERRC);
 11.1230 +	temp = er32(RXERRC);
 11.1231 +	temp = er32(TNCRS);
 11.1232 +	temp = er32(CEXTERR);
 11.1233 +	temp = er32(TSCTC);
 11.1234 +	temp = er32(TSCTFC);
 11.1235 +
 11.1236 +	temp = er32(MGTPRC);
 11.1237 +	temp = er32(MGTPDC);
 11.1238 +	temp = er32(MGTPTC);
 11.1239 +
 11.1240 +	temp = er32(IAC);
 11.1241 +	temp = er32(ICRXOC);
 11.1242 +
 11.1243 +	temp = er32(ICRXPTC);
 11.1244 +	temp = er32(ICRXATC);
 11.1245 +	temp = er32(ICTXPTC);
 11.1246 +	temp = er32(ICTXATC);
 11.1247 +	temp = er32(ICTXQEC);
 11.1248 +	temp = er32(ICTXQMTC);
 11.1249 +	temp = er32(ICRXDMTC);
 11.1250 +}
 11.1251 +
 11.1252 +static struct e1000_mac_operations es2_mac_ops = {
 11.1253 +	.check_mng_mode		= e1000e_check_mng_mode_generic,
 11.1254 +	/* check_for_link dependent on media type */
 11.1255 +	.cleanup_led		= e1000e_cleanup_led_generic,
 11.1256 +	.clear_hw_cntrs		= e1000_clear_hw_cntrs_80003es2lan,
 11.1257 +	.get_bus_info		= e1000e_get_bus_info_pcie,
 11.1258 +	.get_link_up_info	= e1000_get_link_up_info_80003es2lan,
 11.1259 +	.led_on			= e1000e_led_on_generic,
 11.1260 +	.led_off		= e1000e_led_off_generic,
 11.1261 +	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
 11.1262 +	.reset_hw		= e1000_reset_hw_80003es2lan,
 11.1263 +	.init_hw		= e1000_init_hw_80003es2lan,
 11.1264 +	.setup_link		= e1000e_setup_link,
 11.1265 +	/* setup_physical_interface dependent on media type */
 11.1266 +};
 11.1267 +
 11.1268 +static struct e1000_phy_operations es2_phy_ops = {
 11.1269 +	.acquire_phy		= e1000_acquire_phy_80003es2lan,
 11.1270 +	.check_reset_block	= e1000e_check_reset_block_generic,
 11.1271 +	.commit_phy	 	= e1000e_phy_sw_reset,
 11.1272 +	.force_speed_duplex 	= e1000_phy_force_speed_duplex_80003es2lan,
 11.1273 +	.get_cfg_done       	= e1000_get_cfg_done_80003es2lan,
 11.1274 +	.get_cable_length   	= e1000_get_cable_length_80003es2lan,
 11.1275 +	.get_phy_info       	= e1000e_get_phy_info_m88,
 11.1276 +	.read_phy_reg       	= e1000_read_phy_reg_gg82563_80003es2lan,
 11.1277 +	.release_phy		= e1000_release_phy_80003es2lan,
 11.1278 +	.reset_phy	  	= e1000e_phy_hw_reset_generic,
 11.1279 +	.set_d0_lplu_state  	= NULL,
 11.1280 +	.set_d3_lplu_state  	= e1000e_set_d3_lplu_state,
 11.1281 +	.write_phy_reg      	= e1000_write_phy_reg_gg82563_80003es2lan,
 11.1282 +};
 11.1283 +
 11.1284 +static struct e1000_nvm_operations es2_nvm_ops = {
 11.1285 +	.acquire_nvm		= e1000_acquire_nvm_80003es2lan,
 11.1286 +	.read_nvm		= e1000e_read_nvm_eerd,
 11.1287 +	.release_nvm		= e1000_release_nvm_80003es2lan,
 11.1288 +	.update_nvm		= e1000e_update_nvm_checksum_generic,
 11.1289 +	.valid_led_default	= e1000e_valid_led_default,
 11.1290 +	.validate_nvm		= e1000e_validate_nvm_checksum_generic,
 11.1291 +	.write_nvm		= e1000_write_nvm_80003es2lan,
 11.1292 +};
 11.1293 +
 11.1294 +struct e1000_info e1000_es2_info = {
 11.1295 +	.mac			= e1000_80003es2lan,
 11.1296 +	.flags			= FLAG_HAS_HW_VLAN_FILTER
 11.1297 +				  | FLAG_HAS_JUMBO_FRAMES
 11.1298 +				  | FLAG_HAS_WOL
 11.1299 +				  | FLAG_APME_IN_CTRL3
 11.1300 +				  | FLAG_RX_CSUM_ENABLED
 11.1301 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
 11.1302 +				  | FLAG_RX_NEEDS_RESTART /* errata */
 11.1303 +				  | FLAG_TARC_SET_BIT_ZERO /* errata */
 11.1304 +				  | FLAG_APME_CHECK_PORT_B
 11.1305 +				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
 11.1306 +				  | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
 11.1307 +	.pba			= 38,
 11.1308 +	.get_variants		= e1000_get_variants_80003es2lan,
 11.1309 +	.mac_ops		= &es2_mac_ops,
 11.1310 +	.phy_ops		= &es2_phy_ops,
 11.1311 +	.nvm_ops		= &es2_nvm_ops,
 11.1312 +};
 11.1313 +
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/drivers/net/e1000e/ethtool.c	Tue Feb 17 11:25:22 2009 +0000
    12.3 @@ -0,0 +1,1949 @@
    12.4 +/*******************************************************************************
    12.5 +
    12.6 +  Intel PRO/1000 Linux driver
    12.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
    12.8 +
    12.9 +  This program is free software; you can redistribute it and/or modify it
   12.10 +  under the terms and conditions of the GNU General Public License,
   12.11 +  version 2, as published by the Free Software Foundation.
   12.12 +
   12.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   12.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   12.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   12.16 +  more details.
   12.17 +
   12.18 +  You should have received a copy of the GNU General Public License along with
   12.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   12.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   12.21 +
   12.22 +  The full GNU General Public License is included in this distribution in
   12.23 +  the file called "COPYING".
   12.24 +
   12.25 +  Contact Information:
   12.26 +  Linux NICS <linux.nics@intel.com>
   12.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   12.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   12.29 +
   12.30 +*******************************************************************************/
   12.31 +
   12.32 +/* ethtool support for e1000 */
   12.33 +
   12.34 +#include <linux/netdevice.h>
   12.35 +#include <linux/ethtool.h>
   12.36 +#include <linux/pci.h>
   12.37 +#include <linux/delay.h>
   12.38 +
   12.39 +#include "e1000.h"
   12.40 +
   12.41 +struct e1000_stats {
   12.42 +	char stat_string[ETH_GSTRING_LEN];
   12.43 +	int sizeof_stat;
   12.44 +	int stat_offset;
   12.45 +};
   12.46 +
   12.47 +#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
   12.48 +		      offsetof(struct e1000_adapter, m)
   12.49 +static const struct e1000_stats e1000_gstrings_stats[] = {
   12.50 +	{ "rx_packets", E1000_STAT(stats.gprc) },
   12.51 +	{ "tx_packets", E1000_STAT(stats.gptc) },
   12.52 +	{ "rx_bytes", E1000_STAT(stats.gorc) },
   12.53 +	{ "tx_bytes", E1000_STAT(stats.gotc) },
   12.54 +	{ "rx_broadcast", E1000_STAT(stats.bprc) },
   12.55 +	{ "tx_broadcast", E1000_STAT(stats.bptc) },
   12.56 +	{ "rx_multicast", E1000_STAT(stats.mprc) },
   12.57 +	{ "tx_multicast", E1000_STAT(stats.mptc) },
   12.58 +	{ "rx_errors", E1000_STAT(net_stats.rx_errors) },
   12.59 +	{ "tx_errors", E1000_STAT(net_stats.tx_errors) },
   12.60 +	{ "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
   12.61 +	{ "multicast", E1000_STAT(stats.mprc) },
   12.62 +	{ "collisions", E1000_STAT(stats.colc) },
   12.63 +	{ "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
   12.64 +	{ "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
   12.65 +	{ "rx_crc_errors", E1000_STAT(stats.crcerrs) },
   12.66 +	{ "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
   12.67 +	{ "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
   12.68 +	{ "rx_missed_errors", E1000_STAT(stats.mpc) },
   12.69 +	{ "tx_aborted_errors", E1000_STAT(stats.ecol) },
   12.70 +	{ "tx_carrier_errors", E1000_STAT(stats.tncrs) },
   12.71 +	{ "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
   12.72 +	{ "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
   12.73 +	{ "tx_window_errors", E1000_STAT(stats.latecol) },
   12.74 +	{ "tx_abort_late_coll", E1000_STAT(stats.latecol) },
   12.75 +	{ "tx_deferred_ok", E1000_STAT(stats.dc) },
   12.76 +	{ "tx_single_coll_ok", E1000_STAT(stats.scc) },
   12.77 +	{ "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
   12.78 +	{ "tx_timeout_count", E1000_STAT(tx_timeout_count) },
   12.79 +	{ "tx_restart_queue", E1000_STAT(restart_queue) },
   12.80 +	{ "rx_long_length_errors", E1000_STAT(stats.roc) },
   12.81 +	{ "rx_short_length_errors", E1000_STAT(stats.ruc) },
   12.82 +	{ "rx_align_errors", E1000_STAT(stats.algnerrc) },
   12.83 +	{ "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
   12.84 +	{ "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
   12.85 +	{ "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
   12.86 +	{ "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
   12.87 +	{ "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
   12.88 +	{ "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
   12.89 +	{ "rx_long_byte_count", E1000_STAT(stats.gorc) },
   12.90 +	{ "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
   12.91 +	{ "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
   12.92 +	{ "rx_header_split", E1000_STAT(rx_hdr_split) },
   12.93 +	{ "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
   12.94 +	{ "tx_smbus", E1000_STAT(stats.mgptc) },
   12.95 +	{ "rx_smbus", E1000_STAT(stats.mgprc) },
   12.96 +	{ "dropped_smbus", E1000_STAT(stats.mgpdc) },
   12.97 +	{ "rx_dma_failed", E1000_STAT(rx_dma_failed) },
   12.98 +	{ "tx_dma_failed", E1000_STAT(tx_dma_failed) },
   12.99 +};
  12.100 +
  12.101 +#define E1000_GLOBAL_STATS_LEN	ARRAY_SIZE(e1000_gstrings_stats)
  12.102 +#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN)
  12.103 +static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
  12.104 +	"Register test  (offline)", "Eeprom test    (offline)",
  12.105 +	"Interrupt test (offline)", "Loopback test  (offline)",
  12.106 +	"Link test   (on/offline)"
  12.107 +};
  12.108 +#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
  12.109 +
  12.110 +static int e1000_get_settings(struct net_device *netdev,
  12.111 +			      struct ethtool_cmd *ecmd)
  12.112 +{
  12.113 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.114 +	struct e1000_hw *hw = &adapter->hw;
  12.115 +	u32 status;
  12.116 +
  12.117 +	if (hw->phy.media_type == e1000_media_type_copper) {
  12.118 +
  12.119 +		ecmd->supported = (SUPPORTED_10baseT_Half |
  12.120 +				   SUPPORTED_10baseT_Full |
  12.121 +				   SUPPORTED_100baseT_Half |
  12.122 +				   SUPPORTED_100baseT_Full |
  12.123 +				   SUPPORTED_1000baseT_Full |
  12.124 +				   SUPPORTED_Autoneg |
  12.125 +				   SUPPORTED_TP);
  12.126 +		if (hw->phy.type == e1000_phy_ife)
  12.127 +			ecmd->supported &= ~SUPPORTED_1000baseT_Full;
  12.128 +		ecmd->advertising = ADVERTISED_TP;
  12.129 +
  12.130 +		if (hw->mac.autoneg == 1) {
  12.131 +			ecmd->advertising |= ADVERTISED_Autoneg;
  12.132 +			/* the e1000 autoneg seems to match ethtool nicely */
  12.133 +			ecmd->advertising |= hw->phy.autoneg_advertised;
  12.134 +		}
  12.135 +
  12.136 +		ecmd->port = PORT_TP;
  12.137 +		ecmd->phy_address = hw->phy.addr;
  12.138 +		ecmd->transceiver = XCVR_INTERNAL;
  12.139 +
  12.140 +	} else {
  12.141 +		ecmd->supported   = (SUPPORTED_1000baseT_Full |
  12.142 +				     SUPPORTED_FIBRE |
  12.143 +				     SUPPORTED_Autoneg);
  12.144 +
  12.145 +		ecmd->advertising = (ADVERTISED_1000baseT_Full |
  12.146 +				     ADVERTISED_FIBRE |
  12.147 +				     ADVERTISED_Autoneg);
  12.148 +
  12.149 +		ecmd->port = PORT_FIBRE;
  12.150 +		ecmd->transceiver = XCVR_EXTERNAL;
  12.151 +	}
  12.152 +
  12.153 +	status = er32(STATUS);
  12.154 +	if (status & E1000_STATUS_LU) {
  12.155 +		if (status & E1000_STATUS_SPEED_1000)
  12.156 +			ecmd->speed = 1000;
  12.157 +		else if (status & E1000_STATUS_SPEED_100)
  12.158 +			ecmd->speed = 100;
  12.159 +		else
  12.160 +			ecmd->speed = 10;
  12.161 +
  12.162 +		if (status & E1000_STATUS_FD)
  12.163 +			ecmd->duplex = DUPLEX_FULL;
  12.164 +		else
  12.165 +			ecmd->duplex = DUPLEX_HALF;
  12.166 +	} else {
  12.167 +		ecmd->speed = -1;
  12.168 +		ecmd->duplex = -1;
  12.169 +	}
  12.170 +
  12.171 +	ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
  12.172 +			 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
  12.173 +	return 0;
  12.174 +}
  12.175 +
  12.176 +static u32 e1000_get_link(struct net_device *netdev)
  12.177 +{
  12.178 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.179 +	struct e1000_hw *hw = &adapter->hw;
  12.180 +	u32 status;
  12.181 +	
  12.182 +	status = er32(STATUS);
  12.183 +	return (status & E1000_STATUS_LU) ? 1 : 0;
  12.184 +}
  12.185 +
  12.186 +static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
  12.187 +{
  12.188 +	struct e1000_mac_info *mac = &adapter->hw.mac;
  12.189 +
  12.190 +	mac->autoneg = 0;
  12.191 +
  12.192 +	/* Fiber NICs only allow 1000 gbps Full duplex */
  12.193 +	if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
  12.194 +		spddplx != (SPEED_1000 + DUPLEX_FULL)) {
  12.195 +		e_err("Unsupported Speed/Duplex configuration\n");
  12.196 +		return -EINVAL;
  12.197 +	}
  12.198 +
  12.199 +	switch (spddplx) {
  12.200 +	case SPEED_10 + DUPLEX_HALF:
  12.201 +		mac->forced_speed_duplex = ADVERTISE_10_HALF;
  12.202 +		break;
  12.203 +	case SPEED_10 + DUPLEX_FULL:
  12.204 +		mac->forced_speed_duplex = ADVERTISE_10_FULL;
  12.205 +		break;
  12.206 +	case SPEED_100 + DUPLEX_HALF:
  12.207 +		mac->forced_speed_duplex = ADVERTISE_100_HALF;
  12.208 +		break;
  12.209 +	case SPEED_100 + DUPLEX_FULL:
  12.210 +		mac->forced_speed_duplex = ADVERTISE_100_FULL;
  12.211 +		break;
  12.212 +	case SPEED_1000 + DUPLEX_FULL:
  12.213 +		mac->autoneg = 1;
  12.214 +		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
  12.215 +		break;
  12.216 +	case SPEED_1000 + DUPLEX_HALF: /* not supported */
  12.217 +	default:
  12.218 +		e_err("Unsupported Speed/Duplex configuration\n");
  12.219 +		return -EINVAL;
  12.220 +	}
  12.221 +	return 0;
  12.222 +}
  12.223 +
  12.224 +static int e1000_set_settings(struct net_device *netdev,
  12.225 +			      struct ethtool_cmd *ecmd)
  12.226 +{
  12.227 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.228 +	struct e1000_hw *hw = &adapter->hw;
  12.229 +
  12.230 +	/*
  12.231 +	 * When SoL/IDER sessions are active, autoneg/speed/duplex
  12.232 +	 * cannot be changed
  12.233 +	 */
  12.234 +	if (e1000_check_reset_block(hw)) {
  12.235 +		e_err("Cannot change link characteristics when SoL/IDER is "
  12.236 +		      "active.\n");
  12.237 +		return -EINVAL;
  12.238 +	}
  12.239 +
  12.240 +	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
  12.241 +		msleep(1);
  12.242 +
  12.243 +	if (ecmd->autoneg == AUTONEG_ENABLE) {
  12.244 +		hw->mac.autoneg = 1;
  12.245 +		if (hw->phy.media_type == e1000_media_type_fiber)
  12.246 +			hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
  12.247 +						     ADVERTISED_FIBRE |
  12.248 +						     ADVERTISED_Autoneg;
  12.249 +		else
  12.250 +			hw->phy.autoneg_advertised = ecmd->advertising |
  12.251 +						     ADVERTISED_TP |
  12.252 +						     ADVERTISED_Autoneg;
  12.253 +		ecmd->advertising = hw->phy.autoneg_advertised;
  12.254 +		if (adapter->fc_autoneg)
  12.255 +			hw->fc.original_type = e1000_fc_default;
  12.256 +	} else {
  12.257 +		if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
  12.258 +			clear_bit(__E1000_RESETTING, &adapter->state);
  12.259 +			return -EINVAL;
  12.260 +		}
  12.261 +	}
  12.262 +
  12.263 +	/* reset the link */
  12.264 +
  12.265 +	if (netif_running(adapter->netdev)) {
  12.266 +		e1000e_down(adapter);
  12.267 +		e1000e_up(adapter);
  12.268 +	} else {
  12.269 +		e1000e_reset(adapter);
  12.270 +	}
  12.271 +
  12.272 +	clear_bit(__E1000_RESETTING, &adapter->state);
  12.273 +	return 0;
  12.274 +}
  12.275 +
  12.276 +static void e1000_get_pauseparam(struct net_device *netdev,
  12.277 +				 struct ethtool_pauseparam *pause)
  12.278 +{
  12.279 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.280 +	struct e1000_hw *hw = &adapter->hw;
  12.281 +
  12.282 +	pause->autoneg =
  12.283 +		(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
  12.284 +
  12.285 +	if (hw->fc.type == e1000_fc_rx_pause) {
  12.286 +		pause->rx_pause = 1;
  12.287 +	} else if (hw->fc.type == e1000_fc_tx_pause) {
  12.288 +		pause->tx_pause = 1;
  12.289 +	} else if (hw->fc.type == e1000_fc_full) {
  12.290 +		pause->rx_pause = 1;
  12.291 +		pause->tx_pause = 1;
  12.292 +	}
  12.293 +}
  12.294 +
  12.295 +static int e1000_set_pauseparam(struct net_device *netdev,
  12.296 +				struct ethtool_pauseparam *pause)
  12.297 +{
  12.298 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.299 +	struct e1000_hw *hw = &adapter->hw;
  12.300 +	int retval = 0;
  12.301 +
  12.302 +	adapter->fc_autoneg = pause->autoneg;
  12.303 +
  12.304 +	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
  12.305 +		msleep(1);
  12.306 +
  12.307 +	if (pause->rx_pause && pause->tx_pause)
  12.308 +		hw->fc.type = e1000_fc_full;
  12.309 +	else if (pause->rx_pause && !pause->tx_pause)
  12.310 +		hw->fc.type = e1000_fc_rx_pause;
  12.311 +	else if (!pause->rx_pause && pause->tx_pause)
  12.312 +		hw->fc.type = e1000_fc_tx_pause;
  12.313 +	else if (!pause->rx_pause && !pause->tx_pause)
  12.314 +		hw->fc.type = e1000_fc_none;
  12.315 +
  12.316 +	hw->fc.original_type = hw->fc.type;
  12.317 +
  12.318 +	if (adapter->fc_autoneg == AUTONEG_ENABLE) {
  12.319 +		hw->fc.type = e1000_fc_default;
  12.320 +		if (netif_running(adapter->netdev)) {
  12.321 +			e1000e_down(adapter);
  12.322 +			e1000e_up(adapter);
  12.323 +		} else {
  12.324 +			e1000e_reset(adapter);
  12.325 +		}
  12.326 +	} else {
  12.327 +		retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
  12.328 +			  hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw));
  12.329 +	}
  12.330 +
  12.331 +	clear_bit(__E1000_RESETTING, &adapter->state);
  12.332 +	return retval;
  12.333 +}
  12.334 +
  12.335 +static u32 e1000_get_rx_csum(struct net_device *netdev)
  12.336 +{
  12.337 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.338 +	return (adapter->flags & FLAG_RX_CSUM_ENABLED);
  12.339 +}
  12.340 +
  12.341 +static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
  12.342 +{
  12.343 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.344 +
  12.345 +	if (data)
  12.346 +		adapter->flags |= FLAG_RX_CSUM_ENABLED;
  12.347 +	else
  12.348 +		adapter->flags &= ~FLAG_RX_CSUM_ENABLED;
  12.349 +
  12.350 +	if (netif_running(netdev))
  12.351 +		e1000e_reinit_locked(adapter);
  12.352 +	else
  12.353 +		e1000e_reset(adapter);
  12.354 +	return 0;
  12.355 +}
  12.356 +
  12.357 +static u32 e1000_get_tx_csum(struct net_device *netdev)
  12.358 +{
  12.359 +	return ((netdev->features & NETIF_F_HW_CSUM) != 0);
  12.360 +}
  12.361 +
  12.362 +static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
  12.363 +{
  12.364 +	if (data)
  12.365 +		netdev->features |= NETIF_F_HW_CSUM;
  12.366 +	else
  12.367 +		netdev->features &= ~NETIF_F_HW_CSUM;
  12.368 +
  12.369 +	return 0;
  12.370 +}
  12.371 +
  12.372 +static int e1000_set_tso(struct net_device *netdev, u32 data)
  12.373 +{
  12.374 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.375 +
  12.376 +	if (data) {
  12.377 +		netdev->features |= NETIF_F_TSO;
  12.378 +		netdev->features |= NETIF_F_TSO6;
  12.379 +	} else {
  12.380 +		netdev->features &= ~NETIF_F_TSO;
  12.381 +		netdev->features &= ~NETIF_F_TSO6;
  12.382 +	}
  12.383 +
  12.384 +	e_info("TSO is %s\n", data ? "Enabled" : "Disabled");
  12.385 +	adapter->flags |= FLAG_TSO_FORCE;
  12.386 +	return 0;
  12.387 +}
  12.388 +
  12.389 +static u32 e1000_get_msglevel(struct net_device *netdev)
  12.390 +{
  12.391 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.392 +	return adapter->msg_enable;
  12.393 +}
  12.394 +
  12.395 +static void e1000_set_msglevel(struct net_device *netdev, u32 data)
  12.396 +{
  12.397 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.398 +	adapter->msg_enable = data;
  12.399 +}
  12.400 +
  12.401 +static int e1000_get_regs_len(struct net_device *netdev)
  12.402 +{
  12.403 +#define E1000_REGS_LEN 32 /* overestimate */
  12.404 +	return E1000_REGS_LEN * sizeof(u32);
  12.405 +}
  12.406 +
  12.407 +static void e1000_get_regs(struct net_device *netdev,
  12.408 +			   struct ethtool_regs *regs, void *p)
  12.409 +{
  12.410 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.411 +	struct e1000_hw *hw = &adapter->hw;
  12.412 +	u32 *regs_buff = p;
  12.413 +	u16 phy_data;
  12.414 +	u8 revision_id;
  12.415 +
  12.416 +	memset(p, 0, E1000_REGS_LEN * sizeof(u32));
  12.417 +
  12.418 +	pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id);
  12.419 +
  12.420 +	regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device;
  12.421 +
  12.422 +	regs_buff[0]  = er32(CTRL);
  12.423 +	regs_buff[1]  = er32(STATUS);
  12.424 +
  12.425 +	regs_buff[2]  = er32(RCTL);
  12.426 +	regs_buff[3]  = er32(RDLEN);
  12.427 +	regs_buff[4]  = er32(RDH);
  12.428 +	regs_buff[5]  = er32(RDT);
  12.429 +	regs_buff[6]  = er32(RDTR);
  12.430 +
  12.431 +	regs_buff[7]  = er32(TCTL);
  12.432 +	regs_buff[8]  = er32(TDLEN);
  12.433 +	regs_buff[9]  = er32(TDH);
  12.434 +	regs_buff[10] = er32(TDT);
  12.435 +	regs_buff[11] = er32(TIDV);
  12.436 +
  12.437 +	regs_buff[12] = adapter->hw.phy.type;  /* PHY type (IGP=1, M88=0) */
  12.438 +	if (hw->phy.type == e1000_phy_m88) {
  12.439 +		e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
  12.440 +		regs_buff[13] = (u32)phy_data; /* cable length */
  12.441 +		regs_buff[14] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
  12.442 +		regs_buff[15] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
  12.443 +		regs_buff[16] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
  12.444 +		e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  12.445 +		regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
  12.446 +		regs_buff[18] = regs_buff[13]; /* cable polarity */
  12.447 +		regs_buff[19] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
  12.448 +		regs_buff[20] = regs_buff[17]; /* polarity correction */
  12.449 +		/* phy receive errors */
  12.450 +		regs_buff[22] = adapter->phy_stats.receive_errors;
  12.451 +		regs_buff[23] = regs_buff[13]; /* mdix mode */
  12.452 +	}
  12.453 +	regs_buff[21] = adapter->phy_stats.idle_errors;  /* phy idle errors */
  12.454 +	e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
  12.455 +	regs_buff[24] = (u32)phy_data;  /* phy local receiver status */
  12.456 +	regs_buff[25] = regs_buff[24];  /* phy remote receiver status */
  12.457 +}
  12.458 +
  12.459 +static int e1000_get_eeprom_len(struct net_device *netdev)
  12.460 +{
  12.461 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.462 +	return adapter->hw.nvm.word_size * 2;
  12.463 +}
  12.464 +
  12.465 +static int e1000_get_eeprom(struct net_device *netdev,
  12.466 +			    struct ethtool_eeprom *eeprom, u8 *bytes)
  12.467 +{
  12.468 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.469 +	struct e1000_hw *hw = &adapter->hw;
  12.470 +	u16 *eeprom_buff;
  12.471 +	int first_word;
  12.472 +	int last_word;
  12.473 +	int ret_val = 0;
  12.474 +	u16 i;
  12.475 +
  12.476 +	if (eeprom->len == 0)
  12.477 +		return -EINVAL;
  12.478 +
  12.479 +	eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16);
  12.480 +
  12.481 +	first_word = eeprom->offset >> 1;
  12.482 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  12.483 +
  12.484 +	eeprom_buff = kmalloc(sizeof(u16) *
  12.485 +			(last_word - first_word + 1), GFP_KERNEL);
  12.486 +	if (!eeprom_buff)
  12.487 +		return -ENOMEM;
  12.488 +
  12.489 +	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
  12.490 +		ret_val = e1000_read_nvm(hw, first_word,
  12.491 +					 last_word - first_word + 1,
  12.492 +					 eeprom_buff);
  12.493 +	} else {
  12.494 +		for (i = 0; i < last_word - first_word + 1; i++) {
  12.495 +			ret_val = e1000_read_nvm(hw, first_word + i, 1,
  12.496 +						      &eeprom_buff[i]);
  12.497 +			if (ret_val) {
  12.498 +				/* a read error occurred, throw away the
  12.499 +				 * result */
  12.500 +				memset(eeprom_buff, 0xff, sizeof(eeprom_buff));
  12.501 +				break;
  12.502 +			}
  12.503 +		}
  12.504 +	}
  12.505 +
  12.506 +	/* Device's eeprom is always little-endian, word addressable */
  12.507 +	for (i = 0; i < last_word - first_word + 1; i++)
  12.508 +		le16_to_cpus(&eeprom_buff[i]);
  12.509 +
  12.510 +	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
  12.511 +	kfree(eeprom_buff);
  12.512 +
  12.513 +	return ret_val;
  12.514 +}
  12.515 +
  12.516 +static int e1000_set_eeprom(struct net_device *netdev,
  12.517 +			    struct ethtool_eeprom *eeprom, u8 *bytes)
  12.518 +{
  12.519 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.520 +	struct e1000_hw *hw = &adapter->hw;
  12.521 +	u16 *eeprom_buff;
  12.522 +	void *ptr;
  12.523 +	int max_len;
  12.524 +	int first_word;
  12.525 +	int last_word;
  12.526 +	int ret_val = 0;
  12.527 +	u16 i;
  12.528 +
  12.529 +	if (eeprom->len == 0)
  12.530 +		return -EOPNOTSUPP;
  12.531 +
  12.532 +	if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 16)))
  12.533 +		return -EFAULT;
  12.534 +
  12.535 +	if (adapter->flags & FLAG_READ_ONLY_NVM)
  12.536 +		return -EINVAL;
  12.537 +
  12.538 +	max_len = hw->nvm.word_size * 2;
  12.539 +
  12.540 +	first_word = eeprom->offset >> 1;
  12.541 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  12.542 +	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
  12.543 +	if (!eeprom_buff)
  12.544 +		return -ENOMEM;
  12.545 +
  12.546 +	ptr = (void *)eeprom_buff;
  12.547 +
  12.548 +	if (eeprom->offset & 1) {
  12.549 +		/* need read/modify/write of first changed EEPROM word */
  12.550 +		/* only the second byte of the word is being modified */
  12.551 +		ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]);
  12.552 +		ptr++;
  12.553 +	}
  12.554 +	if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0))
  12.555 +		/* need read/modify/write of last changed EEPROM word */
  12.556 +		/* only the first byte of the word is being modified */
  12.557 +		ret_val = e1000_read_nvm(hw, last_word, 1,
  12.558 +				  &eeprom_buff[last_word - first_word]);
  12.559 +
  12.560 +	/* Device's eeprom is always little-endian, word addressable */
  12.561 +	for (i = 0; i < last_word - first_word + 1; i++)
  12.562 +		le16_to_cpus(&eeprom_buff[i]);
  12.563 +
  12.564 +	memcpy(ptr, bytes, eeprom->len);
  12.565 +
  12.566 +	for (i = 0; i < last_word - first_word + 1; i++)
  12.567 +		eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
  12.568 +
  12.569 +	ret_val = e1000_write_nvm(hw, first_word,
  12.570 +				  last_word - first_word + 1, eeprom_buff);
  12.571 +
  12.572 +	/*
  12.573 +	 * Update the checksum over the first part of the EEPROM if needed
  12.574 +	 * and flush shadow RAM for 82573 controllers
  12.575 +	 */
  12.576 +	if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) ||
  12.577 +			       (hw->mac.type == e1000_82574) ||
  12.578 +			       (hw->mac.type == e1000_82573)))
  12.579 +		e1000e_update_nvm_checksum(hw);
  12.580 +
  12.581 +	kfree(eeprom_buff);
  12.582 +	return ret_val;
  12.583 +}
  12.584 +
  12.585 +static void e1000_get_drvinfo(struct net_device *netdev,
  12.586 +			      struct ethtool_drvinfo *drvinfo)
  12.587 +{
  12.588 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.589 +	char firmware_version[32];
  12.590 +	u16 eeprom_data;
  12.591 +
  12.592 +	strncpy(drvinfo->driver,  e1000e_driver_name, 32);
  12.593 +	strncpy(drvinfo->version, e1000e_driver_version, 32);
  12.594 +
  12.595 +	/*
  12.596 +	 * EEPROM image version # is reported as firmware version # for
  12.597 +	 * PCI-E controllers
  12.598 +	 */
  12.599 +	e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data);
  12.600 +	sprintf(firmware_version, "%d.%d-%d",
  12.601 +		(eeprom_data & 0xF000) >> 12,
  12.602 +		(eeprom_data & 0x0FF0) >> 4,
  12.603 +		eeprom_data & 0x000F);
  12.604 +
  12.605 +	strncpy(drvinfo->fw_version, firmware_version, 32);
  12.606 +	strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
  12.607 +	drvinfo->regdump_len = e1000_get_regs_len(netdev);
  12.608 +	drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
  12.609 +}
  12.610 +
  12.611 +static void e1000_get_ringparam(struct net_device *netdev,
  12.612 +				struct ethtool_ringparam *ring)
  12.613 +{
  12.614 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.615 +	struct e1000_ring *tx_ring = adapter->tx_ring;
  12.616 +	struct e1000_ring *rx_ring = adapter->rx_ring;
  12.617 +
  12.618 +	ring->rx_max_pending = E1000_MAX_RXD;
  12.619 +	ring->tx_max_pending = E1000_MAX_TXD;
  12.620 +	ring->rx_mini_max_pending = 0;
  12.621 +	ring->rx_jumbo_max_pending = 0;
  12.622 +	ring->rx_pending = rx_ring->count;
  12.623 +	ring->tx_pending = tx_ring->count;
  12.624 +	ring->rx_mini_pending = 0;
  12.625 +	ring->rx_jumbo_pending = 0;
  12.626 +}
  12.627 +
  12.628 +static int e1000_set_ringparam(struct net_device *netdev,
  12.629 +			       struct ethtool_ringparam *ring)
  12.630 +{
  12.631 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.632 +	struct e1000_ring *tx_ring, *tx_old;
  12.633 +	struct e1000_ring *rx_ring, *rx_old;
  12.634 +	int err;
  12.635 +
  12.636 +	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
  12.637 +		return -EINVAL;
  12.638 +
  12.639 +	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
  12.640 +		msleep(1);
  12.641 +
  12.642 +	if (netif_running(adapter->netdev))
  12.643 +		e1000e_down(adapter);
  12.644 +
  12.645 +	tx_old = adapter->tx_ring;
  12.646 +	rx_old = adapter->rx_ring;
  12.647 +
  12.648 +	err = -ENOMEM;
  12.649 +	tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
  12.650 +	if (!tx_ring)
  12.651 +		goto err_alloc_tx;
  12.652 +	/*
  12.653 +	 * use a memcpy to save any previously configured
  12.654 +	 * items like napi structs from having to be
  12.655 +	 * reinitialized
  12.656 +	 */
  12.657 +	memcpy(tx_ring, tx_old, sizeof(struct e1000_ring));
  12.658 +
  12.659 +	rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
  12.660 +	if (!rx_ring)
  12.661 +		goto err_alloc_rx;
  12.662 +	memcpy(rx_ring, rx_old, sizeof(struct e1000_ring));
  12.663 +
  12.664 +	adapter->tx_ring = tx_ring;
  12.665 +	adapter->rx_ring = rx_ring;
  12.666 +
  12.667 +	rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
  12.668 +	rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD));
  12.669 +	rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
  12.670 +
  12.671 +	tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
  12.672 +	tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD));
  12.673 +	tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
  12.674 +
  12.675 +	if (netif_running(adapter->netdev)) {
  12.676 +		/* Try to get new resources before deleting old */
  12.677 +		err = e1000e_setup_rx_resources(adapter);
  12.678 +		if (err)
  12.679 +			goto err_setup_rx;
  12.680 +		err = e1000e_setup_tx_resources(adapter);
  12.681 +		if (err)
  12.682 +			goto err_setup_tx;
  12.683 +
  12.684 +		/*
  12.685 +		 * restore the old in order to free it,
  12.686 +		 * then add in the new
  12.687 +		 */
  12.688 +		adapter->rx_ring = rx_old;
  12.689 +		adapter->tx_ring = tx_old;
  12.690 +		e1000e_free_rx_resources(adapter);
  12.691 +		e1000e_free_tx_resources(adapter);
  12.692 +		kfree(tx_old);
  12.693 +		kfree(rx_old);
  12.694 +		adapter->rx_ring = rx_ring;
  12.695 +		adapter->tx_ring = tx_ring;
  12.696 +		err = e1000e_up(adapter);
  12.697 +		if (err)
  12.698 +			goto err_setup;
  12.699 +	}
  12.700 +
  12.701 +	clear_bit(__E1000_RESETTING, &adapter->state);
  12.702 +	return 0;
  12.703 +err_setup_tx:
  12.704 +	e1000e_free_rx_resources(adapter);
  12.705 +err_setup_rx:
  12.706 +	adapter->rx_ring = rx_old;
  12.707 +	adapter->tx_ring = tx_old;
  12.708 +	kfree(rx_ring);
  12.709 +err_alloc_rx:
  12.710 +	kfree(tx_ring);
  12.711 +err_alloc_tx:
  12.712 +	e1000e_up(adapter);
  12.713 +err_setup:
  12.714 +	clear_bit(__E1000_RESETTING, &adapter->state);
  12.715 +	return err;
  12.716 +}
  12.717 +
  12.718 +static int reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
  12.719 +			     int reg, int offset, u32 mask, u32 write)
  12.720 +{
  12.721 +	u32 pat, val;
  12.722 +	static const u32 test[] =
  12.723 +		{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
  12.724 +	for (pat = 0; pat < ARRAY_SIZE(test); pat++) {
  12.725 +		E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset,
  12.726 +				      (test[pat] & write));
  12.727 +		val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
  12.728 +		if (val != (test[pat] & write & mask)) {
  12.729 +			e_err("pattern test reg %04X failed: got 0x%08X "
  12.730 +			      "expected 0x%08X\n", reg + offset, val,
  12.731 +			      (test[pat] & write & mask));
  12.732 +			*data = reg;
  12.733 +			return 1;
  12.734 +		}
  12.735 +	}
  12.736 +	return 0;
  12.737 +}
  12.738 +
  12.739 +static int reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
  12.740 +			      int reg, u32 mask, u32 write)
  12.741 +{
  12.742 +	u32 val;
  12.743 +	__ew32(&adapter->hw, reg, write & mask);
  12.744 +	val = __er32(&adapter->hw, reg);
  12.745 +	if ((write & mask) != (val & mask)) {
  12.746 +		e_err("set/check reg %04X test failed: got 0x%08X "
  12.747 +		      "expected 0x%08X\n", reg, (val & mask), (write & mask));
  12.748 +		*data = reg;
  12.749 +		return 1;
  12.750 +	}
  12.751 +	return 0;
  12.752 +}
  12.753 +#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write)                       \
  12.754 +	do {                                                                   \
  12.755 +		if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \
  12.756 +			return 1;                                              \
  12.757 +	} while (0)
  12.758 +#define REG_PATTERN_TEST(reg, mask, write)                                     \
  12.759 +	REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
  12.760 +
  12.761 +#define REG_SET_AND_CHECK(reg, mask, write)                                    \
  12.762 +	do {                                                                   \
  12.763 +		if (reg_set_and_check(adapter, data, reg, mask, write))        \
  12.764 +			return 1;                                              \
  12.765 +	} while (0)
  12.766 +
  12.767 +static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
  12.768 +{
  12.769 +	struct e1000_hw *hw = &adapter->hw;
  12.770 +	struct e1000_mac_info *mac = &adapter->hw.mac;
  12.771 +	u32 value;
  12.772 +	u32 before;
  12.773 +	u32 after;
  12.774 +	u32 i;
  12.775 +	u32 toggle;
  12.776 +
  12.777 +	/*
  12.778 +	 * The status register is Read Only, so a write should fail.
  12.779 +	 * Some bits that get toggled are ignored.
  12.780 +	 */
  12.781 +	switch (mac->type) {
  12.782 +	/* there are several bits on newer hardware that are r/w */
  12.783 +	case e1000_82571:
  12.784 +	case e1000_82572:
  12.785 +	case e1000_80003es2lan:
  12.786 +		toggle = 0x7FFFF3FF;
  12.787 +		break;
  12.788 +	case e1000_82573:
  12.789 +	case e1000_82574:
  12.790 +	case e1000_ich8lan:
  12.791 +	case e1000_ich9lan:
  12.792 +	case e1000_ich10lan:
  12.793 +		toggle = 0x7FFFF033;
  12.794 +		break;
  12.795 +	default:
  12.796 +		toggle = 0xFFFFF833;
  12.797 +		break;
  12.798 +	}
  12.799 +
  12.800 +	before = er32(STATUS);
  12.801 +	value = (er32(STATUS) & toggle);
  12.802 +	ew32(STATUS, toggle);
  12.803 +	after = er32(STATUS) & toggle;
  12.804 +	if (value != after) {
  12.805 +		e_err("failed STATUS register test got: 0x%08X expected: "
  12.806 +		      "0x%08X\n", after, value);
  12.807 +		*data = 1;
  12.808 +		return 1;
  12.809 +	}
  12.810 +	/* restore previous status */
  12.811 +	ew32(STATUS, before);
  12.812 +
  12.813 +	if (!(adapter->flags & FLAG_IS_ICH)) {
  12.814 +		REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
  12.815 +		REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
  12.816 +		REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
  12.817 +		REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
  12.818 +	}
  12.819 +
  12.820 +	REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
  12.821 +	REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
  12.822 +	REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF);
  12.823 +	REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF);
  12.824 +	REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF);
  12.825 +	REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
  12.826 +	REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
  12.827 +	REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
  12.828 +	REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
  12.829 +	REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF);
  12.830 +
  12.831 +	REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
  12.832 +
  12.833 +	before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
  12.834 +	REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
  12.835 +	REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
  12.836 +
  12.837 +	REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
  12.838 +	REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
  12.839 +	if (!(adapter->flags & FLAG_IS_ICH))
  12.840 +		REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
  12.841 +	REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
  12.842 +	REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
  12.843 +	for (i = 0; i < mac->rar_entry_count; i++)
  12.844 +		REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
  12.845 +				       ((mac->type == e1000_ich10lan) ?
  12.846 +					   0x8007FFFF : 0x8003FFFF),
  12.847 +				       0xFFFFFFFF);
  12.848 +
  12.849 +	for (i = 0; i < mac->mta_reg_count; i++)
  12.850 +		REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
  12.851 +
  12.852 +	*data = 0;
  12.853 +	return 0;
  12.854 +}
  12.855 +
  12.856 +static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
  12.857 +{
  12.858 +	u16 temp;
  12.859 +	u16 checksum = 0;
  12.860 +	u16 i;
  12.861 +
  12.862 +	*data = 0;
  12.863 +	/* Read and add up the contents of the EEPROM */
  12.864 +	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
  12.865 +		if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) {
  12.866 +			*data = 1;
  12.867 +			break;
  12.868 +		}
  12.869 +		checksum += temp;
  12.870 +	}
  12.871 +
  12.872 +	/* If Checksum is not Correct return error else test passed */
  12.873 +	if ((checksum != (u16) NVM_SUM) && !(*data))
  12.874 +		*data = 2;
  12.875 +
  12.876 +	return *data;
  12.877 +}
  12.878 +
  12.879 +static irqreturn_t e1000_test_intr(int irq, void *data, struct pt_regs *regs)
  12.880 +{
  12.881 +	struct net_device *netdev = (struct net_device *) data;
  12.882 +	struct e1000_adapter *adapter = netdev_priv(netdev);
  12.883 +	struct e1000_hw *hw = &adapter->hw;
  12.884 +
  12.885 +	adapter->test_icr |= er32(ICR);
  12.886 +
  12.887 +	return IRQ_HANDLED;
  12.888 +}
  12.889 +
  12.890 +static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
  12.891 +{
  12.892 +	struct net_device *netdev = adapter->netdev;
  12.893 +	struct e1000_hw *hw = &adapter->hw;
  12.894 +	u32 mask;
  12.895 +	u32 shared_int = 1;
  12.896 +	u32 irq = adapter->pdev->irq;
  12.897 +	int i;
  12.898 +	int ret_val = 0;
  12.899 +	int int_mode = E1000E_INT_MODE_LEGACY;
  12.900 +
  12.901 +	*data = 0;
  12.902 +
  12.903 +	/* NOTE: we don't test MSI/MSI-X interrupts here, yet */
  12.904 +	if (adapter->int_mode == E1000E_INT_MODE_MSIX) {
  12.905 +		int_mode = adapter->int_mode;
  12.906 +		e1000e_reset_interrupt_capability(adapter);
  12.907 +		adapter->int_mode = E1000E_INT_MODE_LEGACY;
  12.908 +		e1000e_set_interrupt_capability(adapter);
  12.909 +	}
  12.910 +	/* Hook up test interrupt handler just for this test */
  12.911 +	if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
  12.912 +			 netdev)) {
  12.913 +		shared_int = 0;
  12.914 +	} else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
  12.915 +		 netdev->name, netdev)) {
  12.916 +		*data = 1;
  12.917 +		ret_val = -1;
  12.918 +		goto out;
  12.919 +	}
  12.920 +	e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared"));
  12.921 +
  12.922 +	/* Disable all the interrupts */
  12.923 +	ew32(IMC, 0xFFFFFFFF);
  12.924 +	msleep(10);
  12.925 +
  12.926 +	/* Test each interrupt */
  12.927 +	for (i = 0; i < 10; i++) {
  12.928 +		/* Interrupt to test */
  12.929 +		mask = 1 << i;
  12.930 +
  12.931 +		if (adapter->flags & FLAG_IS_ICH) {
  12.932 +			switch (mask) {
  12.933 +			case E1000_ICR_RXSEQ:
  12.934 +				continue;
  12.935 +			case 0x00000100:
  12.936 +				if (adapter->hw.mac.type == e1000_ich8lan ||
  12.937 +				    adapter->hw.mac.type == e1000_ich9lan)
  12.938 +					continue;
  12.939 +				break;
  12.940 +			default:
  12.941 +				break;
  12.942 +			}
  12.943 +		}
  12.944 +
  12.945 +		if (!shared_int) {
  12.946 +			/*
  12.947 +			 * Disable the interrupt to be reported in
  12.948 +			 * the cause register and then force the same
  12.949 +			 * interrupt and see if one gets posted.  If
  12.950 +			 * an interrupt was posted to the bus, the
  12.951 +			 * test failed.
  12.952 +			 */
  12.953 +			adapter->test_icr = 0;
  12.954 +			ew32(IMC, mask);
  12.955 +			ew32(ICS, mask);
  12.956 +			msleep(10);
  12.957 +
  12.958 +			if (adapter->test_icr & mask) {
  12.959 +				*data = 3;
  12.960 +				break;
  12.961 +			}
  12.962 +		}
  12.963 +
  12.964 +		/*
  12.965 +		 * Enable the interrupt to be reported in
  12.966 +		 * the cause register and then force the same
  12.967 +		 * interrupt and see if one gets posted.  If
  12.968 +		 * an interrupt was not posted to the bus, the
  12.969 +		 * test failed.
  12.970 +		 */
  12.971 +		adapter->test_icr = 0;
  12.972 +		ew32(IMS, mask);
  12.973 +		ew32(ICS, mask);
  12.974 +		msleep(10);
  12.975 +
  12.976 +		if (!(adapter->test_icr & mask)) {
  12.977 +			*data = 4;
  12.978 +			break;
  12.979 +		}
  12.980 +
  12.981 +		if (!shared_int) {
  12.982 +			/*
  12.983 +			 * Disable the other interrupts to be reported in
  12.984 +			 * the cause register and then force the other
  12.985 +			 * interrupts and see if any get posted.  If
  12.986 +			 * an interrupt was posted to the bus, the
  12.987 +			 * test failed.
  12.988 +			 */
  12.989 +			adapter->test_icr = 0;
  12.990 +			ew32(IMC, ~mask & 0x00007FFF);
  12.991 +			ew32(ICS, ~mask & 0x00007FFF);
  12.992 +			msleep(10);
  12.993 +
  12.994 +			if (adapter->test_icr) {
  12.995 +				*data = 5;
  12.996 +				break;
  12.997 +			}
  12.998 +		}
  12.999 +	}
 12.1000 +
 12.1001 +	/* Disable all the interrupts */
 12.1002 +	ew32(IMC, 0xFFFFFFFF);
 12.1003 +	msleep(10);
 12.1004 +
 12.1005 +	/* Unhook test interrupt handler */
 12.1006 +	free_irq(irq, netdev);
 12.1007 +
 12.1008 +out:
 12.1009 +	if (int_mode == E1000E_INT_MODE_MSIX) {
 12.1010 +		e1000e_reset_interrupt_capability(adapter);
 12.1011 +		adapter->int_mode = int_mode;
 12.1012 +		e1000e_set_interrupt_capability(adapter);
 12.1013 +	}
 12.1014 +
 12.1015 +	return ret_val;
 12.1016 +}
 12.1017 +
 12.1018 +static void e1000_free_desc_rings(struct e1000_adapter *adapter)
 12.1019 +{
 12.1020 +	struct e1000_ring *tx_ring = &adapter->test_tx_ring;
 12.1021 +	struct e1000_ring *rx_ring = &adapter->test_rx_ring;
 12.1022 +	struct pci_dev *pdev = adapter->pdev;
 12.1023 +	int i;
 12.1024 +
 12.1025 +	if (tx_ring->desc && tx_ring->buffer_info) {
 12.1026 +		for (i = 0; i < tx_ring->count; i++) {
 12.1027 +			if (tx_ring->buffer_info[i].dma)
 12.1028 +				pci_unmap_single(pdev,
 12.1029 +					tx_ring->buffer_info[i].dma,
 12.1030 +					tx_ring->buffer_info[i].length,
 12.1031 +					PCI_DMA_TODEVICE);
 12.1032 +			if (tx_ring->buffer_info[i].skb)
 12.1033 +				dev_kfree_skb(tx_ring->buffer_info[i].skb);
 12.1034 +		}
 12.1035 +	}
 12.1036 +
 12.1037 +	if (rx_ring->desc && rx_ring->buffer_info) {
 12.1038 +		for (i = 0; i < rx_ring->count; i++) {
 12.1039 +			if (rx_ring->buffer_info[i].dma)
 12.1040 +				pci_unmap_single(pdev,
 12.1041 +					rx_ring->buffer_info[i].dma,
 12.1042 +					2048, PCI_DMA_FROMDEVICE);
 12.1043 +			if (rx_ring->buffer_info[i].skb)
 12.1044 +				dev_kfree_skb(rx_ring->buffer_info[i].skb);
 12.1045 +		}
 12.1046 +	}
 12.1047 +
 12.1048 +	if (tx_ring->desc) {
 12.1049 +		dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
 12.1050 +				  tx_ring->dma);
 12.1051 +		tx_ring->desc = NULL;
 12.1052 +	}
 12.1053 +	if (rx_ring->desc) {
 12.1054 +		dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
 12.1055 +				  rx_ring->dma);
 12.1056 +		rx_ring->desc = NULL;
 12.1057 +	}
 12.1058 +
 12.1059 +	kfree(tx_ring->buffer_info);
 12.1060 +	tx_ring->buffer_info = NULL;
 12.1061 +	kfree(rx_ring->buffer_info);
 12.1062 +	rx_ring->buffer_info = NULL;
 12.1063 +}
 12.1064 +
 12.1065 +static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
 12.1066 +{
 12.1067 +	struct e1000_ring *tx_ring = &adapter->test_tx_ring;
 12.1068 +	struct e1000_ring *rx_ring = &adapter->test_rx_ring;
 12.1069 +	struct pci_dev *pdev = adapter->pdev;
 12.1070 +	struct e1000_hw *hw = &adapter->hw;
 12.1071 +	u32 rctl;
 12.1072 +	int i;
 12.1073 +	int ret_val;
 12.1074 +
 12.1075 +	/* Setup Tx descriptor ring and Tx buffers */
 12.1076 +
 12.1077 +	if (!tx_ring->count)
 12.1078 +		tx_ring->count = E1000_DEFAULT_TXD;
 12.1079 +
 12.1080 +	tx_ring->buffer_info = kcalloc(tx_ring->count,
 12.1081 +				       sizeof(struct e1000_buffer),
 12.1082 +				       GFP_KERNEL);
 12.1083 +	if (!(tx_ring->buffer_info)) {
 12.1084 +		ret_val = 1;
 12.1085 +		goto err_nomem;
 12.1086 +	}
 12.1087 +
 12.1088 +	tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
 12.1089 +	tx_ring->size = ALIGN(tx_ring->size, 4096);
 12.1090 +	tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
 12.1091 +					   &tx_ring->dma, GFP_KERNEL);
 12.1092 +	if (!tx_ring->desc) {
 12.1093 +		ret_val = 2;
 12.1094 +		goto err_nomem;
 12.1095 +	}
 12.1096 +	tx_ring->next_to_use = 0;
 12.1097 +	tx_ring->next_to_clean = 0;
 12.1098 +
 12.1099 +	ew32(TDBAL, ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
 12.1100 +	ew32(TDBAH, ((u64) tx_ring->dma >> 32));
 12.1101 +	ew32(TDLEN, tx_ring->count * sizeof(struct e1000_tx_desc));
 12.1102 +	ew32(TDH, 0);
 12.1103 +	ew32(TDT, 0);
 12.1104 +	ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR |
 12.1105 +	     E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
 12.1106 +	     E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
 12.1107 +
 12.1108 +	for (i = 0; i < tx_ring->count; i++) {
 12.1109 +		struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
 12.1110 +		struct sk_buff *skb;
 12.1111 +		unsigned int skb_size = 1024;
 12.1112 +
 12.1113 +		skb = alloc_skb(skb_size, GFP_KERNEL);
 12.1114 +		if (!skb) {
 12.1115 +			ret_val = 3;
 12.1116 +			goto err_nomem;
 12.1117 +		}
 12.1118 +		skb_put(skb, skb_size);
 12.1119 +		tx_ring->buffer_info[i].skb = skb;
 12.1120 +		tx_ring->buffer_info[i].length = skb->len;
 12.1121 +		tx_ring->buffer_info[i].dma =
 12.1122 +			pci_map_single(pdev, skb->data, skb->len,
 12.1123 +				       PCI_DMA_TODEVICE);
 12.1124 +		if (pci_dma_mapping_error(tx_ring->buffer_info[i].dma)) {
 12.1125 +			ret_val = 4;
 12.1126 +			goto err_nomem;
 12.1127 +		}
 12.1128 +		tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
 12.1129 +		tx_desc->lower.data = cpu_to_le32(skb->len);
 12.1130 +		tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
 12.1131 +						   E1000_TXD_CMD_IFCS |
 12.1132 +						   E1000_TXD_CMD_RS);
 12.1133 +		tx_desc->upper.data = 0;
 12.1134 +	}
 12.1135 +
 12.1136 +	/* Setup Rx descriptor ring and Rx buffers */
 12.1137 +
 12.1138 +	if (!rx_ring->count)
 12.1139 +		rx_ring->count = E1000_DEFAULT_RXD;
 12.1140 +
 12.1141 +	rx_ring->buffer_info = kcalloc(rx_ring->count,
 12.1142 +				       sizeof(struct e1000_buffer),
 12.1143 +				       GFP_KERNEL);
 12.1144 +	if (!(rx_ring->buffer_info)) {
 12.1145 +		ret_val = 5;
 12.1146 +		goto err_nomem;
 12.1147 +	}
 12.1148 +
 12.1149 +	rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
 12.1150 +	rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
 12.1151 +					   &rx_ring->dma, GFP_KERNEL);
 12.1152 +	if (!rx_ring->desc) {
 12.1153 +		ret_val = 6;
 12.1154 +		goto err_nomem;
 12.1155 +	}
 12.1156 +	rx_ring->next_to_use = 0;
 12.1157 +	rx_ring->next_to_clean = 0;
 12.1158 +
 12.1159 +	rctl = er32(RCTL);
 12.1160 +	ew32(RCTL, rctl & ~E1000_RCTL_EN);
 12.1161 +	ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF));
 12.1162 +	ew32(RDBAH, ((u64) rx_ring->dma >> 32));
 12.1163 +	ew32(RDLEN, rx_ring->size);
 12.1164 +	ew32(RDH, 0);
 12.1165 +	ew32(RDT, 0);
 12.1166 +	rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
 12.1167 +		E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE |
 12.1168 +		E1000_RCTL_SBP | E1000_RCTL_SECRC |
 12.1169 +		E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
 12.1170 +		(adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
 12.1171 +	ew32(RCTL, rctl);
 12.1172 +
 12.1173 +	for (i = 0; i < rx_ring->count; i++) {
 12.1174 +		struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
 12.1175 +		struct sk_buff *skb;
 12.1176 +
 12.1177 +		skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL);
 12.1178 +		if (!skb) {
 12.1179 +			ret_val = 7;
 12.1180 +			goto err_nomem;
 12.1181 +		}
 12.1182 +		skb_reserve(skb, NET_IP_ALIGN);
 12.1183 +		rx_ring->buffer_info[i].skb = skb;
 12.1184 +		rx_ring->buffer_info[i].dma =
 12.1185 +			pci_map_single(pdev, skb->data, 2048,
 12.1186 +				       PCI_DMA_FROMDEVICE);
 12.1187 +		if (pci_dma_mapping_error(rx_ring->buffer_info[i].dma)) {
 12.1188 +			ret_val = 8;
 12.1189 +			goto err_nomem;
 12.1190 +		}
 12.1191 +		rx_desc->buffer_addr =
 12.1192 +			cpu_to_le64(rx_ring->buffer_info[i].dma);
 12.1193 +		memset(skb->data, 0x00, skb->len);
 12.1194 +	}
 12.1195 +
 12.1196 +	return 0;
 12.1197 +
 12.1198 +err_nomem:
 12.1199 +	e1000_free_desc_rings(adapter);
 12.1200 +	return ret_val;
 12.1201 +}
 12.1202 +
 12.1203 +static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
 12.1204 +{
 12.1205 +	/* Write out to PHY registers 29 and 30 to disable the Receiver. */
 12.1206 +	e1e_wphy(&adapter->hw, 29, 0x001F);
 12.1207 +	e1e_wphy(&adapter->hw, 30, 0x8FFC);
 12.1208 +	e1e_wphy(&adapter->hw, 29, 0x001A);
 12.1209 +	e1e_wphy(&adapter->hw, 30, 0x8FF0);
 12.1210 +}
 12.1211 +
 12.1212 +static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
 12.1213 +{
 12.1214 +	struct e1000_hw *hw = &adapter->hw;
 12.1215 +	u32 ctrl_reg = 0;
 12.1216 +	u32 stat_reg = 0;
 12.1217 +	u16 phy_reg = 0;
 12.1218 +
 12.1219 +	hw->mac.autoneg = 0;
 12.1220 +
 12.1221 +	if (hw->phy.type == e1000_phy_m88) {
 12.1222 +		/* Auto-MDI/MDIX Off */
 12.1223 +		e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
 12.1224 +		/* reset to update Auto-MDI/MDIX */
 12.1225 +		e1e_wphy(hw, PHY_CONTROL, 0x9140);
 12.1226 +		/* autoneg off */
 12.1227 +		e1e_wphy(hw, PHY_CONTROL, 0x8140);
 12.1228 +	} else if (hw->phy.type == e1000_phy_gg82563)
 12.1229 +		e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
 12.1230 +
 12.1231 +	ctrl_reg = er32(CTRL);
 12.1232 +
 12.1233 +	switch (hw->phy.type) {
 12.1234 +	case e1000_phy_ife:
 12.1235 +		/* force 100, set loopback */
 12.1236 +		e1e_wphy(hw, PHY_CONTROL, 0x6100);
 12.1237 +
 12.1238 +		/* Now set up the MAC to the same speed/duplex as the PHY. */
 12.1239 +		ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
 12.1240 +		ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
 12.1241 +			     E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
 12.1242 +			     E1000_CTRL_SPD_100 |/* Force Speed to 100 */
 12.1243 +			     E1000_CTRL_FD);	 /* Force Duplex to FULL */
 12.1244 +		break;
 12.1245 +	case e1000_phy_bm:
 12.1246 +		/* Set Default MAC Interface speed to 1GB */
 12.1247 +		e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);
 12.1248 +		phy_reg &= ~0x0007;
 12.1249 +		phy_reg |= 0x006;
 12.1250 +		e1e_wphy(hw, PHY_REG(2, 21), phy_reg);
 12.1251 +		/* Assert SW reset for above settings to take effect */
 12.1252 +		e1000e_commit_phy(hw);
 12.1253 +		mdelay(1);
 12.1254 +		/* Force Full Duplex */
 12.1255 +		e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
 12.1256 +		e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
 12.1257 +		/* Set Link Up (in force link) */
 12.1258 +		e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);
 12.1259 +		e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);
 12.1260 +		/* Force Link */
 12.1261 +		e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
 12.1262 +		e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);
 12.1263 +		/* Set Early Link Enable */
 12.1264 +		e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
 12.1265 +		e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);
 12.1266 +		/* fall through */
 12.1267 +	default:
 12.1268 +		/* force 1000, set loopback */
 12.1269 +		e1e_wphy(hw, PHY_CONTROL, 0x4140);
 12.1270 +		mdelay(250);
 12.1271 +
 12.1272 +		/* Now set up the MAC to the same speed/duplex as the PHY. */
 12.1273 +		ctrl_reg = er32(CTRL);
 12.1274 +		ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
 12.1275 +		ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
 12.1276 +			     E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
 12.1277 +			     E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
 12.1278 +			     E1000_CTRL_FD);	 /* Force Duplex to FULL */
 12.1279 +
 12.1280 +		if (adapter->flags & FLAG_IS_ICH)
 12.1281 +			ctrl_reg |= E1000_CTRL_SLU;	/* Set Link Up */
 12.1282 +	}
 12.1283 +
 12.1284 +	if (hw->phy.media_type == e1000_media_type_copper &&
 12.1285 +	    hw->phy.type == e1000_phy_m88) {
 12.1286 +		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
 12.1287 +	} else {
 12.1288 +		/*
 12.1289 +		 * Set the ILOS bit on the fiber Nic if half duplex link is
 12.1290 +		 * detected.
 12.1291 +		 */
 12.1292 +		stat_reg = er32(STATUS);
 12.1293 +		if ((stat_reg & E1000_STATUS_FD) == 0)
 12.1294 +			ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
 12.1295 +	}
 12.1296 +
 12.1297 +	ew32(CTRL, ctrl_reg);
 12.1298 +
 12.1299 +	/*
 12.1300 +	 * Disable the receiver on the PHY so when a cable is plugged in, the
 12.1301 +	 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
 12.1302 +	 */
 12.1303 +	if (hw->phy.type == e1000_phy_m88)
 12.1304 +		e1000_phy_disable_receiver(adapter);
 12.1305 +
 12.1306 +	udelay(500);
 12.1307 +
 12.1308 +	return 0;
 12.1309 +}
 12.1310 +
 12.1311 +static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
 12.1312 +{
 12.1313 +	struct e1000_hw *hw = &adapter->hw;
 12.1314 +	u32 ctrl = er32(CTRL);
 12.1315 +	int link = 0;
 12.1316 +
 12.1317 +	/* special requirements for 82571/82572 fiber adapters */
 12.1318 +
 12.1319 +	/*
 12.1320 +	 * jump through hoops to make sure link is up because serdes
 12.1321 +	 * link is hardwired up
 12.1322 +	 */
 12.1323 +	ctrl |= E1000_CTRL_SLU;
 12.1324 +	ew32(CTRL, ctrl);
 12.1325 +
 12.1326 +	/* disable autoneg */
 12.1327 +	ctrl = er32(TXCW);
 12.1328 +	ctrl &= ~(1 << 31);
 12.1329 +	ew32(TXCW, ctrl);
 12.1330 +
 12.1331 +	link = (er32(STATUS) & E1000_STATUS_LU);
 12.1332 +
 12.1333 +	if (!link) {
 12.1334 +		/* set invert loss of signal */
 12.1335 +		ctrl = er32(CTRL);
 12.1336 +		ctrl |= E1000_CTRL_ILOS;
 12.1337 +		ew32(CTRL, ctrl);
 12.1338 +	}
 12.1339 +
 12.1340 +	/*
 12.1341 +	 * special write to serdes control register to enable SerDes analog
 12.1342 +	 * loopback
 12.1343 +	 */
 12.1344 +#define E1000_SERDES_LB_ON 0x410
 12.1345 +	ew32(SCTL, E1000_SERDES_LB_ON);
 12.1346 +	msleep(10);
 12.1347 +
 12.1348 +	return 0;
 12.1349 +}
 12.1350 +
 12.1351 +/* only call this for fiber/serdes connections to es2lan */
 12.1352 +static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
 12.1353 +{
 12.1354 +	struct e1000_hw *hw = &adapter->hw;
 12.1355 +	u32 ctrlext = er32(CTRL_EXT);
 12.1356 +	u32 ctrl = er32(CTRL);
 12.1357 +
 12.1358 +	/*
 12.1359 +	 * save CTRL_EXT to restore later, reuse an empty variable (unused
 12.1360 +	 * on mac_type 80003es2lan)
 12.1361 +	 */
 12.1362 +	adapter->tx_fifo_head = ctrlext;
 12.1363 +
 12.1364 +	/* clear the serdes mode bits, putting the device into mac loopback */
 12.1365 +	ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 12.1366 +	ew32(CTRL_EXT, ctrlext);
 12.1367 +
 12.1368 +	/* force speed to 1000/FD, link up */
 12.1369 +	ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
 12.1370 +	ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
 12.1371 +		 E1000_CTRL_SPD_1000 | E1000_CTRL_FD);
 12.1372 +	ew32(CTRL, ctrl);
 12.1373 +
 12.1374 +	/* set mac loopback */
 12.1375 +	ctrl = er32(RCTL);
 12.1376 +	ctrl |= E1000_RCTL_LBM_MAC;
 12.1377 +	ew32(RCTL, ctrl);
 12.1378 +
 12.1379 +	/* set testing mode parameters (no need to reset later) */
 12.1380 +#define KMRNCTRLSTA_OPMODE (0x1F << 16)
 12.1381 +#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582
 12.1382 +	ew32(KMRNCTRLSTA,
 12.1383 +	     (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII));
 12.1384 +
 12.1385 +	return 0;
 12.1386 +}
 12.1387 +
 12.1388 +static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
 12.1389 +{
 12.1390 +	struct e1000_hw *hw = &adapter->hw;
 12.1391 +	u32 rctl;
 12.1392 +
 12.1393 +	if (hw->phy.media_type == e1000_media_type_fiber ||
 12.1394 +	    hw->phy.media_type == e1000_media_type_internal_serdes) {
 12.1395 +		switch (hw->mac.type) {
 12.1396 +		case e1000_80003es2lan:
 12.1397 +			return e1000_set_es2lan_mac_loopback(adapter);
 12.1398 +			break;
 12.1399 +		case e1000_82571:
 12.1400 +		case e1000_82572:
 12.1401 +			return e1000_set_82571_fiber_loopback(adapter);
 12.1402 +			break;
 12.1403 +		default:
 12.1404 +			rctl = er32(RCTL);
 12.1405 +			rctl |= E1000_RCTL_LBM_TCVR;
 12.1406 +			ew32(RCTL, rctl);
 12.1407 +			return 0;
 12.1408 +		}
 12.1409 +	} else if (hw->phy.media_type == e1000_media_type_copper) {
 12.1410 +		return e1000_integrated_phy_loopback(adapter);
 12.1411 +	}
 12.1412 +
 12.1413 +	return 7;
 12.1414 +}
 12.1415 +
 12.1416 +static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
 12.1417 +{
 12.1418 +	struct e1000_hw *hw = &adapter->hw;
 12.1419 +	u32 rctl;
 12.1420 +	u16 phy_reg;
 12.1421 +
 12.1422 +	rctl = er32(RCTL);
 12.1423 +	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
 12.1424 +	ew32(RCTL, rctl);
 12.1425 +
 12.1426 +	switch (hw->mac.type) {
 12.1427 +	case e1000_80003es2lan:
 12.1428 +		if (hw->phy.media_type == e1000_media_type_fiber ||
 12.1429 +		    hw->phy.media_type == e1000_media_type_internal_serdes) {
 12.1430 +			/* restore CTRL_EXT, stealing space from tx_fifo_head */
 12.1431 +			ew32(CTRL_EXT, adapter->tx_fifo_head);
 12.1432 +			adapter->tx_fifo_head = 0;
 12.1433 +		}
 12.1434 +		/* fall through */
 12.1435 +	case e1000_82571:
 12.1436 +	case e1000_82572:
 12.1437 +		if (hw->phy.media_type == e1000_media_type_fiber ||
 12.1438 +		    hw->phy.media_type == e1000_media_type_internal_serdes) {
 12.1439 +#define E1000_SERDES_LB_OFF 0x400
 12.1440 +			ew32(SCTL, E1000_SERDES_LB_OFF);
 12.1441 +			msleep(10);
 12.1442 +			break;
 12.1443 +		}
 12.1444 +		/* Fall Through */
 12.1445 +	default:
 12.1446 +		hw->mac.autoneg = 1;
 12.1447 +		if (hw->phy.type == e1000_phy_gg82563)
 12.1448 +			e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
 12.1449 +		e1e_rphy(hw, PHY_CONTROL, &phy_reg);
 12.1450 +		if (phy_reg & MII_CR_LOOPBACK) {
 12.1451 +			phy_reg &= ~MII_CR_LOOPBACK;
 12.1452 +			e1e_wphy(hw, PHY_CONTROL, phy_reg);
 12.1453 +			e1000e_commit_phy(hw);
 12.1454 +		}
 12.1455 +		break;
 12.1456 +	}
 12.1457 +}
 12.1458 +
 12.1459 +static void e1000_create_lbtest_frame(struct sk_buff *skb,
 12.1460 +				      unsigned int frame_size)
 12.1461 +{
 12.1462 +	memset(skb->data, 0xFF, frame_size);
 12.1463 +	frame_size &= ~1;
 12.1464 +	memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
 12.1465 +	memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
 12.1466 +	memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
 12.1467 +}
 12.1468 +
 12.1469 +static int e1000_check_lbtest_frame(struct sk_buff *skb,
 12.1470 +				    unsigned int frame_size)
 12.1471 +{
 12.1472 +	frame_size &= ~1;
 12.1473 +	if (*(skb->data + 3) == 0xFF)
 12.1474 +		if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
 12.1475 +		   (*(skb->data + frame_size / 2 + 12) == 0xAF))
 12.1476 +			return 0;
 12.1477 +	return 13;
 12.1478 +}
 12.1479 +
 12.1480 +static int e1000_run_loopback_test(struct e1000_adapter *adapter)
 12.1481 +{
 12.1482 +	struct e1000_ring *tx_ring = &adapter->test_tx_ring;
 12.1483 +	struct e1000_ring *rx_ring = &adapter->test_rx_ring;
 12.1484 +	struct pci_dev *pdev = adapter->pdev;
 12.1485 +	struct e1000_hw *hw = &adapter->hw;
 12.1486 +	int i, j, k, l;
 12.1487 +	int lc;
 12.1488 +	int good_cnt;
 12.1489 +	int ret_val = 0;
 12.1490 +	unsigned long time;
 12.1491 +
 12.1492 +	ew32(RDT, rx_ring->count - 1);
 12.1493 +
 12.1494 +	/*
 12.1495 +	 * Calculate the loop count based on the largest descriptor ring
 12.1496 +	 * The idea is to wrap the largest ring a number of times using 64
 12.1497 +	 * send/receive pairs during each loop
 12.1498 +	 */
 12.1499 +
 12.1500 +	if (rx_ring->count <= tx_ring->count)
 12.1501 +		lc = ((tx_ring->count / 64) * 2) + 1;
 12.1502 +	else
 12.1503 +		lc = ((rx_ring->count / 64) * 2) + 1;
 12.1504 +
 12.1505 +	k = 0;
 12.1506 +	l = 0;
 12.1507 +	for (j = 0; j <= lc; j++) { /* loop count loop */
 12.1508 +		for (i = 0; i < 64; i++) { /* send the packets */
 12.1509 +			e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb,
 12.1510 +						  1024);
 12.1511 +			pci_dma_sync_single_for_device(pdev,
 12.1512 +					tx_ring->buffer_info[k].dma,
 12.1513 +					tx_ring->buffer_info[k].length,
 12.1514 +					PCI_DMA_TODEVICE);
 12.1515 +			k++;
 12.1516 +			if (k == tx_ring->count)
 12.1517 +				k = 0;
 12.1518 +		}
 12.1519 +		ew32(TDT, k);
 12.1520 +		msleep(200);
 12.1521 +		time = jiffies; /* set the start time for the receive */
 12.1522 +		good_cnt = 0;
 12.1523 +		do { /* receive the sent packets */
 12.1524 +			pci_dma_sync_single_for_cpu(pdev,
 12.1525 +					rx_ring->buffer_info[l].dma, 2048,
 12.1526 +					PCI_DMA_FROMDEVICE);
 12.1527 +
 12.1528 +			ret_val = e1000_check_lbtest_frame(
 12.1529 +					rx_ring->buffer_info[l].skb, 1024);
 12.1530 +			if (!ret_val)
 12.1531 +				good_cnt++;
 12.1532 +			l++;
 12.1533 +			if (l == rx_ring->count)
 12.1534 +				l = 0;
 12.1535 +			/*
 12.1536 +			 * time + 20 msecs (200 msecs on 2.4) is more than
 12.1537 +			 * enough time to complete the receives, if it's
 12.1538 +			 * exceeded, break and error off
 12.1539 +			 */
 12.1540 +		} while (good_cnt < 64 && jiffies < (time + 20));
 12.1541 +		if (good_cnt != 64) {
 12.1542 +			ret_val = 13; /* ret_val is the same as mis-compare */
 12.1543 +			break;
 12.1544 +		}
 12.1545 +		if (jiffies >= (time + 20)) {
 12.1546 +			ret_val = 14; /* error code for time out error */
 12.1547 +			break;
 12.1548 +		}
 12.1549 +	} /* end loop count loop */
 12.1550 +	return ret_val;
 12.1551 +}
 12.1552 +
 12.1553 +static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
 12.1554 +{
 12.1555 +	/*
 12.1556 +	 * PHY loopback cannot be performed if SoL/IDER
 12.1557 +	 * sessions are active
 12.1558 +	 */
 12.1559 +	if (e1000_check_reset_block(&adapter->hw)) {
 12.1560 +		e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
 12.1561 +		*data = 0;
 12.1562 +		goto out;
 12.1563 +	}
 12.1564 +
 12.1565 +	*data = e1000_setup_desc_rings(adapter);
 12.1566 +	if (*data)
 12.1567 +		goto out;
 12.1568 +
 12.1569 +	*data = e1000_setup_loopback_test(adapter);
 12.1570 +	if (*data)
 12.1571 +		goto err_loopback;
 12.1572 +
 12.1573 +	*data = e1000_run_loopback_test(adapter);
 12.1574 +	e1000_loopback_cleanup(adapter);
 12.1575 +
 12.1576 +err_loopback:
 12.1577 +	e1000_free_desc_rings(adapter);
 12.1578 +out:
 12.1579 +	return *data;
 12.1580 +}
 12.1581 +
 12.1582 +static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
 12.1583 +{
 12.1584 +	struct e1000_hw *hw = &adapter->hw;
 12.1585 +
 12.1586 +	*data = 0;
 12.1587 +	if (hw->phy.media_type == e1000_media_type_internal_serdes) {
 12.1588 +		int i = 0;
 12.1589 +		hw->mac.serdes_has_link = 0;
 12.1590 +
 12.1591 +		/*
 12.1592 +		 * On some blade server designs, link establishment
 12.1593 +		 * could take as long as 2-3 minutes
 12.1594 +		 */
 12.1595 +		do {
 12.1596 +			hw->mac.ops.check_for_link(hw);
 12.1597 +			if (hw->mac.serdes_has_link)
 12.1598 +				return *data;
 12.1599 +			msleep(20);
 12.1600 +		} while (i++ < 3750);
 12.1601 +
 12.1602 +		*data = 1;
 12.1603 +	} else {
 12.1604 +		hw->mac.ops.check_for_link(hw);
 12.1605 +		if (hw->mac.autoneg)
 12.1606 +			msleep(4000);
 12.1607 +
 12.1608 +		if (!(er32(STATUS) &
 12.1609 +		      E1000_STATUS_LU))
 12.1610 +			*data = 1;
 12.1611 +	}
 12.1612 +	return *data;
 12.1613 +}
 12.1614 +
 12.1615 +static int e1000_diag_test_count(struct net_device *netdev)
 12.1616 +{
 12.1617 +	return E1000_TEST_LEN;
 12.1618 +}
 12.1619 +
 12.1620 +static void e1000_diag_test(struct net_device *netdev,
 12.1621 +			    struct ethtool_test *eth_test, u64 *data)
 12.1622 +{
 12.1623 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1624 +	u16 autoneg_advertised;
 12.1625 +	u8 forced_speed_duplex;
 12.1626 +	u8 autoneg;
 12.1627 +	int if_running = netif_running(netdev);
 12.1628 +
 12.1629 +	set_bit(__E1000_TESTING, &adapter->state);
 12.1630 +	if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
 12.1631 +		/* Offline tests */
 12.1632 +
 12.1633 +		/* save speed, duplex, autoneg settings */
 12.1634 +		autoneg_advertised = adapter->hw.phy.autoneg_advertised;
 12.1635 +		forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
 12.1636 +		autoneg = adapter->hw.mac.autoneg;
 12.1637 +
 12.1638 +		e_info("offline testing starting\n");
 12.1639 +
 12.1640 +		/*
 12.1641 +		 * Link test performed before hardware reset so autoneg doesn't
 12.1642 +		 * interfere with test result
 12.1643 +		 */
 12.1644 +		if (e1000_link_test(adapter, &data[4]))
 12.1645 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1646 +
 12.1647 +		if (if_running)
 12.1648 +			/* indicate we're in test mode */
 12.1649 +			dev_close(netdev);
 12.1650 +		else
 12.1651 +			e1000e_reset(adapter);
 12.1652 +
 12.1653 +		if (e1000_reg_test(adapter, &data[0]))
 12.1654 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1655 +
 12.1656 +		e1000e_reset(adapter);
 12.1657 +		if (e1000_eeprom_test(adapter, &data[1]))
 12.1658 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1659 +
 12.1660 +		e1000e_reset(adapter);
 12.1661 +		if (e1000_intr_test(adapter, &data[2]))
 12.1662 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1663 +
 12.1664 +		e1000e_reset(adapter);
 12.1665 +		/* make sure the phy is powered up */
 12.1666 +		e1000e_power_up_phy(adapter);
 12.1667 +		if (e1000_loopback_test(adapter, &data[3]))
 12.1668 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1669 +
 12.1670 +		/* restore speed, duplex, autoneg settings */
 12.1671 +		adapter->hw.phy.autoneg_advertised = autoneg_advertised;
 12.1672 +		adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
 12.1673 +		adapter->hw.mac.autoneg = autoneg;
 12.1674 +
 12.1675 +		/* force this routine to wait until autoneg complete/timeout */
 12.1676 +		adapter->hw.phy.autoneg_wait_to_complete = 1;
 12.1677 +		e1000e_reset(adapter);
 12.1678 +		adapter->hw.phy.autoneg_wait_to_complete = 0;
 12.1679 +
 12.1680 +		clear_bit(__E1000_TESTING, &adapter->state);
 12.1681 +		if (if_running)
 12.1682 +			dev_open(netdev);
 12.1683 +	} else {
 12.1684 +		e_info("online testing starting\n");
 12.1685 +		/* Online tests */
 12.1686 +		if (e1000_link_test(adapter, &data[4]))
 12.1687 +			eth_test->flags |= ETH_TEST_FL_FAILED;
 12.1688 +
 12.1689 +		/* Online tests aren't run; pass by default */
 12.1690 +		data[0] = 0;
 12.1691 +		data[1] = 0;
 12.1692 +		data[2] = 0;
 12.1693 +		data[3] = 0;
 12.1694 +
 12.1695 +		clear_bit(__E1000_TESTING, &adapter->state);
 12.1696 +	}
 12.1697 +	msleep_interruptible(4 * 1000);
 12.1698 +}
 12.1699 +
 12.1700 +static void e1000_get_wol(struct net_device *netdev,
 12.1701 +			  struct ethtool_wolinfo *wol)
 12.1702 +{
 12.1703 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1704 +
 12.1705 +	wol->supported = 0;
 12.1706 +	wol->wolopts = 0;
 12.1707 +
 12.1708 +	if (!(adapter->flags & FLAG_HAS_WOL))
 12.1709 +		return;
 12.1710 +
 12.1711 +	wol->supported = WAKE_UCAST | WAKE_MCAST |
 12.1712 +	                 WAKE_BCAST | WAKE_MAGIC |
 12.1713 +	                 WAKE_PHY | WAKE_ARP;
 12.1714 +
 12.1715 +	/* apply any specific unsupported masks here */
 12.1716 +	if (adapter->flags & FLAG_NO_WAKE_UCAST) {
 12.1717 +		wol->supported &= ~WAKE_UCAST;
 12.1718 +
 12.1719 +		if (adapter->wol & E1000_WUFC_EX)
 12.1720 +			e_err("Interface does not support directed (unicast) "
 12.1721 +			      "frame wake-up packets\n");
 12.1722 +	}
 12.1723 +
 12.1724 +	if (adapter->wol & E1000_WUFC_EX)
 12.1725 +		wol->wolopts |= WAKE_UCAST;
 12.1726 +	if (adapter->wol & E1000_WUFC_MC)
 12.1727 +		wol->wolopts |= WAKE_MCAST;
 12.1728 +	if (adapter->wol & E1000_WUFC_BC)
 12.1729 +		wol->wolopts |= WAKE_BCAST;
 12.1730 +	if (adapter->wol & E1000_WUFC_MAG)
 12.1731 +		wol->wolopts |= WAKE_MAGIC;
 12.1732 +	if (adapter->wol & E1000_WUFC_LNKC)
 12.1733 +		wol->wolopts |= WAKE_PHY;
 12.1734 +	if (adapter->wol & E1000_WUFC_ARP)
 12.1735 +		wol->wolopts |= WAKE_ARP;
 12.1736 +	if (adapter->wol & E1000_WUFC_LNKC)
 12.1737 +		wol->wolopts |= WAKE_PHY;
 12.1738 +	if (adapter->wol & E1000_WUFC_ARP)
 12.1739 +		wol->wolopts |= WAKE_ARP;
 12.1740 +}
 12.1741 +
 12.1742 +static int e1000_set_wol(struct net_device *netdev,
 12.1743 +			 struct ethtool_wolinfo *wol)
 12.1744 +{
 12.1745 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1746 +
 12.1747 +	if (wol->wolopts & WAKE_MAGICSECURE)
 12.1748 +		return -EOPNOTSUPP;
 12.1749 +
 12.1750 +	if (!(adapter->flags & FLAG_HAS_WOL))
 12.1751 +		return wol->wolopts ? -EOPNOTSUPP : 0;
 12.1752 +
 12.1753 +	/* these settings will always override what we currently have */
 12.1754 +	adapter->wol = 0;
 12.1755 +
 12.1756 +	if (wol->wolopts & WAKE_UCAST)
 12.1757 +		adapter->wol |= E1000_WUFC_EX;
 12.1758 +	if (wol->wolopts & WAKE_MCAST)
 12.1759 +		adapter->wol |= E1000_WUFC_MC;
 12.1760 +	if (wol->wolopts & WAKE_BCAST)
 12.1761 +		adapter->wol |= E1000_WUFC_BC;
 12.1762 +	if (wol->wolopts & WAKE_MAGIC)
 12.1763 +		adapter->wol |= E1000_WUFC_MAG;
 12.1764 +	if (wol->wolopts & WAKE_PHY)
 12.1765 +		adapter->wol |= E1000_WUFC_LNKC;
 12.1766 +	if (wol->wolopts & WAKE_ARP)
 12.1767 +		adapter->wol |= E1000_WUFC_ARP;
 12.1768 +
 12.1769 +	return 0;
 12.1770 +}
 12.1771 +
 12.1772 +/* toggle LED 4 times per second = 2 "blinks" per second */
 12.1773 +#define E1000_ID_INTERVAL	(HZ/4)
 12.1774 +
 12.1775 +/* bit defines for adapter->led_status */
 12.1776 +#define E1000_LED_ON		0
 12.1777 +
 12.1778 +static void e1000_led_blink_callback(unsigned long data)
 12.1779 +{
 12.1780 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
 12.1781 +
 12.1782 +	if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
 12.1783 +		adapter->hw.mac.ops.led_off(&adapter->hw);
 12.1784 +	else
 12.1785 +		adapter->hw.mac.ops.led_on(&adapter->hw);
 12.1786 +
 12.1787 +	mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
 12.1788 +}
 12.1789 +
 12.1790 +static int e1000_phys_id(struct net_device *netdev, u32 data)
 12.1791 +{
 12.1792 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1793 +	struct e1000_hw *hw = &adapter->hw;
 12.1794 +
 12.1795 +	if (!data)
 12.1796 +		data = INT_MAX;
 12.1797 +
 12.1798 +	if ((hw->phy.type == e1000_phy_ife) ||
 12.1799 +	    (hw->mac.type == e1000_82574)) {
 12.1800 +		if (!adapter->blink_timer.function) {
 12.1801 +			init_timer(&adapter->blink_timer);
 12.1802 +			adapter->blink_timer.function =
 12.1803 +				e1000_led_blink_callback;
 12.1804 +			adapter->blink_timer.data = (unsigned long) adapter;
 12.1805 +		}
 12.1806 +		mod_timer(&adapter->blink_timer, jiffies);
 12.1807 +		msleep_interruptible(data * 1000);
 12.1808 +		del_timer_sync(&adapter->blink_timer);
 12.1809 +		if (hw->phy.type == e1000_phy_ife)
 12.1810 +			e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
 12.1811 +	} else {
 12.1812 +		e1000e_blink_led(hw);
 12.1813 +		msleep_interruptible(data * 1000);
 12.1814 +	}
 12.1815 +
 12.1816 +	hw->mac.ops.led_off(hw);
 12.1817 +	clear_bit(E1000_LED_ON, &adapter->led_status);
 12.1818 +	hw->mac.ops.cleanup_led(hw);
 12.1819 +
 12.1820 +	return 0;
 12.1821 +}
 12.1822 +
 12.1823 +static int e1000_get_coalesce(struct net_device *netdev,
 12.1824 +			      struct ethtool_coalesce *ec)
 12.1825 +{
 12.1826 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1827 +
 12.1828 +	if (adapter->itr_setting <= 3)
 12.1829 +		ec->rx_coalesce_usecs = adapter->itr_setting;
 12.1830 +	else
 12.1831 +		ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
 12.1832 +
 12.1833 +	return 0;
 12.1834 +}
 12.1835 +
 12.1836 +static int e1000_set_coalesce(struct net_device *netdev,
 12.1837 +			      struct ethtool_coalesce *ec)
 12.1838 +{
 12.1839 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1840 +	struct e1000_hw *hw = &adapter->hw;
 12.1841 +
 12.1842 +	if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) ||
 12.1843 +	    ((ec->rx_coalesce_usecs > 3) &&
 12.1844 +	     (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) ||
 12.1845 +	    (ec->rx_coalesce_usecs == 2))
 12.1846 +		return -EINVAL;
 12.1847 +
 12.1848 +	if (ec->rx_coalesce_usecs <= 3) {
 12.1849 +		adapter->itr = 20000;
 12.1850 +		adapter->itr_setting = ec->rx_coalesce_usecs;
 12.1851 +	} else {
 12.1852 +		adapter->itr = (1000000 / ec->rx_coalesce_usecs);
 12.1853 +		adapter->itr_setting = adapter->itr & ~3;
 12.1854 +	}
 12.1855 +
 12.1856 +	if (adapter->itr_setting != 0)
 12.1857 +		ew32(ITR, 1000000000 / (adapter->itr * 256));
 12.1858 +	else
 12.1859 +		ew32(ITR, 0);
 12.1860 +
 12.1861 +	return 0;
 12.1862 +}
 12.1863 +
 12.1864 +static int e1000_nway_reset(struct net_device *netdev)
 12.1865 +{
 12.1866 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1867 +	if (netif_running(netdev))
 12.1868 +		e1000e_reinit_locked(adapter);
 12.1869 +	return 0;
 12.1870 +}
 12.1871 +
 12.1872 +static int e1000_get_stats_count(struct net_device *netdev)
 12.1873 +{
 12.1874 +	return E1000_STATS_LEN;
 12.1875 +}
 12.1876 +
 12.1877 +static void e1000_get_ethtool_stats(struct net_device *netdev,
 12.1878 +				    struct ethtool_stats *stats,
 12.1879 +				    u64 *data)
 12.1880 +{
 12.1881 +	struct e1000_adapter *adapter = netdev_priv(netdev);
 12.1882 +	int i;
 12.1883 +
 12.1884 +	e1000e_update_stats(adapter);
 12.1885 +	for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
 12.1886 +		char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
 12.1887 +		data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
 12.1888 +			sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
 12.1889 +	}
 12.1890 +}
 12.1891 +
 12.1892 +static void e1000_get_strings(struct net_device *netdev, u32 stringset,
 12.1893 +			      u8 *data)
 12.1894 +{
 12.1895 +	u8 *p = data;
 12.1896 +	int i;
 12.1897 +
 12.1898 +	switch (stringset) {
 12.1899 +	case ETH_SS_TEST:
 12.1900 +		memcpy(data, *e1000_gstrings_test, E1000_TEST_LEN*ETH_GSTRING_LEN);
 12.1901 +		break;
 12.1902 +	case ETH_SS_STATS:
 12.1903 +		for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
 12.1904 +			memcpy(p, e1000_gstrings_stats[i].stat_string,
 12.1905 +			       ETH_GSTRING_LEN);
 12.1906 +			p += ETH_GSTRING_LEN;
 12.1907 +		}
 12.1908 +		break;
 12.1909 +	}
 12.1910 +}
 12.1911 +
 12.1912 +static struct ethtool_ops e1000_ethtool_ops = {
 12.1913 +	.get_settings		= e1000_get_settings,
 12.1914 +	.set_settings		= e1000_set_settings,
 12.1915 +	.get_drvinfo		= e1000_get_drvinfo,
 12.1916 +	.get_regs_len		= e1000_get_regs_len,
 12.1917 +	.get_regs		= e1000_get_regs,
 12.1918 +	.get_wol		= e1000_get_wol,
 12.1919 +	.set_wol		= e1000_set_wol,
 12.1920 +	.get_msglevel		= e1000_get_msglevel,
 12.1921 +	.set_msglevel		= e1000_set_msglevel,
 12.1922 +	.nway_reset		= e1000_nway_reset,
 12.1923 +	.get_link		= e1000_get_link,
 12.1924 +	.get_eeprom_len		= e1000_get_eeprom_len,
 12.1925 +	.get_eeprom		= e1000_get_eeprom,
 12.1926 +	.set_eeprom		= e1000_set_eeprom,
 12.1927 +	.get_ringparam		= e1000_get_ringparam,
 12.1928 +	.set_ringparam		= e1000_set_ringparam,
 12.1929 +	.get_pauseparam		= e1000_get_pauseparam,
 12.1930 +	.set_pauseparam		= e1000_set_pauseparam,
 12.1931 +	.get_rx_csum		= e1000_get_rx_csum,
 12.1932 +	.set_rx_csum		= e1000_set_rx_csum,
 12.1933 +	.get_tx_csum		= e1000_get_tx_csum,
 12.1934 +	.set_tx_csum		= e1000_set_tx_csum,
 12.1935 +	.get_sg			= ethtool_op_get_sg,
 12.1936 +	.set_sg			= ethtool_op_set_sg,
 12.1937 +	.get_tso		= ethtool_op_get_tso,
 12.1938 +	.set_tso		= e1000_set_tso,
 12.1939 +	.self_test_count	= e1000_diag_test_count,
 12.1940 +	.self_test		= e1000_diag_test,
 12.1941 +	.get_strings		= e1000_get_strings,
 12.1942 +	.phys_id		= e1000_phys_id,
 12.1943 +	.get_stats_count	= e1000_get_stats_count,
 12.1944 +	.get_ethtool_stats	= e1000_get_ethtool_stats,
 12.1945 +	.get_coalesce		= e1000_get_coalesce,
 12.1946 +	.set_coalesce		= e1000_set_coalesce,
 12.1947 +};
 12.1948 +
 12.1949 +void e1000e_set_ethtool_ops(struct net_device *netdev)
 12.1950 +{
 12.1951 +	SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
 12.1952 +}
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/drivers/net/e1000e/hw.h	Tue Feb 17 11:25:22 2009 +0000
    13.3 @@ -0,0 +1,903 @@
    13.4 +/*******************************************************************************
    13.5 +
    13.6 +  Intel PRO/1000 Linux driver
    13.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
    13.8 +
    13.9 +  This program is free software; you can redistribute it and/or modify it
   13.10 +  under the terms and conditions of the GNU General Public License,
   13.11 +  version 2, as published by the Free Software Foundation.
   13.12 +
   13.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   13.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   13.16 +  more details.
   13.17 +
   13.18 +  You should have received a copy of the GNU General Public License along with
   13.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   13.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   13.21 +
   13.22 +  The full GNU General Public License is included in this distribution in
   13.23 +  the file called "COPYING".
   13.24 +
   13.25 +  Contact Information:
   13.26 +  Linux NICS <linux.nics@intel.com>
   13.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   13.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   13.29 +
   13.30 +*******************************************************************************/
   13.31 +
   13.32 +#ifndef _E1000_HW_H_
   13.33 +#define _E1000_HW_H_
   13.34 +
   13.35 +#include <linux/types.h>
   13.36 +
   13.37 +struct e1000_hw;
   13.38 +struct e1000_adapter;
   13.39 +
   13.40 +#include "defines.h"
   13.41 +
   13.42 +#define er32(reg)	__er32(hw, E1000_##reg)
   13.43 +#define ew32(reg,val)	__ew32(hw, E1000_##reg, (val))
   13.44 +#define e1e_flush()	er32(STATUS)
   13.45 +
   13.46 +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
   13.47 +	(writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
   13.48 +
   13.49 +#define E1000_READ_REG_ARRAY(a, reg, offset) \
   13.50 +	(readl((a)->hw_addr + reg + ((offset) << 2)))
   13.51 +
   13.52 +enum e1e_registers {
   13.53 +	E1000_CTRL     = 0x00000, /* Device Control - RW */
   13.54 +	E1000_STATUS   = 0x00008, /* Device Status - RO */
   13.55 +	E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
   13.56 +	E1000_EERD     = 0x00014, /* EEPROM Read - RW */
   13.57 +	E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
   13.58 +	E1000_FLA      = 0x0001C, /* Flash Access - RW */
   13.59 +	E1000_MDIC     = 0x00020, /* MDI Control - RW */
   13.60 +	E1000_SCTL     = 0x00024, /* SerDes Control - RW */
   13.61 +	E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
   13.62 +	E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
   13.63 +	E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
   13.64 +	E1000_FCT      = 0x00030, /* Flow Control Type - RW */
   13.65 +	E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
   13.66 +	E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
   13.67 +	E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
   13.68 +	E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
   13.69 +	E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
   13.70 +	E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
   13.71 +	E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
   13.72 +	E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
   13.73 +	E1000_IVAR     = 0x000E4, /* Interrupt Vector Allocation - RW */
   13.74 +	E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
   13.75 +#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
   13.76 +	E1000_RCTL     = 0x00100, /* Rx Control - RW */
   13.77 +	E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
   13.78 +	E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
   13.79 +	E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
   13.80 +	E1000_TCTL     = 0x00400, /* Tx Control - RW */
   13.81 +	E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
   13.82 +	E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
   13.83 +	E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
   13.84 +	E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
   13.85 +	E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
   13.86 +	E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
   13.87 +	E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
   13.88 +	E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
   13.89 +	E1000_PBS      = 0x01008, /* Packet Buffer Size */
   13.90 +	E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
   13.91 +	E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
   13.92 +	E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
   13.93 +	E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
   13.94 +	E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
   13.95 +	E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
   13.96 +	E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
   13.97 +	E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
   13.98 +	E1000_RDBAL    = 0x02800, /* Rx Descriptor Base Address Low - RW */
   13.99 +	E1000_RDBAH    = 0x02804, /* Rx Descriptor Base Address High - RW */
  13.100 +	E1000_RDLEN    = 0x02808, /* Rx Descriptor Length - RW */
  13.101 +	E1000_RDH      = 0x02810, /* Rx Descriptor Head - RW */
  13.102 +	E1000_RDT      = 0x02818, /* Rx Descriptor Tail - RW */
  13.103 +	E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
  13.104 +	E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
  13.105 +#define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
  13.106 +	E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
  13.107 +
  13.108 +/* Convenience macros
  13.109 + *
  13.110 + * Note: "_n" is the queue number of the register to be written to.
  13.111 + *
  13.112 + * Example usage:
  13.113 + * E1000_RDBAL_REG(current_rx_queue)
  13.114 + *
  13.115 + */
  13.116 +#define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
  13.117 +	E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
  13.118 +	E1000_TDBAL    = 0x03800, /* Tx Descriptor Base Address Low - RW */
  13.119 +	E1000_TDBAH    = 0x03804, /* Tx Descriptor Base Address High - RW */
  13.120 +	E1000_TDLEN    = 0x03808, /* Tx Descriptor Length - RW */
  13.121 +	E1000_TDH      = 0x03810, /* Tx Descriptor Head - RW */
  13.122 +	E1000_TDT      = 0x03818, /* Tx Descriptor Tail - RW */
  13.123 +	E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
  13.124 +	E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
  13.125 +#define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
  13.126 +	E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
  13.127 +	E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
  13.128 +#define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
  13.129 +	E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
  13.130 +	E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
  13.131 +	E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
  13.132 +	E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
  13.133 +	E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
  13.134 +	E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
  13.135 +	E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
  13.136 +	E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
  13.137 +	E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
  13.138 +	E1000_COLC     = 0x04028, /* Collision Count - R/clr */
  13.139 +	E1000_DC       = 0x04030, /* Defer Count - R/clr */
  13.140 +	E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
  13.141 +	E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
  13.142 +	E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
  13.143 +	E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
  13.144 +	E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
  13.145 +	E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
  13.146 +	E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
  13.147 +	E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
  13.148 +	E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
  13.149 +	E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
  13.150 +	E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
  13.151 +	E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
  13.152 +	E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
  13.153 +	E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
  13.154 +	E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
  13.155 +	E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
  13.156 +	E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
  13.157 +	E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
  13.158 +	E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
  13.159 +	E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
  13.160 +	E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
  13.161 +	E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
  13.162 +	E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
  13.163 +	E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
  13.164 +	E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
  13.165 +	E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
  13.166 +	E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
  13.167 +	E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
  13.168 +	E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
  13.169 +	E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
  13.170 +	E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
  13.171 +	E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
  13.172 +	E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
  13.173 +	E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
  13.174 +	E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
  13.175 +	E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
  13.176 +	E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
  13.177 +	E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
  13.178 +	E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
  13.179 +	E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
  13.180 +	E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
  13.181 +	E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
  13.182 +	E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
  13.183 +	E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
  13.184 +	E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
  13.185 +	E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
  13.186 +	E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
  13.187 +	E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
  13.188 +	E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
  13.189 +	E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
  13.190 +	E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
  13.191 +	E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
  13.192 +	E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
  13.193 +	E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
  13.194 +	E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
  13.195 +	E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
  13.196 +	E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
  13.197 +	E1000_RFCTL    = 0x05008, /* Receive Filter Control */
  13.198 +	E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
  13.199 +	E1000_RA       = 0x05400, /* Receive Address - RW Array */
  13.200 +	E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
  13.201 +	E1000_WUC      = 0x05800, /* Wakeup Control - RW */
  13.202 +	E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
  13.203 +	E1000_WUS      = 0x05810, /* Wakeup Status - RO */
  13.204 +	E1000_MANC     = 0x05820, /* Management Control - RW */
  13.205 +	E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
  13.206 +	E1000_HOST_IF  = 0x08800, /* Host Interface */
  13.207 +
  13.208 +	E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
  13.209 +	E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
  13.210 +	E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
  13.211 +	E1000_GCR	= 0x05B00, /* PCI-Ex Control */
  13.212 +	E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
  13.213 +	E1000_SWSM      = 0x05B50, /* SW Semaphore */
  13.214 +	E1000_FWSM      = 0x05B54, /* FW Semaphore */
  13.215 +	E1000_HICR      = 0x08F00, /* Host Interface Control */
  13.216 +};
  13.217 +
  13.218 +/* RSS registers */
  13.219 +
  13.220 +/* IGP01E1000 Specific Registers */
  13.221 +#define IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
  13.222 +#define IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
  13.223 +#define IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
  13.224 +#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
  13.225 +#define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
  13.226 +#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
  13.227 +#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
  13.228 +#define IGP_PAGE_SHIFT			5
  13.229 +#define PHY_REG_MASK			0x1F
  13.230 +
  13.231 +#define BM_WUC_PAGE			800
  13.232 +#define BM_WUC_ADDRESS_OPCODE		0x11
  13.233 +#define BM_WUC_DATA_OPCODE		0x12
  13.234 +#define BM_WUC_ENABLE_PAGE		769
  13.235 +#define BM_WUC_ENABLE_REG		17
  13.236 +#define BM_WUC_ENABLE_BIT		(1 << 2)
  13.237 +#define BM_WUC_HOST_WU_BIT		(1 << 4)
  13.238 +
  13.239 +#define BM_WUC	PHY_REG(BM_WUC_PAGE, 1)
  13.240 +#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
  13.241 +#define BM_WUS	PHY_REG(BM_WUC_PAGE, 3)
  13.242 +
  13.243 +#define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
  13.244 +#define IGP01E1000_PHY_POLARITY_MASK	0x0078
  13.245 +
  13.246 +#define IGP01E1000_PSCR_AUTO_MDIX	0x1000
  13.247 +#define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
  13.248 +
  13.249 +#define IGP01E1000_PSCFR_SMART_SPEED	0x0080
  13.250 +
  13.251 +#define IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
  13.252 +#define IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
  13.253 +#define IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
  13.254 +
  13.255 +#define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
  13.256 +
  13.257 +#define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
  13.258 +#define IGP01E1000_PSSR_MDIX			0x0008
  13.259 +#define IGP01E1000_PSSR_SPEED_MASK		0xC000
  13.260 +#define IGP01E1000_PSSR_SPEED_1000MBPS		0xC000
  13.261 +
  13.262 +#define IGP02E1000_PHY_CHANNEL_NUM		4
  13.263 +#define IGP02E1000_PHY_AGC_A			0x11B1
  13.264 +#define IGP02E1000_PHY_AGC_B			0x12B1
  13.265 +#define IGP02E1000_PHY_AGC_C			0x14B1
  13.266 +#define IGP02E1000_PHY_AGC_D			0x18B1
  13.267 +
  13.268 +#define IGP02E1000_AGC_LENGTH_SHIFT	9 /* Course - 15:13, Fine - 12:9 */
  13.269 +#define IGP02E1000_AGC_LENGTH_MASK	0x7F
  13.270 +#define IGP02E1000_AGC_RANGE		15
  13.271 +
  13.272 +/* manage.c */
  13.273 +#define E1000_VFTA_ENTRY_SHIFT		5
  13.274 +#define E1000_VFTA_ENTRY_MASK		0x7F
  13.275 +#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK	0x1F
  13.276 +
  13.277 +#define E1000_HICR_EN			0x01  /* Enable bit - RO */
  13.278 +/* Driver sets this bit when done to put command in RAM */
  13.279 +#define E1000_HICR_C			0x02
  13.280 +#define E1000_HICR_FW_RESET_ENABLE	0x40
  13.281 +#define E1000_HICR_FW_RESET		0x80
  13.282 +
  13.283 +#define E1000_FWSM_MODE_MASK		0xE
  13.284 +#define E1000_FWSM_MODE_SHIFT		1
  13.285 +
  13.286 +#define E1000_MNG_IAMT_MODE		0x3
  13.287 +#define E1000_MNG_DHCP_COOKIE_LENGTH	0x10
  13.288 +#define E1000_MNG_DHCP_COOKIE_OFFSET	0x6F0
  13.289 +#define E1000_MNG_DHCP_COMMAND_TIMEOUT	10
  13.290 +#define E1000_MNG_DHCP_TX_PAYLOAD_CMD	64
  13.291 +#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
  13.292 +#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
  13.293 +
  13.294 +/* nvm.c */
  13.295 +#define E1000_STM_OPCODE  0xDB00
  13.296 +
  13.297 +#define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
  13.298 +#define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
  13.299 +#define E1000_KMRNCTRLSTA_REN		0x00200000
  13.300 +#define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
  13.301 +#define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
  13.302 +
  13.303 +#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
  13.304 +#define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
  13.305 +#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
  13.306 +#define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
  13.307 +
  13.308 +/* IFE PHY Extended Status Control */
  13.309 +#define IFE_PESC_POLARITY_REVERSED	0x0100
  13.310 +
  13.311 +/* IFE PHY Special Control */
  13.312 +#define IFE_PSC_AUTO_POLARITY_DISABLE		0x0010
  13.313 +#define IFE_PSC_FORCE_POLARITY			0x0020
  13.314 +
  13.315 +/* IFE PHY Special Control and LED Control */
  13.316 +#define IFE_PSCL_PROBE_MODE		0x0020
  13.317 +#define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
  13.318 +#define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
  13.319 +
  13.320 +/* IFE PHY MDIX Control */
  13.321 +#define IFE_PMC_MDIX_STATUS	0x0020 /* 1=MDI-X, 0=MDI */
  13.322 +#define IFE_PMC_FORCE_MDIX	0x0040 /* 1=force MDI-X, 0=force MDI */
  13.323 +#define IFE_PMC_AUTO_MDIX	0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
  13.324 +
  13.325 +#define E1000_CABLE_LENGTH_UNDEFINED	0xFF
  13.326 +
  13.327 +#define E1000_DEV_ID_82571EB_COPPER		0x105E
  13.328 +#define E1000_DEV_ID_82571EB_FIBER		0x105F
  13.329 +#define E1000_DEV_ID_82571EB_SERDES		0x1060
  13.330 +#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
  13.331 +#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
  13.332 +#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
  13.333 +#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
  13.334 +#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
  13.335 +#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
  13.336 +#define E1000_DEV_ID_82572EI_COPPER		0x107D
  13.337 +#define E1000_DEV_ID_82572EI_FIBER		0x107E
  13.338 +#define E1000_DEV_ID_82572EI_SERDES		0x107F
  13.339 +#define E1000_DEV_ID_82572EI			0x10B9
  13.340 +#define E1000_DEV_ID_82573E			0x108B
  13.341 +#define E1000_DEV_ID_82573E_IAMT		0x108C
  13.342 +#define E1000_DEV_ID_82573L			0x109A
  13.343 +#define E1000_DEV_ID_82574L			0x10D3
  13.344 +
  13.345 +#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
  13.346 +#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
  13.347 +#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
  13.348 +#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
  13.349 +
  13.350 +#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
  13.351 +#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
  13.352 +#define E1000_DEV_ID_ICH8_IGP_C			0x104B
  13.353 +#define E1000_DEV_ID_ICH8_IFE			0x104C
  13.354 +#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
  13.355 +#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
  13.356 +#define E1000_DEV_ID_ICH8_IGP_M			0x104D
  13.357 +#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
  13.358 +#define E1000_DEV_ID_ICH9_BM			0x10E5
  13.359 +#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
  13.360 +#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
  13.361 +#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
  13.362 +#define E1000_DEV_ID_ICH9_IGP_C			0x294C
  13.363 +#define E1000_DEV_ID_ICH9_IFE			0x10C0
  13.364 +#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
  13.365 +#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
  13.366 +#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
  13.367 +#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
  13.368 +#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
  13.369 +#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
  13.370 +#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
  13.371 +
  13.372 +#define E1000_REVISION_4 4
  13.373 +
  13.374 +#define E1000_FUNC_1 1
  13.375 +
  13.376 +enum e1000_mac_type {
  13.377 +	e1000_82571,
  13.378 +	e1000_82572,
  13.379 +	e1000_82573,
  13.380 +	e1000_82574,
  13.381 +	e1000_80003es2lan,
  13.382 +	e1000_ich8lan,
  13.383 +	e1000_ich9lan,
  13.384 +	e1000_ich10lan,
  13.385 +};
  13.386 +
  13.387 +enum e1000_media_type {
  13.388 +	e1000_media_type_unknown = 0,
  13.389 +	e1000_media_type_copper = 1,
  13.390 +	e1000_media_type_fiber = 2,
  13.391 +	e1000_media_type_internal_serdes = 3,
  13.392 +	e1000_num_media_types
  13.393 +};
  13.394 +
  13.395 +enum e1000_nvm_type {
  13.396 +	e1000_nvm_unknown = 0,
  13.397 +	e1000_nvm_none,
  13.398 +	e1000_nvm_eeprom_spi,
  13.399 +	e1000_nvm_flash_hw,
  13.400 +	e1000_nvm_flash_sw
  13.401 +};
  13.402 +
  13.403 +enum e1000_nvm_override {
  13.404 +	e1000_nvm_override_none = 0,
  13.405 +	e1000_nvm_override_spi_small,
  13.406 +	e1000_nvm_override_spi_large
  13.407 +};
  13.408 +
  13.409 +enum e1000_phy_type {
  13.410 +	e1000_phy_unknown = 0,
  13.411 +	e1000_phy_none,
  13.412 +	e1000_phy_m88,
  13.413 +	e1000_phy_igp,
  13.414 +	e1000_phy_igp_2,
  13.415 +	e1000_phy_gg82563,
  13.416 +	e1000_phy_igp_3,
  13.417 +	e1000_phy_ife,
  13.418 +	e1000_phy_bm,
  13.419 +};
  13.420 +
  13.421 +enum e1000_bus_width {
  13.422 +	e1000_bus_width_unknown = 0,
  13.423 +	e1000_bus_width_pcie_x1,
  13.424 +	e1000_bus_width_pcie_x2,
  13.425 +	e1000_bus_width_pcie_x4 = 4,
  13.426 +	e1000_bus_width_32,
  13.427 +	e1000_bus_width_64,
  13.428 +	e1000_bus_width_reserved
  13.429 +};
  13.430 +
  13.431 +enum e1000_1000t_rx_status {
  13.432 +	e1000_1000t_rx_status_not_ok = 0,
  13.433 +	e1000_1000t_rx_status_ok,
  13.434 +	e1000_1000t_rx_status_undefined = 0xFF
  13.435 +};
  13.436 +
  13.437 +enum e1000_rev_polarity{
  13.438 +	e1000_rev_polarity_normal = 0,
  13.439 +	e1000_rev_polarity_reversed,
  13.440 +	e1000_rev_polarity_undefined = 0xFF
  13.441 +};
  13.442 +
  13.443 +enum e1000_fc_type {
  13.444 +	e1000_fc_none = 0,
  13.445 +	e1000_fc_rx_pause,
  13.446 +	e1000_fc_tx_pause,
  13.447 +	e1000_fc_full,
  13.448 +	e1000_fc_default = 0xFF
  13.449 +};
  13.450 +
  13.451 +enum e1000_ms_type {
  13.452 +	e1000_ms_hw_default = 0,
  13.453 +	e1000_ms_force_master,
  13.454 +	e1000_ms_force_slave,
  13.455 +	e1000_ms_auto
  13.456 +};
  13.457 +
  13.458 +enum e1000_smart_speed {
  13.459 +	e1000_smart_speed_default = 0,
  13.460 +	e1000_smart_speed_on,
  13.461 +	e1000_smart_speed_off
  13.462 +};
  13.463 +
  13.464 +/* Receive Descriptor */
  13.465 +struct e1000_rx_desc {
  13.466 +	__le64 buffer_addr; /* Address of the descriptor's data buffer */
  13.467 +	__le16 length;      /* Length of data DMAed into data buffer */
  13.468 +	__le16 csum;	/* Packet checksum */
  13.469 +	u8  status;      /* Descriptor status */
  13.470 +	u8  errors;      /* Descriptor Errors */
  13.471 +	__le16 special;
  13.472 +};
  13.473 +
  13.474 +/* Receive Descriptor - Extended */
  13.475 +union e1000_rx_desc_extended {
  13.476 +	struct {
  13.477 +		__le64 buffer_addr;
  13.478 +		__le64 reserved;
  13.479 +	} read;
  13.480 +	struct {
  13.481 +		struct {
  13.482 +			__le32 mrq;	      /* Multiple Rx Queues */
  13.483 +			union {
  13.484 +				__le32 rss;	    /* RSS Hash */
  13.485 +				struct {
  13.486 +					__le16 ip_id;  /* IP id */
  13.487 +					__le16 csum;   /* Packet Checksum */
  13.488 +				} csum_ip;
  13.489 +			} hi_dword;
  13.490 +		} lower;
  13.491 +		struct {
  13.492 +			__le32 status_error;     /* ext status/error */
  13.493 +			__le16 length;
  13.494 +			__le16 vlan;	     /* VLAN tag */
  13.495 +		} upper;
  13.496 +	} wb;  /* writeback */
  13.497 +};
  13.498 +
  13.499 +#define MAX_PS_BUFFERS 4
  13.500 +/* Receive Descriptor - Packet Split */
  13.501 +union e1000_rx_desc_packet_split {
  13.502 +	struct {
  13.503 +		/* one buffer for protocol header(s), three data buffers */
  13.504 +		__le64 buffer_addr[MAX_PS_BUFFERS];
  13.505 +	} read;
  13.506 +	struct {
  13.507 +		struct {
  13.508 +			__le32 mrq;	      /* Multiple Rx Queues */
  13.509 +			union {
  13.510 +				__le32 rss;	      /* RSS Hash */
  13.511 +				struct {
  13.512 +					__le16 ip_id;    /* IP id */
  13.513 +					__le16 csum;     /* Packet Checksum */
  13.514 +				} csum_ip;
  13.515 +			} hi_dword;
  13.516 +		} lower;
  13.517 +		struct {
  13.518 +			__le32 status_error;     /* ext status/error */
  13.519 +			__le16 length0;	  /* length of buffer 0 */
  13.520 +			__le16 vlan;	     /* VLAN tag */
  13.521 +		} middle;
  13.522 +		struct {
  13.523 +			__le16 header_status;
  13.524 +			__le16 length[3];	/* length of buffers 1-3 */
  13.525 +		} upper;
  13.526 +		__le64 reserved;
  13.527 +	} wb; /* writeback */
  13.528 +};
  13.529 +
  13.530 +/* Transmit Descriptor */
  13.531 +struct e1000_tx_desc {
  13.532 +	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
  13.533 +	union {
  13.534 +		__le32 data;
  13.535 +		struct {
  13.536 +			__le16 length;    /* Data buffer length */
  13.537 +			u8 cso;	/* Checksum offset */
  13.538 +			u8 cmd;	/* Descriptor control */
  13.539 +		} flags;
  13.540 +	} lower;
  13.541 +	union {
  13.542 +		__le32 data;
  13.543 +		struct {
  13.544 +			u8 status;     /* Descriptor status */
  13.545 +			u8 css;	/* Checksum start */
  13.546 +			__le16 special;
  13.547 +		} fields;
  13.548 +	} upper;
  13.549 +};
  13.550 +
  13.551 +/* Offload Context Descriptor */
  13.552 +struct e1000_context_desc {
  13.553 +	union {
  13.554 +		__le32 ip_config;
  13.555 +		struct {
  13.556 +			u8 ipcss;      /* IP checksum start */
  13.557 +			u8 ipcso;      /* IP checksum offset */
  13.558 +			__le16 ipcse;     /* IP checksum end */
  13.559 +		} ip_fields;
  13.560 +	} lower_setup;
  13.561 +	union {
  13.562 +		__le32 tcp_config;
  13.563 +		struct {
  13.564 +			u8 tucss;      /* TCP checksum start */
  13.565 +			u8 tucso;      /* TCP checksum offset */
  13.566 +			__le16 tucse;     /* TCP checksum end */
  13.567 +		} tcp_fields;
  13.568 +	} upper_setup;
  13.569 +	__le32 cmd_and_length;
  13.570 +	union {
  13.571 +		__le32 data;
  13.572 +		struct {
  13.573 +			u8 status;     /* Descriptor status */
  13.574 +			u8 hdr_len;    /* Header length */
  13.575 +			__le16 mss;       /* Maximum segment size */
  13.576 +		} fields;
  13.577 +	} tcp_seg_setup;
  13.578 +};
  13.579 +
  13.580 +/* Offload data descriptor */
  13.581 +struct e1000_data_desc {
  13.582 +	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
  13.583 +	union {
  13.584 +		__le32 data;
  13.585 +		struct {
  13.586 +			__le16 length;    /* Data buffer length */
  13.587 +			u8 typ_len_ext;
  13.588 +			u8 cmd;
  13.589 +		} flags;
  13.590 +	} lower;
  13.591 +	union {
  13.592 +		__le32 data;
  13.593 +		struct {
  13.594 +			u8 status;     /* Descriptor status */
  13.595 +			u8 popts;      /* Packet Options */
  13.596 +			__le16 special;   /* */
  13.597 +		} fields;
  13.598 +	} upper;
  13.599 +};
  13.600 +
  13.601 +/* Statistics counters collected by the MAC */
  13.602 +struct e1000_hw_stats {
  13.603 +	u64 crcerrs;
  13.604 +	u64 algnerrc;
  13.605 +	u64 symerrs;
  13.606 +	u64 rxerrc;
  13.607 +	u64 mpc;
  13.608 +	u64 scc;
  13.609 +	u64 ecol;
  13.610 +	u64 mcc;
  13.611 +	u64 latecol;
  13.612 +	u64 colc;
  13.613 +	u64 dc;
  13.614 +	u64 tncrs;
  13.615 +	u64 sec;
  13.616 +	u64 cexterr;
  13.617 +	u64 rlec;
  13.618 +	u64 xonrxc;
  13.619 +	u64 xontxc;
  13.620 +	u64 xoffrxc;
  13.621 +	u64 xofftxc;
  13.622 +	u64 fcruc;
  13.623 +	u64 prc64;
  13.624 +	u64 prc127;
  13.625 +	u64 prc255;
  13.626 +	u64 prc511;
  13.627 +	u64 prc1023;
  13.628 +	u64 prc1522;
  13.629 +	u64 gprc;
  13.630 +	u64 bprc;
  13.631 +	u64 mprc;
  13.632 +	u64 gptc;
  13.633 +	u64 gorc;
  13.634 +	u64 gotc;
  13.635 +	u64 rnbc;
  13.636 +	u64 ruc;
  13.637 +	u64 rfc;
  13.638 +	u64 roc;
  13.639 +	u64 rjc;
  13.640 +	u64 mgprc;
  13.641 +	u64 mgpdc;
  13.642 +	u64 mgptc;
  13.643 +	u64 tor;
  13.644 +	u64 tot;
  13.645 +	u64 tpr;
  13.646 +	u64 tpt;
  13.647 +	u64 ptc64;
  13.648 +	u64 ptc127;
  13.649 +	u64 ptc255;
  13.650 +	u64 ptc511;
  13.651 +	u64 ptc1023;
  13.652 +	u64 ptc1522;
  13.653 +	u64 mptc;
  13.654 +	u64 bptc;
  13.655 +	u64 tsctc;
  13.656 +	u64 tsctfc;
  13.657 +	u64 iac;
  13.658 +	u64 icrxptc;
  13.659 +	u64 icrxatc;
  13.660 +	u64 ictxptc;
  13.661 +	u64 ictxatc;
  13.662 +	u64 ictxqec;
  13.663 +	u64 ictxqmtc;
  13.664 +	u64 icrxdmtc;
  13.665 +	u64 icrxoc;
  13.666 +};
  13.667 +
  13.668 +struct e1000_phy_stats {
  13.669 +	u32 idle_errors;
  13.670 +	u32 receive_errors;
  13.671 +};
  13.672 +
  13.673 +struct e1000_host_mng_dhcp_cookie {
  13.674 +	u32 signature;
  13.675 +	u8  status;
  13.676 +	u8  reserved0;
  13.677 +	u16 vlan_id;
  13.678 +	u32 reserved1;
  13.679 +	u16 reserved2;
  13.680 +	u8  reserved3;
  13.681 +	u8  checksum;
  13.682 +};
  13.683 +
  13.684 +/* Host Interface "Rev 1" */
  13.685 +struct e1000_host_command_header {
  13.686 +	u8 command_id;
  13.687 +	u8 command_length;
  13.688 +	u8 command_options;
  13.689 +	u8 checksum;
  13.690 +};
  13.691 +
  13.692 +#define E1000_HI_MAX_DATA_LENGTH     252
  13.693 +struct e1000_host_command_info {
  13.694 +	struct e1000_host_command_header command_header;
  13.695 +	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
  13.696 +};
  13.697 +
  13.698 +/* Host Interface "Rev 2" */
  13.699 +struct e1000_host_mng_command_header {
  13.700 +	u8  command_id;
  13.701 +	u8  checksum;
  13.702 +	u16 reserved1;
  13.703 +	u16 reserved2;
  13.704 +	u16 command_length;
  13.705 +};
  13.706 +
  13.707 +#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
  13.708 +struct e1000_host_mng_command_info {
  13.709 +	struct e1000_host_mng_command_header command_header;
  13.710 +	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
  13.711 +};
  13.712 +
  13.713 +/* Function pointers and static data for the MAC. */
  13.714 +struct e1000_mac_operations {
  13.715 +	bool (*check_mng_mode)(struct e1000_hw *);
  13.716 +	s32  (*check_for_link)(struct e1000_hw *);
  13.717 +	s32  (*cleanup_led)(struct e1000_hw *);
  13.718 +	void (*clear_hw_cntrs)(struct e1000_hw *);
  13.719 +	s32  (*get_bus_info)(struct e1000_hw *);
  13.720 +	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
  13.721 +	s32  (*led_on)(struct e1000_hw *);
  13.722 +	s32  (*led_off)(struct e1000_hw *);
  13.723 +	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
  13.724 +	s32  (*reset_hw)(struct e1000_hw *);
  13.725 +	s32  (*init_hw)(struct e1000_hw *);
  13.726 +	s32  (*setup_link)(struct e1000_hw *);
  13.727 +	s32  (*setup_physical_interface)(struct e1000_hw *);
  13.728 +};
  13.729 +
  13.730 +/* Function pointers for the PHY. */
  13.731 +struct e1000_phy_operations {
  13.732 +	s32  (*acquire_phy)(struct e1000_hw *);
  13.733 +	s32  (*check_reset_block)(struct e1000_hw *);
  13.734 +	s32  (*commit_phy)(struct e1000_hw *);
  13.735 +	s32  (*force_speed_duplex)(struct e1000_hw *);
  13.736 +	s32  (*get_cfg_done)(struct e1000_hw *hw);
  13.737 +	s32  (*get_cable_length)(struct e1000_hw *);
  13.738 +	s32  (*get_phy_info)(struct e1000_hw *);
  13.739 +	s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
  13.740 +	void (*release_phy)(struct e1000_hw *);
  13.741 +	s32  (*reset_phy)(struct e1000_hw *);
  13.742 +	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
  13.743 +	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
  13.744 +	s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
  13.745 +};
  13.746 +
  13.747 +/* Function pointers for the NVM. */
  13.748 +struct e1000_nvm_operations {
  13.749 +	s32  (*acquire_nvm)(struct e1000_hw *);
  13.750 +	s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
  13.751 +	void (*release_nvm)(struct e1000_hw *);
  13.752 +	s32  (*update_nvm)(struct e1000_hw *);
  13.753 +	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
  13.754 +	s32  (*validate_nvm)(struct e1000_hw *);
  13.755 +	s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
  13.756 +};
  13.757 +
  13.758 +struct e1000_mac_info {
  13.759 +	struct e1000_mac_operations ops;
  13.760 +
  13.761 +	u8 addr[6];
  13.762 +	u8 perm_addr[6];
  13.763 +
  13.764 +	enum e1000_mac_type type;
  13.765 +
  13.766 +	u32 collision_delta;
  13.767 +	u32 ledctl_default;
  13.768 +	u32 ledctl_mode1;
  13.769 +	u32 ledctl_mode2;
  13.770 +	u32 mc_filter_type;
  13.771 +	u32 tx_packet_delta;
  13.772 +	u32 txcw;
  13.773 +
  13.774 +	u16 current_ifs_val;
  13.775 +	u16 ifs_max_val;
  13.776 +	u16 ifs_min_val;
  13.777 +	u16 ifs_ratio;
  13.778 +	u16 ifs_step_size;
  13.779 +	u16 mta_reg_count;
  13.780 +	u16 rar_entry_count;
  13.781 +
  13.782 +	u8  forced_speed_duplex;
  13.783 +
  13.784 +	bool arc_subsystem_valid;
  13.785 +	bool autoneg;
  13.786 +	bool autoneg_failed;
  13.787 +	bool get_link_status;
  13.788 +	bool in_ifs_mode;
  13.789 +	bool serdes_has_link;
  13.790 +	bool tx_pkt_filtering;
  13.791 +};
  13.792 +
  13.793 +struct e1000_phy_info {
  13.794 +	struct e1000_phy_operations ops;
  13.795 +
  13.796 +	enum e1000_phy_type type;
  13.797 +
  13.798 +	enum e1000_1000t_rx_status local_rx;
  13.799 +	enum e1000_1000t_rx_status remote_rx;
  13.800 +	enum e1000_ms_type ms_type;
  13.801 +	enum e1000_ms_type original_ms_type;
  13.802 +	enum e1000_rev_polarity cable_polarity;
  13.803 +	enum e1000_smart_speed smart_speed;
  13.804 +
  13.805 +	u32 addr;
  13.806 +	u32 id;
  13.807 +	u32 reset_delay_us; /* in usec */
  13.808 +	u32 revision;
  13.809 +
  13.810 +	enum e1000_media_type media_type;
  13.811 +
  13.812 +	u16 autoneg_advertised;
  13.813 +	u16 autoneg_mask;
  13.814 +	u16 cable_length;
  13.815 +	u16 max_cable_length;
  13.816 +	u16 min_cable_length;
  13.817 +
  13.818 +	u8 mdix;
  13.819 +
  13.820 +	bool disable_polarity_correction;
  13.821 +	bool is_mdix;
  13.822 +	bool polarity_correction;
  13.823 +	bool speed_downgraded;
  13.824 +	bool autoneg_wait_to_complete;
  13.825 +};
  13.826 +
  13.827 +struct e1000_nvm_info {
  13.828 +	struct e1000_nvm_operations ops;
  13.829 +
  13.830 +	enum e1000_nvm_type type;
  13.831 +	enum e1000_nvm_override override;
  13.832 +
  13.833 +	u32 flash_bank_size;
  13.834 +	u32 flash_base_addr;
  13.835 +
  13.836 +	u16 word_size;
  13.837 +	u16 delay_usec;
  13.838 +	u16 address_bits;
  13.839 +	u16 opcode_bits;
  13.840 +	u16 page_size;
  13.841 +};
  13.842 +
  13.843 +struct e1000_bus_info {
  13.844 +	enum e1000_bus_width width;
  13.845 +
  13.846 +	u16 func;
  13.847 +};
  13.848 +
  13.849 +struct e1000_fc_info {
  13.850 +	u32 high_water;          /* Flow control high-water mark */
  13.851 +	u32 low_water;           /* Flow control low-water mark */
  13.852 +	u16 pause_time;          /* Flow control pause timer */
  13.853 +	bool send_xon;           /* Flow control send XON */
  13.854 +	bool strict_ieee;        /* Strict IEEE mode */
  13.855 +	enum e1000_fc_type type; /* Type of flow control */
  13.856 +	enum e1000_fc_type original_type;
  13.857 +};
  13.858 +
  13.859 +struct e1000_dev_spec_82571 {
  13.860 +	bool laa_is_present;
  13.861 +	bool alt_mac_addr_is_present;
  13.862 +};
  13.863 +
  13.864 +struct e1000_shadow_ram {
  13.865 +	u16  value;
  13.866 +	bool modified;
  13.867 +};
  13.868 +
  13.869 +#define E1000_ICH8_SHADOW_RAM_WORDS		2048
  13.870 +
  13.871 +struct e1000_dev_spec_ich8lan {
  13.872 +	bool kmrn_lock_loss_workaround_enabled;
  13.873 +	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
  13.874 +};
  13.875 +
  13.876 +struct e1000_hw {
  13.877 +	struct e1000_adapter *adapter;
  13.878 +
  13.879 +	u8 __iomem *hw_addr;
  13.880 +	u8 __iomem *flash_address;
  13.881 +
  13.882 +	struct e1000_mac_info  mac;
  13.883 +	struct e1000_fc_info   fc;
  13.884 +	struct e1000_phy_info  phy;
  13.885 +	struct e1000_nvm_info  nvm;
  13.886 +	struct e1000_bus_info  bus;
  13.887 +	struct e1000_host_mng_dhcp_cookie mng_cookie;
  13.888 +
  13.889 +	union {
  13.890 +		struct e1000_dev_spec_82571	e82571;
  13.891 +		struct e1000_dev_spec_ich8lan	ich8lan;
  13.892 +	} dev_spec;
  13.893 +};
  13.894 +
  13.895 +#ifdef DEBUG
  13.896 +#define hw_dbg(hw, format, arg...) \
  13.897 +	printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
  13.898 +#else
  13.899 +static inline int __attribute__ ((format (printf, 2, 3)))
  13.900 +hw_dbg(struct e1000_hw *hw, const char *format, ...)
  13.901 +{
  13.902 +	return 0;
  13.903 +}
  13.904 +#endif
  13.905 +
  13.906 +#endif
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/drivers/net/e1000e/ich8lan.c	Tue Feb 17 11:25:22 2009 +0000
    14.3 @@ -0,0 +1,2568 @@
    14.4 +/*******************************************************************************
    14.5 +
    14.6 +  Intel PRO/1000 Linux driver
    14.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
    14.8 +
    14.9 +  This program is free software; you can redistribute it and/or modify it
   14.10 +  under the terms and conditions of the GNU General Public License,
   14.11 +  version 2, as published by the Free Software Foundation.
   14.12 +
   14.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   14.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   14.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   14.16 +  more details.
   14.17 +
   14.18 +  You should have received a copy of the GNU General Public License along with
   14.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   14.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   14.21 +
   14.22 +  The full GNU General Public License is included in this distribution in
   14.23 +  the file called "COPYING".
   14.24 +
   14.25 +  Contact Information:
   14.26 +  Linux NICS <linux.nics@intel.com>
   14.27 +  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   14.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   14.29 +
   14.30 +*******************************************************************************/
   14.31 +
   14.32 +/*
   14.33 + * 82562G-2 10/100 Network Connection
   14.34 + * 82562GT 10/100 Network Connection
   14.35 + * 82562GT-2 10/100 Network Connection
   14.36 + * 82562V 10/100 Network Connection
   14.37 + * 82562V-2 10/100 Network Connection
   14.38 + * 82566DC-2 Gigabit Network Connection
   14.39 + * 82566DC Gigabit Network Connection
   14.40 + * 82566DM-2 Gigabit Network Connection
   14.41 + * 82566DM Gigabit Network Connection
   14.42 + * 82566MC Gigabit Network Connection
   14.43 + * 82566MM Gigabit Network Connection
   14.44 + * 82567LM Gigabit Network Connection
   14.45 + * 82567LF Gigabit Network Connection
   14.46 + * 82567LM-2 Gigabit Network Connection
   14.47 + * 82567LF-2 Gigabit Network Connection
   14.48 + * 82567V-2 Gigabit Network Connection
   14.49 + * 82567LF-3 Gigabit Network Connection
   14.50 + * 82567LM-3 Gigabit Network Connection
   14.51 + * 82567LM-4 Gigabit Network Connection
   14.52 + */
   14.53 +
   14.54 +#include <linux/netdevice.h>
   14.55 +#include <linux/ethtool.h>
   14.56 +#include <linux/delay.h>
   14.57 +#include <linux/pci.h>
   14.58 +
   14.59 +#include "e1000.h"
   14.60 +
   14.61 +#define ICH_FLASH_GFPREG		0x0000
   14.62 +#define ICH_FLASH_HSFSTS		0x0004
   14.63 +#define ICH_FLASH_HSFCTL		0x0006
   14.64 +#define ICH_FLASH_FADDR			0x0008
   14.65 +#define ICH_FLASH_FDATA0		0x0010
   14.66 +#define ICH_FLASH_PR0			0x0074
   14.67 +
   14.68 +#define ICH_FLASH_READ_COMMAND_TIMEOUT	500
   14.69 +#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500
   14.70 +#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000
   14.71 +#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
   14.72 +#define ICH_FLASH_CYCLE_REPEAT_COUNT	10
   14.73 +
   14.74 +#define ICH_CYCLE_READ			0
   14.75 +#define ICH_CYCLE_WRITE			2
   14.76 +#define ICH_CYCLE_ERASE			3
   14.77 +
   14.78 +#define FLASH_GFPREG_BASE_MASK		0x1FFF
   14.79 +#define FLASH_SECTOR_ADDR_SHIFT		12
   14.80 +
   14.81 +#define ICH_FLASH_SEG_SIZE_256		256
   14.82 +#define ICH_FLASH_SEG_SIZE_4K		4096
   14.83 +#define ICH_FLASH_SEG_SIZE_8K		8192
   14.84 +#define ICH_FLASH_SEG_SIZE_64K		65536
   14.85 +
   14.86 +
   14.87 +#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */
   14.88 +
   14.89 +#define E1000_ICH_MNG_IAMT_MODE		0x2
   14.90 +
   14.91 +#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
   14.92 +				 (ID_LED_DEF1_OFF2 <<  8) | \
   14.93 +				 (ID_LED_DEF1_ON2  <<  4) | \
   14.94 +				 (ID_LED_DEF1_DEF2))
   14.95 +
   14.96 +#define E1000_ICH_NVM_SIG_WORD		0x13
   14.97 +#define E1000_ICH_NVM_SIG_MASK		0xC000
   14.98 +
   14.99 +#define E1000_ICH8_LAN_INIT_TIMEOUT	1500
  14.100 +
  14.101 +#define E1000_FEXTNVM_SW_CONFIG		1
  14.102 +#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
  14.103 +
  14.104 +#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL
  14.105 +
  14.106 +#define E1000_ICH_RAR_ENTRIES		7
  14.107 +
  14.108 +#define PHY_PAGE_SHIFT 5
  14.109 +#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
  14.110 +			   ((reg) & MAX_PHY_REG_ADDRESS))
  14.111 +#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
  14.112 +#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
  14.113 +
  14.114 +#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002
  14.115 +#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
  14.116 +#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200
  14.117 +
  14.118 +/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  14.119 +/* Offset 04h HSFSTS */
  14.120 +union ich8_hws_flash_status {
  14.121 +	struct ich8_hsfsts {
  14.122 +		u16 flcdone    :1; /* bit 0 Flash Cycle Done */
  14.123 +		u16 flcerr     :1; /* bit 1 Flash Cycle Error */
  14.124 +		u16 dael       :1; /* bit 2 Direct Access error Log */
  14.125 +		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
  14.126 +		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
  14.127 +		u16 reserved1  :2; /* bit 13:6 Reserved */
  14.128 +		u16 reserved2  :6; /* bit 13:6 Reserved */
  14.129 +		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
  14.130 +		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
  14.131 +	} hsf_status;
  14.132 +	u16 regval;
  14.133 +};
  14.134 +
  14.135 +/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  14.136 +/* Offset 06h FLCTL */
  14.137 +union ich8_hws_flash_ctrl {
  14.138 +	struct ich8_hsflctl {
  14.139 +		u16 flcgo      :1;   /* 0 Flash Cycle Go */
  14.140 +		u16 flcycle    :2;   /* 2:1 Flash Cycle */
  14.141 +		u16 reserved   :5;   /* 7:3 Reserved  */
  14.142 +		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
  14.143 +		u16 flockdn    :6;   /* 15:10 Reserved */
  14.144 +	} hsf_ctrl;
  14.145 +	u16 regval;
  14.146 +};
  14.147 +
  14.148 +/* ICH Flash Region Access Permissions */
  14.149 +union ich8_hws_flash_regacc {
  14.150 +	struct ich8_flracc {
  14.151 +		u32 grra      :8; /* 0:7 GbE region Read Access */
  14.152 +		u32 grwa      :8; /* 8:15 GbE region Write Access */
  14.153 +		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
  14.154 +		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
  14.155 +	} hsf_flregacc;
  14.156 +	u16 regval;
  14.157 +};
  14.158 +
  14.159 +/* ICH Flash Protected Region */
  14.160 +union ich8_flash_protected_range {
  14.161 +	struct ich8_pr {
  14.162 +		u32 base:13;     /* 0:12 Protected Range Base */
  14.163 +		u32 reserved1:2; /* 13:14 Reserved */
  14.164 +		u32 rpe:1;       /* 15 Read Protection Enable */
  14.165 +		u32 limit:13;    /* 16:28 Protected Range Limit */
  14.166 +		u32 reserved2:2; /* 29:30 Reserved */
  14.167 +		u32 wpe:1;       /* 31 Write Protection Enable */
  14.168 +	} range;
  14.169 +	u32 regval;
  14.170 +};
  14.171 +
  14.172 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
  14.173 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  14.174 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  14.175 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
  14.176 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  14.177 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
  14.178 +						u32 offset, u8 byte);
  14.179 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
  14.180 +					 u8 *data);
  14.181 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
  14.182 +					 u16 *data);
  14.183 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
  14.184 +					 u8 size, u16 *data);
  14.185 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  14.186 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
  14.187 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
  14.188 +
  14.189 +static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
  14.190 +{
  14.191 +	return readw(hw->flash_address + reg);
  14.192 +}
  14.193 +
  14.194 +static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
  14.195 +{
  14.196 +	return readl(hw->flash_address + reg);
  14.197 +}
  14.198 +
  14.199 +static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
  14.200 +{
  14.201 +	writew(val, hw->flash_address + reg);
  14.202 +}
  14.203 +
  14.204 +static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
  14.205 +{
  14.206 +	writel(val, hw->flash_address + reg);
  14.207 +}
  14.208 +
  14.209 +#define er16flash(reg)		__er16flash(hw, (reg))
  14.210 +#define er32flash(reg)		__er32flash(hw, (reg))
  14.211 +#define ew16flash(reg,val)	__ew16flash(hw, (reg), (val))
  14.212 +#define ew32flash(reg,val)	__ew32flash(hw, (reg), (val))
  14.213 +
  14.214 +/**
  14.215 + *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
  14.216 + *  @hw: pointer to the HW structure
  14.217 + *
  14.218 + *  Initialize family-specific PHY parameters and function pointers.
  14.219 + **/
  14.220 +static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
  14.221 +{
  14.222 +	struct e1000_phy_info *phy = &hw->phy;
  14.223 +	s32 ret_val;
  14.224 +	u16 i = 0;
  14.225 +
  14.226 +	phy->addr			= 1;
  14.227 +	phy->reset_delay_us		= 100;
  14.228 +
  14.229 +	/*
  14.230 +	 * We may need to do this twice - once for IGP and if that fails,
  14.231 +	 * we'll set BM func pointers and try again
  14.232 +	 */
  14.233 +	ret_val = e1000e_determine_phy_address(hw);
  14.234 +	if (ret_val) {
  14.235 +		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
  14.236 +		hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
  14.237 +		ret_val = e1000e_determine_phy_address(hw);
  14.238 +		if (ret_val)
  14.239 +			return ret_val;
  14.240 +	}
  14.241 +
  14.242 +	phy->id = 0;
  14.243 +	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
  14.244 +	       (i++ < 100)) {
  14.245 +		msleep(1);
  14.246 +		ret_val = e1000e_get_phy_id(hw);
  14.247 +		if (ret_val)
  14.248 +			return ret_val;
  14.249 +	}
  14.250 +
  14.251 +	/* Verify phy id */
  14.252 +	switch (phy->id) {
  14.253 +	case IGP03E1000_E_PHY_ID:
  14.254 +		phy->type = e1000_phy_igp_3;
  14.255 +		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  14.256 +		break;
  14.257 +	case IFE_E_PHY_ID:
  14.258 +	case IFE_PLUS_E_PHY_ID:
  14.259 +	case IFE_C_E_PHY_ID:
  14.260 +		phy->type = e1000_phy_ife;
  14.261 +		phy->autoneg_mask = E1000_ALL_NOT_GIG;
  14.262 +		break;
  14.263 +	case BME1000_E_PHY_ID:
  14.264 +		phy->type = e1000_phy_bm;
  14.265 +		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  14.266 +		hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
  14.267 +		hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
  14.268 +		hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
  14.269 +		break;
  14.270 +	default:
  14.271 +		return -E1000_ERR_PHY;
  14.272 +		break;
  14.273 +	}
  14.274 +
  14.275 +	return 0;
  14.276 +}
  14.277 +
  14.278 +/**
  14.279 + *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
  14.280 + *  @hw: pointer to the HW structure
  14.281 + *
  14.282 + *  Initialize family-specific NVM parameters and function
  14.283 + *  pointers.
  14.284 + **/
  14.285 +static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
  14.286 +{
  14.287 +	struct e1000_nvm_info *nvm = &hw->nvm;
  14.288 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
  14.289 +	u32 gfpreg;
  14.290 +	u32 sector_base_addr;
  14.291 +	u32 sector_end_addr;
  14.292 +	u16 i;
  14.293 +
  14.294 +	/* Can't read flash registers if the register set isn't mapped. */
  14.295 +	if (!hw->flash_address) {
  14.296 +		hw_dbg(hw, "ERROR: Flash registers not mapped\n");
  14.297 +		return -E1000_ERR_CONFIG;
  14.298 +	}
  14.299 +
  14.300 +	nvm->type = e1000_nvm_flash_sw;
  14.301 +
  14.302 +	gfpreg = er32flash(ICH_FLASH_GFPREG);
  14.303 +
  14.304 +	/*
  14.305 +	 * sector_X_addr is a "sector"-aligned address (4096 bytes)
  14.306 +	 * Add 1 to sector_end_addr since this sector is included in
  14.307 +	 * the overall size.
  14.308 +	 */
  14.309 +	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
  14.310 +	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
  14.311 +
  14.312 +	/* flash_base_addr is byte-aligned */
  14.313 +	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
  14.314 +
  14.315 +	/*
  14.316 +	 * find total size of the NVM, then cut in half since the total
  14.317 +	 * size represents two separate NVM banks.
  14.318 +	 */
  14.319 +	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
  14.320 +				<< FLASH_SECTOR_ADDR_SHIFT;
  14.321 +	nvm->flash_bank_size /= 2;
  14.322 +	/* Adjust to word count */
  14.323 +	nvm->flash_bank_size /= sizeof(u16);
  14.324 +
  14.325 +	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
  14.326 +
  14.327 +	/* Clear shadow ram */
  14.328 +	for (i = 0; i < nvm->word_size; i++) {
  14.329 +		dev_spec->shadow_ram[i].modified = 0;
  14.330 +		dev_spec->shadow_ram[i].value    = 0xFFFF;
  14.331 +	}
  14.332 +
  14.333 +	return 0;
  14.334 +}
  14.335 +
  14.336 +/**
  14.337 + *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
  14.338 + *  @hw: pointer to the HW structure
  14.339 + *
  14.340 + *  Initialize family-specific MAC parameters and function
  14.341 + *  pointers.
  14.342 + **/
  14.343 +static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
  14.344 +{
  14.345 +	struct e1000_hw *hw = &adapter->hw;
  14.346 +	struct e1000_mac_info *mac = &hw->mac;
  14.347 +
  14.348 +	/* Set media type function pointer */
  14.349 +	hw->phy.media_type = e1000_media_type_copper;
  14.350 +
  14.351 +	/* Set mta register count */
  14.352 +	mac->mta_reg_count = 32;
  14.353 +	/* Set rar entry count */
  14.354 +	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
  14.355 +	if (mac->type == e1000_ich8lan)
  14.356 +		mac->rar_entry_count--;
  14.357 +	/* Set if manageability features are enabled. */
  14.358 +	mac->arc_subsystem_valid = 1;
  14.359 +
  14.360 +	/* Enable PCS Lock-loss workaround for ICH8 */
  14.361 +	if (mac->type == e1000_ich8lan)
  14.362 +		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
  14.363 +
  14.364 +	return 0;
  14.365 +}
  14.366 +
  14.367 +static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
  14.368 +{
  14.369 +	struct e1000_hw *hw = &adapter->hw;
  14.370 +	s32 rc;
  14.371 +
  14.372 +	rc = e1000_init_mac_params_ich8lan(adapter);
  14.373 +	if (rc)
  14.374 +		return rc;
  14.375 +
  14.376 +	rc = e1000_init_nvm_params_ich8lan(hw);
  14.377 +	if (rc)
  14.378 +		return rc;
  14.379 +
  14.380 +	rc = e1000_init_phy_params_ich8lan(hw);
  14.381 +	if (rc)
  14.382 +		return rc;
  14.383 +
  14.384 +	if ((adapter->hw.mac.type == e1000_ich8lan) &&
  14.385 +	    (adapter->hw.phy.type == e1000_phy_igp_3))
  14.386 +		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
  14.387 +
  14.388 +	return 0;
  14.389 +}
  14.390 +
  14.391 +/**
  14.392 + *  e1000_acquire_swflag_ich8lan - Acquire software control flag
  14.393 + *  @hw: pointer to the HW structure
  14.394 + *
  14.395 + *  Acquires the software control flag for performing NVM and PHY
  14.396 + *  operations.  This is a function pointer entry point only called by
  14.397 + *  read/write routines for the PHY and NVM parts.
  14.398 + **/
  14.399 +static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
  14.400 +{
  14.401 +	u32 extcnf_ctrl;
  14.402 +	u32 timeout = PHY_CFG_TIMEOUT;
  14.403 +
  14.404 +	while (timeout) {
  14.405 +		extcnf_ctrl = er32(EXTCNF_CTRL);
  14.406 +		extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
  14.407 +		ew32(EXTCNF_CTRL, extcnf_ctrl);
  14.408 +
  14.409 +		extcnf_ctrl = er32(EXTCNF_CTRL);
  14.410 +		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
  14.411 +			break;
  14.412 +		mdelay(1);
  14.413 +		timeout--;
  14.414 +	}
  14.415 +
  14.416 +	if (!timeout) {
  14.417 +		hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
  14.418 +		return -E1000_ERR_CONFIG;
  14.419 +	}
  14.420 +
  14.421 +	return 0;
  14.422 +}
  14.423 +
  14.424 +/**
  14.425 + *  e1000_release_swflag_ich8lan - Release software control flag
  14.426 + *  @hw: pointer to the HW structure
  14.427 + *
  14.428 + *  Releases the software control flag for performing NVM and PHY operations.
  14.429 + *  This is a function pointer entry point only called by read/write
  14.430 + *  routines for the PHY and NVM parts.
  14.431 + **/
  14.432 +static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
  14.433 +{
  14.434 +	u32 extcnf_ctrl;
  14.435 +
  14.436 +	extcnf_ctrl = er32(EXTCNF_CTRL);
  14.437 +	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
  14.438 +	ew32(EXTCNF_CTRL, extcnf_ctrl);
  14.439 +}
  14.440 +
  14.441 +/**
  14.442 + *  e1000_check_mng_mode_ich8lan - Checks management mode
  14.443 + *  @hw: pointer to the HW structure
  14.444 + *
  14.445 + *  This checks if the adapter has manageability enabled.
  14.446 + *  This is a function pointer entry point only called by read/write
  14.447 + *  routines for the PHY and NVM parts.
  14.448 + **/
  14.449 +static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
  14.450 +{
  14.451 +	u32 fwsm = er32(FWSM);
  14.452 +
  14.453 +	return (fwsm & E1000_FWSM_MODE_MASK) ==
  14.454 +		(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
  14.455 +}
  14.456 +
  14.457 +/**
  14.458 + *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
  14.459 + *  @hw: pointer to the HW structure
  14.460 + *
  14.461 + *  Checks if firmware is blocking the reset of the PHY.
  14.462 + *  This is a function pointer entry point only called by
  14.463 + *  reset routines.
  14.464 + **/
  14.465 +static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
  14.466 +{
  14.467 +	u32 fwsm;
  14.468 +
  14.469 +	fwsm = er32(FWSM);
  14.470 +
  14.471 +	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
  14.472 +}
  14.473 +
  14.474 +/**
  14.475 + *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
  14.476 + *  @hw: pointer to the HW structure
  14.477 + *
  14.478 + *  Forces the speed and duplex settings of the PHY.
  14.479 + *  This is a function pointer entry point only called by
  14.480 + *  PHY setup routines.
  14.481 + **/
  14.482 +static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
  14.483 +{
  14.484 +	struct e1000_phy_info *phy = &hw->phy;
  14.485 +	s32 ret_val;
  14.486 +	u16 data;
  14.487 +	bool link;
  14.488 +
  14.489 +	if (phy->type != e1000_phy_ife) {
  14.490 +		ret_val = e1000e_phy_force_speed_duplex_igp(hw);
  14.491 +		return ret_val;
  14.492 +	}
  14.493 +
  14.494 +	ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
  14.495 +	if (ret_val)
  14.496 +		return ret_val;
  14.497 +
  14.498 +	e1000e_phy_force_speed_duplex_setup(hw, &data);
  14.499 +
  14.500 +	ret_val = e1e_wphy(hw, PHY_CONTROL, data);
  14.501 +	if (ret_val)
  14.502 +		return ret_val;
  14.503 +
  14.504 +	/* Disable MDI-X support for 10/100 */
  14.505 +	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
  14.506 +	if (ret_val)
  14.507 +		return ret_val;
  14.508 +
  14.509 +	data &= ~IFE_PMC_AUTO_MDIX;
  14.510 +	data &= ~IFE_PMC_FORCE_MDIX;
  14.511 +
  14.512 +	ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
  14.513 +	if (ret_val)
  14.514 +		return ret_val;
  14.515 +
  14.516 +	hw_dbg(hw, "IFE PMC: %X\n", data);
  14.517 +
  14.518 +	udelay(1);
  14.519 +
  14.520 +	if (phy->autoneg_wait_to_complete) {
  14.521 +		hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
  14.522 +
  14.523 +		ret_val = e1000e_phy_has_link_generic(hw,
  14.524 +						     PHY_FORCE_LIMIT,
  14.525 +						     100000,
  14.526 +						     &link);
  14.527 +		if (ret_val)
  14.528 +			return ret_val;
  14.529 +
  14.530 +		if (!link)
  14.531 +			hw_dbg(hw, "Link taking longer than expected.\n");
  14.532 +
  14.533 +		/* Try once more */
  14.534 +		ret_val = e1000e_phy_has_link_generic(hw,
  14.535 +						     PHY_FORCE_LIMIT,
  14.536 +						     100000,
  14.537 +						     &link);
  14.538 +		if (ret_val)
  14.539 +			return ret_val;
  14.540 +	}
  14.541 +
  14.542 +	return 0;
  14.543 +}
  14.544 +
  14.545 +/**
  14.546 + *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
  14.547 + *  @hw: pointer to the HW structure
  14.548 + *
  14.549 + *  Resets the PHY
  14.550 + *  This is a function pointer entry point called by drivers
  14.551 + *  or other shared routines.
  14.552 + **/
  14.553 +static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
  14.554 +{
  14.555 +	struct e1000_phy_info *phy = &hw->phy;
  14.556 +	u32 i;
  14.557 +	u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
  14.558 +	s32 ret_val;
  14.559 +	u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
  14.560 +	u16 word_addr, reg_data, reg_addr, phy_page = 0;
  14.561 +
  14.562 +	ret_val = e1000e_phy_hw_reset_generic(hw);
  14.563 +	if (ret_val)
  14.564 +		return ret_val;
  14.565 +
  14.566 +	/*
  14.567 +	 * Initialize the PHY from the NVM on ICH platforms.  This
  14.568 +	 * is needed due to an issue where the NVM configuration is
  14.569 +	 * not properly autoloaded after power transitions.
  14.570 +	 * Therefore, after each PHY reset, we will load the
  14.571 +	 * configuration data out of the NVM manually.
  14.572 +	 */
  14.573 +	if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
  14.574 +		struct e1000_adapter *adapter = hw->adapter;
  14.575 +
  14.576 +		/* Check if SW needs configure the PHY */
  14.577 +		if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
  14.578 +		    (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
  14.579 +			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
  14.580 +		else
  14.581 +			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
  14.582 +
  14.583 +		data = er32(FEXTNVM);
  14.584 +		if (!(data & sw_cfg_mask))
  14.585 +			return 0;
  14.586 +
  14.587 +		/* Wait for basic configuration completes before proceeding*/
  14.588 +		do {
  14.589 +			data = er32(STATUS);
  14.590 +			data &= E1000_STATUS_LAN_INIT_DONE;
  14.591 +			udelay(100);
  14.592 +		} while ((!data) && --loop);
  14.593 +
  14.594 +		/*
  14.595 +		 * If basic configuration is incomplete before the above loop
  14.596 +		 * count reaches 0, loading the configuration from NVM will
  14.597 +		 * leave the PHY in a bad state possibly resulting in no link.
  14.598 +		 */
  14.599 +		if (loop == 0) {
  14.600 +			hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
  14.601 +		}
  14.602 +
  14.603 +		/* Clear the Init Done bit for the next init event */
  14.604 +		data = er32(STATUS);
  14.605 +		data &= ~E1000_STATUS_LAN_INIT_DONE;
  14.606 +		ew32(STATUS, data);
  14.607 +
  14.608 +		/*
  14.609 +		 * Make sure HW does not configure LCD from PHY
  14.610 +		 * extended configuration before SW configuration
  14.611 +		 */
  14.612 +		data = er32(EXTCNF_CTRL);
  14.613 +		if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
  14.614 +			return 0;
  14.615 +
  14.616 +		cnf_size = er32(EXTCNF_SIZE);
  14.617 +		cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
  14.618 +		cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
  14.619 +		if (!cnf_size)
  14.620 +			return 0;
  14.621 +
  14.622 +		cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
  14.623 +		cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
  14.624 +
  14.625 +		/* Configure LCD from extended configuration region. */
  14.626 +
  14.627 +		/* cnf_base_addr is in DWORD */
  14.628 +		word_addr = (u16)(cnf_base_addr << 1);
  14.629 +
  14.630 +		for (i = 0; i < cnf_size; i++) {
  14.631 +			ret_val = e1000_read_nvm(hw,
  14.632 +						(word_addr + i * 2),
  14.633 +						1,
  14.634 +						&reg_data);
  14.635 +			if (ret_val)
  14.636 +				return ret_val;
  14.637 +
  14.638 +			ret_val = e1000_read_nvm(hw,
  14.639 +						(word_addr + i * 2 + 1),
  14.640 +						1,
  14.641 +						&reg_addr);
  14.642 +			if (ret_val)
  14.643 +				return ret_val;
  14.644 +
  14.645 +			/* Save off the PHY page for future writes. */
  14.646 +			if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
  14.647 +				phy_page = reg_data;
  14.648 +				continue;
  14.649 +			}
  14.650 +
  14.651 +			reg_addr |= phy_page;
  14.652 +
  14.653 +			ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
  14.654 +			if (ret_val)
  14.655 +				return ret_val;
  14.656 +		}
  14.657 +	}
  14.658 +
  14.659 +	return 0;
  14.660 +}
  14.661 +
  14.662 +/**
  14.663 + *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
  14.664 + *  @hw: pointer to the HW structure
  14.665 + *
  14.666 + *  Populates "phy" structure with various feature states.
  14.667 + *  This function is only called by other family-specific
  14.668 + *  routines.
  14.669 + **/
  14.670 +static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
  14.671 +{
  14.672 +	struct e1000_phy_info *phy = &hw->phy;
  14.673 +	s32 ret_val;
  14.674 +	u16 data;
  14.675 +	bool link;
  14.676 +
  14.677 +	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
  14.678 +	if (ret_val)
  14.679 +		return ret_val;
  14.680 +
  14.681 +	if (!link) {
  14.682 +		hw_dbg(hw, "Phy info is only valid if link is up\n");
  14.683 +		return -E1000_ERR_CONFIG;
  14.684 +	}
  14.685 +
  14.686 +	ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
  14.687 +	if (ret_val)
  14.688 +		return ret_val;
  14.689 +	phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
  14.690 +
  14.691 +	if (phy->polarity_correction) {
  14.692 +		ret_val = e1000_check_polarity_ife_ich8lan(hw);
  14.693 +		if (ret_val)
  14.694 +			return ret_val;
  14.695 +	} else {
  14.696 +		/* Polarity is forced */
  14.697 +		phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
  14.698 +				      ? e1000_rev_polarity_reversed
  14.699 +				      : e1000_rev_polarity_normal;
  14.700 +	}
  14.701 +
  14.702 +	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
  14.703 +	if (ret_val)
  14.704 +		return ret_val;
  14.705 +
  14.706 +	phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
  14.707 +
  14.708 +	/* The following parameters are undefined for 10/100 operation. */
  14.709 +	phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
  14.710 +	phy->local_rx = e1000_1000t_rx_status_undefined;
  14.711 +	phy->remote_rx = e1000_1000t_rx_status_undefined;
  14.712 +
  14.713 +	return 0;
  14.714 +}
  14.715 +
  14.716 +/**
  14.717 + *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
  14.718 + *  @hw: pointer to the HW structure
  14.719 + *
  14.720 + *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
  14.721 + *  This is a function pointer entry point called by drivers
  14.722 + *  or other shared routines.
  14.723 + **/
  14.724 +static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
  14.725 +{
  14.726 +	switch (hw->phy.type) {
  14.727 +	case e1000_phy_ife:
  14.728 +		return e1000_get_phy_info_ife_ich8lan(hw);
  14.729 +		break;
  14.730 +	case e1000_phy_igp_3:
  14.731 +	case e1000_phy_bm:
  14.732 +		return e1000e_get_phy_info_igp(hw);
  14.733 +		break;
  14.734 +	default:
  14.735 +		break;
  14.736 +	}
  14.737 +
  14.738 +	return -E1000_ERR_PHY_TYPE;
  14.739 +}
  14.740 +
  14.741 +/**
  14.742 + *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
  14.743 + *  @hw: pointer to the HW structure
  14.744 + *
  14.745 + *  Polarity is determined on the polarity reversal feature being enabled.
  14.746 + *  This function is only called by other family-specific
  14.747 + *  routines.
  14.748 + **/
  14.749 +static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
  14.750 +{
  14.751 +	struct e1000_phy_info *phy = &hw->phy;
  14.752 +	s32 ret_val;
  14.753 +	u16 phy_data, offset, mask;
  14.754 +
  14.755 +	/*
  14.756 +	 * Polarity is determined based on the reversal feature being enabled.
  14.757 +	 */
  14.758 +	if (phy->polarity_correction) {
  14.759 +		offset	= IFE_PHY_EXTENDED_STATUS_CONTROL;
  14.760 +		mask	= IFE_PESC_POLARITY_REVERSED;
  14.761 +	} else {
  14.762 +		offset	= IFE_PHY_SPECIAL_CONTROL;
  14.763 +		mask	= IFE_PSC_FORCE_POLARITY;
  14.764 +	}
  14.765 +
  14.766 +	ret_val = e1e_rphy(hw, offset, &phy_data);
  14.767 +
  14.768 +	if (!ret_val)
  14.769 +		phy->cable_polarity = (phy_data & mask)
  14.770 +				      ? e1000_rev_polarity_reversed
  14.771 +				      : e1000_rev_polarity_normal;
  14.772 +
  14.773 +	return ret_val;
  14.774 +}
  14.775 +
  14.776 +/**
  14.777 + *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
  14.778 + *  @hw: pointer to the HW structure
  14.779 + *  @active: TRUE to enable LPLU, FALSE to disable
  14.780 + *
  14.781 + *  Sets the LPLU D0 state according to the active flag.  When
  14.782 + *  activating LPLU this function also disables smart speed
  14.783 + *  and vice versa.  LPLU will not be activated unless the
  14.784 + *  device autonegotiation advertisement meets standards of
  14.785 + *  either 10 or 10/100 or 10/100/1000 at all duplexes.
  14.786 + *  This is a function pointer entry point only called by
  14.787 + *  PHY setup routines.
  14.788 + **/
  14.789 +static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
  14.790 +{
  14.791 +	struct e1000_phy_info *phy = &hw->phy;
  14.792 +	u32 phy_ctrl;
  14.793 +	s32 ret_val = 0;
  14.794 +	u16 data;
  14.795 +
  14.796 +	if (phy->type == e1000_phy_ife)
  14.797 +		return ret_val;
  14.798 +
  14.799 +	phy_ctrl = er32(PHY_CTRL);
  14.800 +
  14.801 +	if (active) {
  14.802 +		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  14.803 +		ew32(PHY_CTRL, phy_ctrl);
  14.804 +
  14.805 +		/*
  14.806 +		 * Call gig speed drop workaround on LPLU before accessing
  14.807 +		 * any PHY registers
  14.808 +		 */
  14.809 +		if ((hw->mac.type == e1000_ich8lan) &&
  14.810 +		    (hw->phy.type == e1000_phy_igp_3))
  14.811 +			e1000e_gig_downshift_workaround_ich8lan(hw);
  14.812 +
  14.813 +		/* When LPLU is enabled, we should disable SmartSpeed */
  14.814 +		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
  14.815 +		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  14.816 +		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
  14.817 +		if (ret_val)
  14.818 +			return ret_val;
  14.819 +	} else {
  14.820 +		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  14.821 +		ew32(PHY_CTRL, phy_ctrl);
  14.822 +
  14.823 +		/*
  14.824 +		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
  14.825 +		 * during Dx states where the power conservation is most
  14.826 +		 * important.  During driver activity we should enable
  14.827 +		 * SmartSpeed, so performance is maintained.
  14.828 +		 */
  14.829 +		if (phy->smart_speed == e1000_smart_speed_on) {
  14.830 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.831 +					   &data);
  14.832 +			if (ret_val)
  14.833 +				return ret_val;
  14.834 +
  14.835 +			data |= IGP01E1000_PSCFR_SMART_SPEED;
  14.836 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.837 +					   data);
  14.838 +			if (ret_val)
  14.839 +				return ret_val;
  14.840 +		} else if (phy->smart_speed == e1000_smart_speed_off) {
  14.841 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.842 +					   &data);
  14.843 +			if (ret_val)
  14.844 +				return ret_val;
  14.845 +
  14.846 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  14.847 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.848 +					   data);
  14.849 +			if (ret_val)
  14.850 +				return ret_val;
  14.851 +		}
  14.852 +	}
  14.853 +
  14.854 +	return 0;
  14.855 +}
  14.856 +
  14.857 +/**
  14.858 + *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
  14.859 + *  @hw: pointer to the HW structure
  14.860 + *  @active: TRUE to enable LPLU, FALSE to disable
  14.861 + *
  14.862 + *  Sets the LPLU D3 state according to the active flag.  When
  14.863 + *  activating LPLU this function also disables smart speed
  14.864 + *  and vice versa.  LPLU will not be activated unless the
  14.865 + *  device autonegotiation advertisement meets standards of
  14.866 + *  either 10 or 10/100 or 10/100/1000 at all duplexes.
  14.867 + *  This is a function pointer entry point only called by
  14.868 + *  PHY setup routines.
  14.869 + **/
  14.870 +static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
  14.871 +{
  14.872 +	struct e1000_phy_info *phy = &hw->phy;
  14.873 +	u32 phy_ctrl;
  14.874 +	s32 ret_val;
  14.875 +	u16 data;
  14.876 +
  14.877 +	phy_ctrl = er32(PHY_CTRL);
  14.878 +
  14.879 +	if (!active) {
  14.880 +		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  14.881 +		ew32(PHY_CTRL, phy_ctrl);
  14.882 +		/*
  14.883 +		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
  14.884 +		 * during Dx states where the power conservation is most
  14.885 +		 * important.  During driver activity we should enable
  14.886 +		 * SmartSpeed, so performance is maintained.
  14.887 +		 */
  14.888 +		if (phy->smart_speed == e1000_smart_speed_on) {
  14.889 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.890 +					   &data);
  14.891 +			if (ret_val)
  14.892 +				return ret_val;
  14.893 +
  14.894 +			data |= IGP01E1000_PSCFR_SMART_SPEED;
  14.895 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.896 +					   data);
  14.897 +			if (ret_val)
  14.898 +				return ret_val;
  14.899 +		} else if (phy->smart_speed == e1000_smart_speed_off) {
  14.900 +			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.901 +					   &data);
  14.902 +			if (ret_val)
  14.903 +				return ret_val;
  14.904 +
  14.905 +			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  14.906 +			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
  14.907 +					   data);
  14.908 +			if (ret_val)
  14.909 +				return ret_val;
  14.910 +		}
  14.911 +	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
  14.912 +		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
  14.913 +		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
  14.914 +		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  14.915 +		ew32(PHY_CTRL, phy_ctrl);
  14.916 +
  14.917 +		/*
  14.918 +		 * Call gig speed drop workaround on LPLU before accessing
  14.919 +		 * any PHY registers
  14.920 +		 */
  14.921 +		if ((hw->mac.type == e1000_ich8lan) &&
  14.922 +		    (hw->phy.type == e1000_phy_igp_3))
  14.923 +			e1000e_gig_downshift_workaround_ich8lan(hw);
  14.924 +
  14.925 +		/* When LPLU is enabled, we should disable SmartSpeed */
  14.926 +		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
  14.927 +		if (ret_val)
  14.928 +			return ret_val;
  14.929 +
  14.930 +		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  14.931 +		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
  14.932 +	}
  14.933 +
  14.934 +	return 0;
  14.935 +}
  14.936 +
  14.937 +/**
  14.938 + *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
  14.939 + *  @hw: pointer to the HW structure
  14.940 + *  @bank:  pointer to the variable that returns the active bank
  14.941 + *
  14.942 + *  Reads signature byte from the NVM using the flash access registers.
  14.943 + **/
  14.944 +static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
  14.945 +{
  14.946 +	struct e1000_nvm_info *nvm = &hw->nvm;
  14.947 +	/* flash bank size is in words */
  14.948 +	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
  14.949 +	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
  14.950 +	u8 bank_high_byte = 0;
  14.951 +
  14.952 +	if (hw->mac.type != e1000_ich10lan) {
  14.953 +		if (er32(EECD) & E1000_EECD_SEC1VAL)
  14.954 +			*bank = 1;
  14.955 +		else
  14.956 +			*bank = 0;
  14.957 +	} else {
  14.958 +		/*
  14.959 +		 * Make sure the signature for bank 0 is valid,
  14.960 +		 * if not check for bank1
  14.961 +		 */
  14.962 +		e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
  14.963 +		if ((bank_high_byte & 0xC0) == 0x80) {
  14.964 +			*bank = 0;
  14.965 +		} else {
  14.966 +			/*
  14.967 +			 * find if segment 1 is valid by verifying
  14.968 +			 * bit 15:14 = 10b in word 0x13
  14.969 +			 */
  14.970 +			e1000_read_flash_byte_ich8lan(hw,
  14.971 +						      act_offset + bank1_offset,
  14.972 +						      &bank_high_byte);
  14.973 +
  14.974 +			/* bank1 has a valid signature equivalent to SEC1V */
  14.975 +			if ((bank_high_byte & 0xC0) == 0x80) {
  14.976 +				*bank = 1;
  14.977 +			} else {
  14.978 +				hw_dbg(hw, "ERROR: EEPROM not present\n");
  14.979 +				return -E1000_ERR_NVM;
  14.980 +			}
  14.981 +		}
  14.982 +	}
  14.983 +
  14.984 +	return 0;
  14.985 +}
  14.986 +
  14.987 +/**
  14.988 + *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
  14.989 + *  @hw: pointer to the HW structure
  14.990 + *  @offset: The offset (in bytes) of the word(s) to read.
  14.991 + *  @words: Size of data to read in words
  14.992 + *  @data: Pointer to the word(s) to read at offset.
  14.993 + *
  14.994 + *  Reads a word(s) from the NVM using the flash access registers.
  14.995 + **/
  14.996 +static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
  14.997 +				  u16 *data)
  14.998 +{
  14.999 +	struct e1000_nvm_info *nvm = &hw->nvm;
 14.1000 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 14.1001 +	u32 act_offset;
 14.1002 +	s32 ret_val;
 14.1003 +	u32 bank = 0;
 14.1004 +	u16 i, word;
 14.1005 +
 14.1006 +	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 14.1007 +	    (words == 0)) {
 14.1008 +		hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 14.1009 +		return -E1000_ERR_NVM;
 14.1010 +	}
 14.1011 +
 14.1012 +	ret_val = e1000_acquire_swflag_ich8lan(hw);
 14.1013 +	if (ret_val)
 14.1014 +		return ret_val;
 14.1015 +
 14.1016 +	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 14.1017 +	if (ret_val)
 14.1018 +		return ret_val;
 14.1019 +
 14.1020 +	act_offset = (bank) ? nvm->flash_bank_size : 0;
 14.1021 +	act_offset += offset;
 14.1022 +
 14.1023 +	for (i = 0; i < words; i++) {
 14.1024 +		if ((dev_spec->shadow_ram) &&
 14.1025 +		    (dev_spec->shadow_ram[offset+i].modified)) {
 14.1026 +			data[i] = dev_spec->shadow_ram[offset+i].value;
 14.1027 +		} else {
 14.1028 +			ret_val = e1000_read_flash_word_ich8lan(hw,
 14.1029 +								act_offset + i,
 14.1030 +								&word);
 14.1031 +			if (ret_val)
 14.1032 +				break;
 14.1033 +			data[i] = word;
 14.1034 +		}
 14.1035 +	}
 14.1036 +
 14.1037 +	e1000_release_swflag_ich8lan(hw);
 14.1038 +
 14.1039 +	return ret_val;
 14.1040 +}
 14.1041 +
 14.1042 +/**
 14.1043 + *  e1000_flash_cycle_init_ich8lan - Initialize flash
 14.1044 + *  @hw: pointer to the HW structure
 14.1045 + *
 14.1046 + *  This function does initial flash setup so that a new read/write/erase cycle
 14.1047 + *  can be started.
 14.1048 + **/
 14.1049 +static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 14.1050 +{
 14.1051 +	union ich8_hws_flash_status hsfsts;
 14.1052 +	s32 ret_val = -E1000_ERR_NVM;
 14.1053 +	s32 i = 0;
 14.1054 +
 14.1055 +	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1056 +
 14.1057 +	/* Check if the flash descriptor is valid */
 14.1058 +	if (hsfsts.hsf_status.fldesvalid == 0) {
 14.1059 +		hw_dbg(hw, "Flash descriptor invalid.  "
 14.1060 +			 "SW Sequencing must be used.");
 14.1061 +		return -E1000_ERR_NVM;
 14.1062 +	}
 14.1063 +
 14.1064 +	/* Clear FCERR and DAEL in hw status by writing 1 */
 14.1065 +	hsfsts.hsf_status.flcerr = 1;
 14.1066 +	hsfsts.hsf_status.dael = 1;
 14.1067 +
 14.1068 +	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 14.1069 +
 14.1070 +	/*
 14.1071 +	 * Either we should have a hardware SPI cycle in progress
 14.1072 +	 * bit to check against, in order to start a new cycle or
 14.1073 +	 * FDONE bit should be changed in the hardware so that it
 14.1074 +	 * is 1 after hardware reset, which can then be used as an
 14.1075 +	 * indication whether a cycle is in progress or has been
 14.1076 +	 * completed.
 14.1077 +	 */
 14.1078 +
 14.1079 +	if (hsfsts.hsf_status.flcinprog == 0) {
 14.1080 +		/*
 14.1081 +		 * There is no cycle running at present,
 14.1082 +		 * so we can start a cycle
 14.1083 +		 * Begin by setting Flash Cycle Done.
 14.1084 +		 */
 14.1085 +		hsfsts.hsf_status.flcdone = 1;
 14.1086 +		ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 14.1087 +		ret_val = 0;
 14.1088 +	} else {
 14.1089 +		/*
 14.1090 +		 * otherwise poll for sometime so the current
 14.1091 +		 * cycle has a chance to end before giving up.
 14.1092 +		 */
 14.1093 +		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
 14.1094 +			hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
 14.1095 +			if (hsfsts.hsf_status.flcinprog == 0) {
 14.1096 +				ret_val = 0;
 14.1097 +				break;
 14.1098 +			}
 14.1099 +			udelay(1);
 14.1100 +		}
 14.1101 +		if (ret_val == 0) {
 14.1102 +			/*
 14.1103 +			 * Successful in waiting for previous cycle to timeout,
 14.1104 +			 * now set the Flash Cycle Done.
 14.1105 +			 */
 14.1106 +			hsfsts.hsf_status.flcdone = 1;
 14.1107 +			ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 14.1108 +		} else {
 14.1109 +			hw_dbg(hw, "Flash controller busy, cannot get access");
 14.1110 +		}
 14.1111 +	}
 14.1112 +
 14.1113 +	return ret_val;
 14.1114 +}
 14.1115 +
 14.1116 +/**
 14.1117 + *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
 14.1118 + *  @hw: pointer to the HW structure
 14.1119 + *  @timeout: maximum time to wait for completion
 14.1120 + *
 14.1121 + *  This function starts a flash cycle and waits for its completion.
 14.1122 + **/
 14.1123 +static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
 14.1124 +{
 14.1125 +	union ich8_hws_flash_ctrl hsflctl;
 14.1126 +	union ich8_hws_flash_status hsfsts;
 14.1127 +	s32 ret_val = -E1000_ERR_NVM;
 14.1128 +	u32 i = 0;
 14.1129 +
 14.1130 +	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
 14.1131 +	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
 14.1132 +	hsflctl.hsf_ctrl.flcgo = 1;
 14.1133 +	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
 14.1134 +
 14.1135 +	/* wait till FDONE bit is set to 1 */
 14.1136 +	do {
 14.1137 +		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1138 +		if (hsfsts.hsf_status.flcdone == 1)
 14.1139 +			break;
 14.1140 +		udelay(1);
 14.1141 +	} while (i++ < timeout);
 14.1142 +
 14.1143 +	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
 14.1144 +		return 0;
 14.1145 +
 14.1146 +	return ret_val;
 14.1147 +}
 14.1148 +
 14.1149 +/**
 14.1150 + *  e1000_read_flash_word_ich8lan - Read word from flash
 14.1151 + *  @hw: pointer to the HW structure
 14.1152 + *  @offset: offset to data location
 14.1153 + *  @data: pointer to the location for storing the data
 14.1154 + *
 14.1155 + *  Reads the flash word at offset into data.  Offset is converted
 14.1156 + *  to bytes before read.
 14.1157 + **/
 14.1158 +static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 14.1159 +					 u16 *data)
 14.1160 +{
 14.1161 +	/* Must convert offset into bytes. */
 14.1162 +	offset <<= 1;
 14.1163 +
 14.1164 +	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
 14.1165 +}
 14.1166 +
 14.1167 +/**
 14.1168 + *  e1000_read_flash_byte_ich8lan - Read byte from flash
 14.1169 + *  @hw: pointer to the HW structure
 14.1170 + *  @offset: The offset of the byte to read.
 14.1171 + *  @data: Pointer to a byte to store the value read.
 14.1172 + *
 14.1173 + *  Reads a single byte from the NVM using the flash access registers.
 14.1174 + **/
 14.1175 +static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 14.1176 +					 u8 *data)
 14.1177 +{
 14.1178 +	s32 ret_val;
 14.1179 +	u16 word = 0;
 14.1180 +
 14.1181 +	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
 14.1182 +	if (ret_val)
 14.1183 +		return ret_val;
 14.1184 +
 14.1185 +	*data = (u8)word;
 14.1186 +
 14.1187 +	return 0;
 14.1188 +}
 14.1189 +
 14.1190 +/**
 14.1191 + *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
 14.1192 + *  @hw: pointer to the HW structure
 14.1193 + *  @offset: The offset (in bytes) of the byte or word to read.
 14.1194 + *  @size: Size of data to read, 1=byte 2=word
 14.1195 + *  @data: Pointer to the word to store the value read.
 14.1196 + *
 14.1197 + *  Reads a byte or word from the NVM using the flash access registers.
 14.1198 + **/
 14.1199 +static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 14.1200 +					 u8 size, u16 *data)
 14.1201 +{
 14.1202 +	union ich8_hws_flash_status hsfsts;
 14.1203 +	union ich8_hws_flash_ctrl hsflctl;
 14.1204 +	u32 flash_linear_addr;
 14.1205 +	u32 flash_data = 0;
 14.1206 +	s32 ret_val = -E1000_ERR_NVM;
 14.1207 +	u8 count = 0;
 14.1208 +
 14.1209 +	if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
 14.1210 +		return -E1000_ERR_NVM;
 14.1211 +
 14.1212 +	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
 14.1213 +			    hw->nvm.flash_base_addr;
 14.1214 +
 14.1215 +	do {
 14.1216 +		udelay(1);
 14.1217 +		/* Steps */
 14.1218 +		ret_val = e1000_flash_cycle_init_ich8lan(hw);
 14.1219 +		if (ret_val != 0)
 14.1220 +			break;
 14.1221 +
 14.1222 +		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
 14.1223 +		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
 14.1224 +		hsflctl.hsf_ctrl.fldbcount = size - 1;
 14.1225 +		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
 14.1226 +		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
 14.1227 +
 14.1228 +		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
 14.1229 +
 14.1230 +		ret_val = e1000_flash_cycle_ich8lan(hw,
 14.1231 +						ICH_FLASH_READ_COMMAND_TIMEOUT);
 14.1232 +
 14.1233 +		/*
 14.1234 +		 * Check if FCERR is set to 1, if set to 1, clear it
 14.1235 +		 * and try the whole sequence a few more times, else
 14.1236 +		 * read in (shift in) the Flash Data0, the order is
 14.1237 +		 * least significant byte first msb to lsb
 14.1238 +		 */
 14.1239 +		if (ret_val == 0) {
 14.1240 +			flash_data = er32flash(ICH_FLASH_FDATA0);
 14.1241 +			if (size == 1) {
 14.1242 +				*data = (u8)(flash_data & 0x000000FF);
 14.1243 +			} else if (size == 2) {
 14.1244 +				*data = (u16)(flash_data & 0x0000FFFF);
 14.1245 +			}
 14.1246 +			break;
 14.1247 +		} else {
 14.1248 +			/*
 14.1249 +			 * If we've gotten here, then things are probably
 14.1250 +			 * completely hosed, but if the error condition is
 14.1251 +			 * detected, it won't hurt to give it another try...
 14.1252 +			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
 14.1253 +			 */
 14.1254 +			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1255 +			if (hsfsts.hsf_status.flcerr == 1) {
 14.1256 +				/* Repeat for some time before giving up. */
 14.1257 +				continue;
 14.1258 +			} else if (hsfsts.hsf_status.flcdone == 0) {
 14.1259 +				hw_dbg(hw, "Timeout error - flash cycle "
 14.1260 +					 "did not complete.");
 14.1261 +				break;
 14.1262 +			}
 14.1263 +		}
 14.1264 +	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
 14.1265 +
 14.1266 +	return ret_val;
 14.1267 +}
 14.1268 +
 14.1269 +/**
 14.1270 + *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
 14.1271 + *  @hw: pointer to the HW structure
 14.1272 + *  @offset: The offset (in bytes) of the word(s) to write.
 14.1273 + *  @words: Size of data to write in words
 14.1274 + *  @data: Pointer to the word(s) to write at offset.
 14.1275 + *
 14.1276 + *  Writes a byte or word to the NVM using the flash access registers.
 14.1277 + **/
 14.1278 +static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 14.1279 +				   u16 *data)
 14.1280 +{
 14.1281 +	struct e1000_nvm_info *nvm = &hw->nvm;
 14.1282 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 14.1283 +	s32 ret_val;
 14.1284 +	u16 i;
 14.1285 +
 14.1286 +	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 14.1287 +	    (words == 0)) {
 14.1288 +		hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 14.1289 +		return -E1000_ERR_NVM;
 14.1290 +	}
 14.1291 +
 14.1292 +	ret_val = e1000_acquire_swflag_ich8lan(hw);
 14.1293 +	if (ret_val)
 14.1294 +		return ret_val;
 14.1295 +
 14.1296 +	for (i = 0; i < words; i++) {
 14.1297 +		dev_spec->shadow_ram[offset+i].modified = 1;
 14.1298 +		dev_spec->shadow_ram[offset+i].value = data[i];
 14.1299 +	}
 14.1300 +
 14.1301 +	e1000_release_swflag_ich8lan(hw);
 14.1302 +
 14.1303 +	return 0;
 14.1304 +}
 14.1305 +
 14.1306 +/**
 14.1307 + *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
 14.1308 + *  @hw: pointer to the HW structure
 14.1309 + *
 14.1310 + *  The NVM checksum is updated by calling the generic update_nvm_checksum,
 14.1311 + *  which writes the checksum to the shadow ram.  The changes in the shadow
 14.1312 + *  ram are then committed to the EEPROM by processing each bank at a time
 14.1313 + *  checking for the modified bit and writing only the pending changes.
 14.1314 + *  After a successful commit, the shadow ram is cleared and is ready for
 14.1315 + *  future writes.
 14.1316 + **/
 14.1317 +static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 14.1318 +{
 14.1319 +	struct e1000_nvm_info *nvm = &hw->nvm;
 14.1320 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 14.1321 +	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
 14.1322 +	s32 ret_val;
 14.1323 +	u16 data;
 14.1324 +
 14.1325 +	ret_val = e1000e_update_nvm_checksum_generic(hw);
 14.1326 +	if (ret_val)
 14.1327 +		return ret_val;
 14.1328 +
 14.1329 +	if (nvm->type != e1000_nvm_flash_sw)
 14.1330 +		return ret_val;
 14.1331 +
 14.1332 +	ret_val = e1000_acquire_swflag_ich8lan(hw);
 14.1333 +	if (ret_val)
 14.1334 +		return ret_val;
 14.1335 +
 14.1336 +	/*
 14.1337 +	 * We're writing to the opposite bank so if we're on bank 1,
 14.1338 +	 * write to bank 0 etc.  We also need to erase the segment that
 14.1339 +	 * is going to be written
 14.1340 +	 */
 14.1341 +	ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
 14.1342 +	if (ret_val)
 14.1343 +		return ret_val;
 14.1344 +
 14.1345 +	if (bank == 0) {
 14.1346 +		new_bank_offset = nvm->flash_bank_size;
 14.1347 +		old_bank_offset = 0;
 14.1348 +		e1000_erase_flash_bank_ich8lan(hw, 1);
 14.1349 +	} else {
 14.1350 +		old_bank_offset = nvm->flash_bank_size;
 14.1351 +		new_bank_offset = 0;
 14.1352 +		e1000_erase_flash_bank_ich8lan(hw, 0);
 14.1353 +	}
 14.1354 +
 14.1355 +	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
 14.1356 +		/*
 14.1357 +		 * Determine whether to write the value stored
 14.1358 +		 * in the other NVM bank or a modified value stored
 14.1359 +		 * in the shadow RAM
 14.1360 +		 */
 14.1361 +		if (dev_spec->shadow_ram[i].modified) {
 14.1362 +			data = dev_spec->shadow_ram[i].value;
 14.1363 +		} else {
 14.1364 +			e1000_read_flash_word_ich8lan(hw,
 14.1365 +						      i + old_bank_offset,
 14.1366 +						      &data);
 14.1367 +		}
 14.1368 +
 14.1369 +		/*
 14.1370 +		 * If the word is 0x13, then make sure the signature bits
 14.1371 +		 * (15:14) are 11b until the commit has completed.
 14.1372 +		 * This will allow us to write 10b which indicates the
 14.1373 +		 * signature is valid.  We want to do this after the write
 14.1374 +		 * has completed so that we don't mark the segment valid
 14.1375 +		 * while the write is still in progress
 14.1376 +		 */
 14.1377 +		if (i == E1000_ICH_NVM_SIG_WORD)
 14.1378 +			data |= E1000_ICH_NVM_SIG_MASK;
 14.1379 +
 14.1380 +		/* Convert offset to bytes. */
 14.1381 +		act_offset = (i + new_bank_offset) << 1;
 14.1382 +
 14.1383 +		udelay(100);
 14.1384 +		/* Write the bytes to the new bank. */
 14.1385 +		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
 14.1386 +							       act_offset,
 14.1387 +							       (u8)data);
 14.1388 +		if (ret_val)
 14.1389 +			break;
 14.1390 +
 14.1391 +		udelay(100);
 14.1392 +		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
 14.1393 +							  act_offset + 1,
 14.1394 +							  (u8)(data >> 8));
 14.1395 +		if (ret_val)
 14.1396 +			break;
 14.1397 +	}
 14.1398 +
 14.1399 +	/*
 14.1400 +	 * Don't bother writing the segment valid bits if sector
 14.1401 +	 * programming failed.
 14.1402 +	 */
 14.1403 +	if (ret_val) {
 14.1404 +		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
 14.1405 +		hw_dbg(hw, "Flash commit failed.\n");
 14.1406 +		e1000_release_swflag_ich8lan(hw);
 14.1407 +		return ret_val;
 14.1408 +	}
 14.1409 +
 14.1410 +	/*
 14.1411 +	 * Finally validate the new segment by setting bit 15:14
 14.1412 +	 * to 10b in word 0x13 , this can be done without an
 14.1413 +	 * erase as well since these bits are 11 to start with
 14.1414 +	 * and we need to change bit 14 to 0b
 14.1415 +	 */
 14.1416 +	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
 14.1417 +	e1000_read_flash_word_ich8lan(hw, act_offset, &data);
 14.1418 +	data &= 0xBFFF;
 14.1419 +	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
 14.1420 +						       act_offset * 2 + 1,
 14.1421 +						       (u8)(data >> 8));
 14.1422 +	if (ret_val) {
 14.1423 +		e1000_release_swflag_ich8lan(hw);
 14.1424 +		return ret_val;
 14.1425 +	}
 14.1426 +
 14.1427 +	/*
 14.1428 +	 * And invalidate the previously valid segment by setting
 14.1429 +	 * its signature word (0x13) high_byte to 0b. This can be
 14.1430 +	 * done without an erase because flash erase sets all bits
 14.1431 +	 * to 1's. We can write 1's to 0's without an erase
 14.1432 +	 */
 14.1433 +	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
 14.1434 +	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
 14.1435 +	if (ret_val) {
 14.1436 +		e1000_release_swflag_ich8lan(hw);
 14.1437 +		return ret_val;
 14.1438 +	}
 14.1439 +
 14.1440 +	/* Great!  Everything worked, we can now clear the cached entries. */
 14.1441 +	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
 14.1442 +		dev_spec->shadow_ram[i].modified = 0;
 14.1443 +		dev_spec->shadow_ram[i].value = 0xFFFF;
 14.1444 +	}
 14.1445 +
 14.1446 +	e1000_release_swflag_ich8lan(hw);
 14.1447 +
 14.1448 +	/*
 14.1449 +	 * Reload the EEPROM, or else modifications will not appear
 14.1450 +	 * until after the next adapter reset.
 14.1451 +	 */
 14.1452 +	e1000e_reload_nvm(hw);
 14.1453 +	msleep(10);
 14.1454 +
 14.1455 +	return ret_val;
 14.1456 +}
 14.1457 +
 14.1458 +/**
 14.1459 + *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
 14.1460 + *  @hw: pointer to the HW structure
 14.1461 + *
 14.1462 + *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
 14.1463 + *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
 14.1464 + *  calculated, in which case we need to calculate the checksum and set bit 6.
 14.1465 + **/
 14.1466 +static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
 14.1467 +{
 14.1468 +	s32 ret_val;
 14.1469 +	u16 data;
 14.1470 +
 14.1471 +	/*
 14.1472 +	 * Read 0x19 and check bit 6.  If this bit is 0, the checksum
 14.1473 +	 * needs to be fixed.  This bit is an indication that the NVM
 14.1474 +	 * was prepared by OEM software and did not calculate the
 14.1475 +	 * checksum...a likely scenario.
 14.1476 +	 */
 14.1477 +	ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
 14.1478 +	if (ret_val)
 14.1479 +		return ret_val;
 14.1480 +
 14.1481 +	if ((data & 0x40) == 0) {
 14.1482 +		data |= 0x40;
 14.1483 +		ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
 14.1484 +		if (ret_val)
 14.1485 +			return ret_val;
 14.1486 +		ret_val = e1000e_update_nvm_checksum(hw);
 14.1487 +		if (ret_val)
 14.1488 +			return ret_val;
 14.1489 +	}
 14.1490 +
 14.1491 +	return e1000e_validate_nvm_checksum_generic(hw);
 14.1492 +}
 14.1493 +
 14.1494 +/**
 14.1495 + *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
 14.1496 + *  @hw: pointer to the HW structure
 14.1497 + *
 14.1498 + *  To prevent malicious write/erase of the NVM, set it to be read-only
 14.1499 + *  so that the hardware ignores all write/erase cycles of the NVM via
 14.1500 + *  the flash control registers.  The shadow-ram copy of the NVM will
 14.1501 + *  still be updated, however any updates to this copy will not stick
 14.1502 + *  across driver reloads.
 14.1503 + **/
 14.1504 +void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
 14.1505 +{
 14.1506 +	union ich8_flash_protected_range pr0;
 14.1507 +	union ich8_hws_flash_status hsfsts;
 14.1508 +	u32 gfpreg;
 14.1509 +	s32 ret_val;
 14.1510 +
 14.1511 +	ret_val = e1000_acquire_swflag_ich8lan(hw);
 14.1512 +	if (ret_val)
 14.1513 +		return;
 14.1514 +
 14.1515 +	gfpreg = er32flash(ICH_FLASH_GFPREG);
 14.1516 +
 14.1517 +	/* Write-protect GbE Sector of NVM */
 14.1518 +	pr0.regval = er32flash(ICH_FLASH_PR0);
 14.1519 +	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
 14.1520 +	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
 14.1521 +	pr0.range.wpe = true;
 14.1522 +	ew32flash(ICH_FLASH_PR0, pr0.regval);
 14.1523 +
 14.1524 +	/*
 14.1525 +	 * Lock down a subset of GbE Flash Control Registers, e.g.
 14.1526 +	 * PR0 to prevent the write-protection from being lifted.
 14.1527 +	 * Once FLOCKDN is set, the registers protected by it cannot
 14.1528 +	 * be written until FLOCKDN is cleared by a hardware reset.
 14.1529 +	 */
 14.1530 +	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1531 +	hsfsts.hsf_status.flockdn = true;
 14.1532 +	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 14.1533 +
 14.1534 +	e1000_release_swflag_ich8lan(hw);
 14.1535 +}
 14.1536 +
 14.1537 +/**
 14.1538 + *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
 14.1539 + *  @hw: pointer to the HW structure
 14.1540 + *  @offset: The offset (in bytes) of the byte/word to read.
 14.1541 + *  @size: Size of data to read, 1=byte 2=word
 14.1542 + *  @data: The byte(s) to write to the NVM.
 14.1543 + *
 14.1544 + *  Writes one/two bytes to the NVM using the flash access registers.
 14.1545 + **/
 14.1546 +static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 14.1547 +					  u8 size, u16 data)
 14.1548 +{
 14.1549 +	union ich8_hws_flash_status hsfsts;
 14.1550 +	union ich8_hws_flash_ctrl hsflctl;
 14.1551 +	u32 flash_linear_addr;
 14.1552 +	u32 flash_data = 0;
 14.1553 +	s32 ret_val;
 14.1554 +	u8 count = 0;
 14.1555 +
 14.1556 +	if (size < 1 || size > 2 || data > size * 0xff ||
 14.1557 +	    offset > ICH_FLASH_LINEAR_ADDR_MASK)
 14.1558 +		return -E1000_ERR_NVM;
 14.1559 +
 14.1560 +	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
 14.1561 +			    hw->nvm.flash_base_addr;
 14.1562 +
 14.1563 +	do {
 14.1564 +		udelay(1);
 14.1565 +		/* Steps */
 14.1566 +		ret_val = e1000_flash_cycle_init_ich8lan(hw);
 14.1567 +		if (ret_val)
 14.1568 +			break;
 14.1569 +
 14.1570 +		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
 14.1571 +		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
 14.1572 +		hsflctl.hsf_ctrl.fldbcount = size -1;
 14.1573 +		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
 14.1574 +		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
 14.1575 +
 14.1576 +		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
 14.1577 +
 14.1578 +		if (size == 1)
 14.1579 +			flash_data = (u32)data & 0x00FF;
 14.1580 +		else
 14.1581 +			flash_data = (u32)data;
 14.1582 +
 14.1583 +		ew32flash(ICH_FLASH_FDATA0, flash_data);
 14.1584 +
 14.1585 +		/*
 14.1586 +		 * check if FCERR is set to 1 , if set to 1, clear it
 14.1587 +		 * and try the whole sequence a few more times else done
 14.1588 +		 */
 14.1589 +		ret_val = e1000_flash_cycle_ich8lan(hw,
 14.1590 +					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
 14.1591 +		if (!ret_val)
 14.1592 +			break;
 14.1593 +
 14.1594 +		/*
 14.1595 +		 * If we're here, then things are most likely
 14.1596 +		 * completely hosed, but if the error condition
 14.1597 +		 * is detected, it won't hurt to give it another
 14.1598 +		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
 14.1599 +		 */
 14.1600 +		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1601 +		if (hsfsts.hsf_status.flcerr == 1)
 14.1602 +			/* Repeat for some time before giving up. */
 14.1603 +			continue;
 14.1604 +		if (hsfsts.hsf_status.flcdone == 0) {
 14.1605 +			hw_dbg(hw, "Timeout error - flash cycle "
 14.1606 +				 "did not complete.");
 14.1607 +			break;
 14.1608 +		}
 14.1609 +	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
 14.1610 +
 14.1611 +	return ret_val;
 14.1612 +}
 14.1613 +
 14.1614 +/**
 14.1615 + *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
 14.1616 + *  @hw: pointer to the HW structure
 14.1617 + *  @offset: The index of the byte to read.
 14.1618 + *  @data: The byte to write to the NVM.
 14.1619 + *
 14.1620 + *  Writes a single byte to the NVM using the flash access registers.
 14.1621 + **/
 14.1622 +static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 14.1623 +					  u8 data)
 14.1624 +{
 14.1625 +	u16 word = (u16)data;
 14.1626 +
 14.1627 +	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
 14.1628 +}
 14.1629 +
 14.1630 +/**
 14.1631 + *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
 14.1632 + *  @hw: pointer to the HW structure
 14.1633 + *  @offset: The offset of the byte to write.
 14.1634 + *  @byte: The byte to write to the NVM.
 14.1635 + *
 14.1636 + *  Writes a single byte to the NVM using the flash access registers.
 14.1637 + *  Goes through a retry algorithm before giving up.
 14.1638 + **/
 14.1639 +static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 14.1640 +						u32 offset, u8 byte)
 14.1641 +{
 14.1642 +	s32 ret_val;
 14.1643 +	u16 program_retries;
 14.1644 +
 14.1645 +	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
 14.1646 +	if (!ret_val)
 14.1647 +		return ret_val;
 14.1648 +
 14.1649 +	for (program_retries = 0; program_retries < 100; program_retries++) {
 14.1650 +		hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
 14.1651 +		udelay(100);
 14.1652 +		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
 14.1653 +		if (!ret_val)
 14.1654 +			break;
 14.1655 +	}
 14.1656 +	if (program_retries == 100)
 14.1657 +		return -E1000_ERR_NVM;
 14.1658 +
 14.1659 +	return 0;
 14.1660 +}
 14.1661 +
 14.1662 +/**
 14.1663 + *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
 14.1664 + *  @hw: pointer to the HW structure
 14.1665 + *  @bank: 0 for first bank, 1 for second bank, etc.
 14.1666 + *
 14.1667 + *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
 14.1668 + *  bank N is 4096 * N + flash_reg_addr.
 14.1669 + **/
 14.1670 +static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
 14.1671 +{
 14.1672 +	struct e1000_nvm_info *nvm = &hw->nvm;
 14.1673 +	union ich8_hws_flash_status hsfsts;
 14.1674 +	union ich8_hws_flash_ctrl hsflctl;
 14.1675 +	u32 flash_linear_addr;
 14.1676 +	/* bank size is in 16bit words - adjust to bytes */
 14.1677 +	u32 flash_bank_size = nvm->flash_bank_size * 2;
 14.1678 +	s32 ret_val;
 14.1679 +	s32 count = 0;
 14.1680 +	s32 iteration;
 14.1681 +	s32 sector_size;
 14.1682 +	s32 j;
 14.1683 +
 14.1684 +	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1685 +
 14.1686 +	/*
 14.1687 +	 * Determine HW Sector size: Read BERASE bits of hw flash status
 14.1688 +	 * register
 14.1689 +	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
 14.1690 +	 *     consecutive sectors.  The start index for the nth Hw sector
 14.1691 +	 *     can be calculated as = bank * 4096 + n * 256
 14.1692 +	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
 14.1693 +	 *     The start index for the nth Hw sector can be calculated
 14.1694 +	 *     as = bank * 4096
 14.1695 +	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
 14.1696 +	 *     (ich9 only, otherwise error condition)
 14.1697 +	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
 14.1698 +	 */
 14.1699 +	switch (hsfsts.hsf_status.berasesz) {
 14.1700 +	case 0:
 14.1701 +		/* Hw sector size 256 */
 14.1702 +		sector_size = ICH_FLASH_SEG_SIZE_256;
 14.1703 +		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
 14.1704 +		break;
 14.1705 +	case 1:
 14.1706 +		sector_size = ICH_FLASH_SEG_SIZE_4K;
 14.1707 +		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
 14.1708 +		break;
 14.1709 +	case 2:
 14.1710 +		if (hw->mac.type == e1000_ich9lan) {
 14.1711 +			sector_size = ICH_FLASH_SEG_SIZE_8K;
 14.1712 +			iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
 14.1713 +		} else {
 14.1714 +			return -E1000_ERR_NVM;
 14.1715 +		}
 14.1716 +		break;
 14.1717 +	case 3:
 14.1718 +		sector_size = ICH_FLASH_SEG_SIZE_64K;
 14.1719 +		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
 14.1720 +		break;
 14.1721 +	default:
 14.1722 +		return -E1000_ERR_NVM;
 14.1723 +	}
 14.1724 +
 14.1725 +	/* Start with the base address, then add the sector offset. */
 14.1726 +	flash_linear_addr = hw->nvm.flash_base_addr;
 14.1727 +	flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
 14.1728 +
 14.1729 +	for (j = 0; j < iteration ; j++) {
 14.1730 +		do {
 14.1731 +			/* Steps */
 14.1732 +			ret_val = e1000_flash_cycle_init_ich8lan(hw);
 14.1733 +			if (ret_val)
 14.1734 +				return ret_val;
 14.1735 +
 14.1736 +			/*
 14.1737 +			 * Write a value 11 (block Erase) in Flash
 14.1738 +			 * Cycle field in hw flash control
 14.1739 +			 */
 14.1740 +			hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
 14.1741 +			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
 14.1742 +			ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
 14.1743 +
 14.1744 +			/*
 14.1745 +			 * Write the last 24 bits of an index within the
 14.1746 +			 * block into Flash Linear address field in Flash
 14.1747 +			 * Address.
 14.1748 +			 */
 14.1749 +			flash_linear_addr += (j * sector_size);
 14.1750 +			ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
 14.1751 +
 14.1752 +			ret_val = e1000_flash_cycle_ich8lan(hw,
 14.1753 +					       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
 14.1754 +			if (ret_val == 0)
 14.1755 +				break;
 14.1756 +
 14.1757 +			/*
 14.1758 +			 * Check if FCERR is set to 1.  If 1,
 14.1759 +			 * clear it and try the whole sequence
 14.1760 +			 * a few more times else Done
 14.1761 +			 */
 14.1762 +			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 14.1763 +			if (hsfsts.hsf_status.flcerr == 1)
 14.1764 +				/* repeat for some time before giving up */
 14.1765 +				continue;
 14.1766 +			else if (hsfsts.hsf_status.flcdone == 0)
 14.1767 +				return ret_val;
 14.1768 +		} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
 14.1769 +	}
 14.1770 +
 14.1771 +	return 0;
 14.1772 +}
 14.1773 +
 14.1774 +/**
 14.1775 + *  e1000_valid_led_default_ich8lan - Set the default LED settings
 14.1776 + *  @hw: pointer to the HW structure
 14.1777 + *  @data: Pointer to the LED settings
 14.1778 + *
 14.1779 + *  Reads the LED default settings from the NVM to data.  If the NVM LED
 14.1780 + *  settings is all 0's or F's, set the LED default to a valid LED default
 14.1781 + *  setting.
 14.1782 + **/
 14.1783 +static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
 14.1784 +{
 14.1785 +	s32 ret_val;
 14.1786 +
 14.1787 +	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
 14.1788 +	if (ret_val) {
 14.1789 +		hw_dbg(hw, "NVM Read Error\n");
 14.1790 +		return ret_val;
 14.1791 +	}
 14.1792 +
 14.1793 +	if (*data == ID_LED_RESERVED_0000 ||
 14.1794 +	    *data == ID_LED_RESERVED_FFFF)
 14.1795 +		*data = ID_LED_DEFAULT_ICH8LAN;
 14.1796 +
 14.1797 +	return 0;
 14.1798 +}
 14.1799 +
 14.1800 +/**
 14.1801 + *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
 14.1802 + *  @hw: pointer to the HW structure
 14.1803 + *
 14.1804 + *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
 14.1805 + *  register, so the the bus width is hard coded.
 14.1806 + **/
 14.1807 +static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 14.1808 +{
 14.1809 +	struct e1000_bus_info *bus = &hw->bus;
 14.1810 +	s32 ret_val;
 14.1811 +
 14.1812 +	ret_val = e1000e_get_bus_info_pcie(hw);
 14.1813 +
 14.1814 +	/*
 14.1815 +	 * ICH devices are "PCI Express"-ish.  They have
 14.1816 +	 * a configuration space, but do not contain
 14.1817 +	 * PCI Express Capability registers, so bus width
 14.1818 +	 * must be hardcoded.
 14.1819 +	 */
 14.1820 +	if (bus->width == e1000_bus_width_unknown)
 14.1821 +		bus->width = e1000_bus_width_pcie_x1;
 14.1822 +
 14.1823 +	return ret_val;
 14.1824 +}
 14.1825 +
 14.1826 +/**
 14.1827 + *  e1000_reset_hw_ich8lan - Reset the hardware
 14.1828 + *  @hw: pointer to the HW structure
 14.1829 + *
 14.1830 + *  Does a full reset of the hardware which includes a reset of the PHY and
 14.1831 + *  MAC.
 14.1832 + **/
 14.1833 +static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 14.1834 +{
 14.1835 +	u32 ctrl, icr, kab;
 14.1836 +	s32 ret_val;
 14.1837 +
 14.1838 +	/*
 14.1839 +	 * Prevent the PCI-E bus from sticking if there is no TLP connection
 14.1840 +	 * on the last TLP read/write transaction when MAC is reset.
 14.1841 +	 */
 14.1842 +	ret_val = e1000e_disable_pcie_master(hw);
 14.1843 +	if (ret_val) {
 14.1844 +		hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 14.1845 +	}
 14.1846 +
 14.1847 +	hw_dbg(hw, "Masking off all interrupts\n");
 14.1848 +	ew32(IMC, 0xffffffff);
 14.1849 +
 14.1850 +	/*
 14.1851 +	 * Disable the Transmit and Receive units.  Then delay to allow
 14.1852 +	 * any pending transactions to complete before we hit the MAC
 14.1853 +	 * with the global reset.
 14.1854 +	 */
 14.1855 +	ew32(RCTL, 0);
 14.1856 +	ew32(TCTL, E1000_TCTL_PSP);
 14.1857 +	e1e_flush();
 14.1858 +
 14.1859 +	msleep(10);
 14.1860 +
 14.1861 +	/* Workaround for ICH8 bit corruption issue in FIFO memory */
 14.1862 +	if (hw->mac.type == e1000_ich8lan) {
 14.1863 +		/* Set Tx and Rx buffer allocation to 8k apiece. */
 14.1864 +		ew32(PBA, E1000_PBA_8K);
 14.1865 +		/* Set Packet Buffer Size to 16k. */
 14.1866 +		ew32(PBS, E1000_PBS_16K);
 14.1867 +	}
 14.1868 +
 14.1869 +	ctrl = er32(CTRL);
 14.1870 +
 14.1871 +	if (!e1000_check_reset_block(hw)) {
 14.1872 +		/*
 14.1873 +		 * PHY HW reset requires MAC CORE reset at the same
 14.1874 +		 * time to make sure the interface between MAC and the
 14.1875 +		 * external PHY is reset.
 14.1876 +		 */
 14.1877 +		ctrl |= E1000_CTRL_PHY_RST;
 14.1878 +	}
 14.1879 +	ret_val = e1000_acquire_swflag_ich8lan(hw);
 14.1880 +	hw_dbg(hw, "Issuing a global reset to ich8lan");
 14.1881 +	ew32(CTRL, (ctrl | E1000_CTRL_RST));
 14.1882 +	msleep(20);
 14.1883 +
 14.1884 +	ret_val = e1000e_get_auto_rd_done(hw);
 14.1885 +	if (ret_val) {
 14.1886 +		/*
 14.1887 +		 * When auto config read does not complete, do not
 14.1888 +		 * return with an error. This can happen in situations
 14.1889 +		 * where there is no eeprom and prevents getting link.
 14.1890 +		 */
 14.1891 +		hw_dbg(hw, "Auto Read Done did not complete\n");
 14.1892 +	}
 14.1893 +
 14.1894 +	ew32(IMC, 0xffffffff);
 14.1895 +	icr = er32(ICR);
 14.1896 +
 14.1897 +	kab = er32(KABGTXD);
 14.1898 +	kab |= E1000_KABGTXD_BGSQLBIAS;
 14.1899 +	ew32(KABGTXD, kab);
 14.1900 +
 14.1901 +	return ret_val;
 14.1902 +}
 14.1903 +
 14.1904 +/**
 14.1905 + *  e1000_init_hw_ich8lan - Initialize the hardware
 14.1906 + *  @hw: pointer to the HW structure
 14.1907 + *
 14.1908 + *  Prepares the hardware for transmit and receive by doing the following:
 14.1909 + *   - initialize hardware bits
 14.1910 + *   - initialize LED identification
 14.1911 + *   - setup receive address registers
 14.1912 + *   - setup flow control
 14.1913 + *   - setup transmit descriptors
 14.1914 + *   - clear statistics
 14.1915 + **/
 14.1916 +static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
 14.1917 +{
 14.1918 +	struct e1000_mac_info *mac = &hw->mac;
 14.1919 +	u32 ctrl_ext, txdctl, snoop;
 14.1920 +	s32 ret_val;
 14.1921 +	u16 i;
 14.1922 +
 14.1923 +	e1000_initialize_hw_bits_ich8lan(hw);
 14.1924 +
 14.1925 +	/* Initialize identification LED */
 14.1926 +	ret_val = e1000e_id_led_init(hw);
 14.1927 +	if (ret_val) {
 14.1928 +		hw_dbg(hw, "Error initializing identification LED\n");
 14.1929 +		return ret_val;
 14.1930 +	}
 14.1931 +
 14.1932 +	/* Setup the receive address. */
 14.1933 +	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 14.1934 +
 14.1935 +	/* Zero out the Multicast HASH table */
 14.1936 +	hw_dbg(hw, "Zeroing the MTA\n");
 14.1937 +	for (i = 0; i < mac->mta_reg_count; i++)
 14.1938 +		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 14.1939 +
 14.1940 +	/* Setup link and flow control */
 14.1941 +	ret_val = e1000_setup_link_ich8lan(hw);
 14.1942 +
 14.1943 +	/* Set the transmit descriptor write-back policy for both queues */
 14.1944 +	txdctl = er32(TXDCTL(0));
 14.1945 +	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 14.1946 +		 E1000_TXDCTL_FULL_TX_DESC_WB;
 14.1947 +	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
 14.1948 +		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 14.1949 +	ew32(TXDCTL(0), txdctl);
 14.1950 +	txdctl = er32(TXDCTL(1));
 14.1951 +	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 14.1952 +		 E1000_TXDCTL_FULL_TX_DESC_WB;
 14.1953 +	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
 14.1954 +		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 14.1955 +	ew32(TXDCTL(1), txdctl);
 14.1956 +
 14.1957 +	/*
 14.1958 +	 * ICH8 has opposite polarity of no_snoop bits.
 14.1959 +	 * By default, we should use snoop behavior.
 14.1960 +	 */
 14.1961 +	if (mac->type == e1000_ich8lan)
 14.1962 +		snoop = PCIE_ICH8_SNOOP_ALL;
 14.1963 +	else
 14.1964 +		snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
 14.1965 +	e1000e_set_pcie_no_snoop(hw, snoop);
 14.1966 +
 14.1967 +	ctrl_ext = er32(CTRL_EXT);
 14.1968 +	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
 14.1969 +	ew32(CTRL_EXT, ctrl_ext);
 14.1970 +
 14.1971 +	/*
 14.1972 +	 * Clear all of the statistics registers (clear on read).  It is
 14.1973 +	 * important that we do this after we have tried to establish link
 14.1974 +	 * because the symbol error count will increment wildly if there
 14.1975 +	 * is no link.
 14.1976 +	 */
 14.1977 +	e1000_clear_hw_cntrs_ich8lan(hw);
 14.1978 +
 14.1979 +	return 0;
 14.1980 +}
 14.1981 +/**
 14.1982 + *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
 14.1983 + *  @hw: pointer to the HW structure
 14.1984 + *
 14.1985 + *  Sets/Clears required hardware bits necessary for correctly setting up the
 14.1986 + *  hardware for transmit and receive.
 14.1987 + **/
 14.1988 +static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
 14.1989 +{
 14.1990 +	u32 reg;
 14.1991 +
 14.1992 +	/* Extended Device Control */
 14.1993 +	reg = er32(CTRL_EXT);
 14.1994 +	reg |= (1 << 22);
 14.1995 +	ew32(CTRL_EXT, reg);
 14.1996 +
 14.1997 +	/* Transmit Descriptor Control 0 */
 14.1998 +	reg = er32(TXDCTL(0));
 14.1999 +	reg |= (1 << 22);
 14.2000 +	ew32(TXDCTL(0), reg);
 14.2001 +
 14.2002 +	/* Transmit Descriptor Control 1 */
 14.2003 +	reg = er32(TXDCTL(1));
 14.2004 +	reg |= (1 << 22);
 14.2005 +	ew32(TXDCTL(1), reg);
 14.2006 +
 14.2007 +	/* Transmit Arbitration Control 0 */
 14.2008 +	reg = er32(TARC(0));
 14.2009 +	if (hw->mac.type == e1000_ich8lan)
 14.2010 +		reg |= (1 << 28) | (1 << 29);
 14.2011 +	reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
 14.2012 +	ew32(TARC(0), reg);
 14.2013 +
 14.2014 +	/* Transmit Arbitration Control 1 */
 14.2015 +	reg = er32(TARC(1));
 14.2016 +	if (er32(TCTL) & E1000_TCTL_MULR)
 14.2017 +		reg &= ~(1 << 28);
 14.2018 +	else
 14.2019 +		reg |= (1 << 28);
 14.2020 +	reg |= (1 << 24) | (1 << 26) | (1 << 30);
 14.2021 +	ew32(TARC(1), reg);
 14.2022 +
 14.2023 +	/* Device Status */
 14.2024 +	if (hw->mac.type == e1000_ich8lan) {
 14.2025 +		reg = er32(STATUS);
 14.2026 +		reg &= ~(1 << 31);
 14.2027 +		ew32(STATUS, reg);
 14.2028 +	}
 14.2029 +}
 14.2030 +
 14.2031 +/**
 14.2032 + *  e1000_setup_link_ich8lan - Setup flow control and link settings
 14.2033 + *  @hw: pointer to the HW structure
 14.2034 + *
 14.2035 + *  Determines which flow control settings to use, then configures flow
 14.2036 + *  control.  Calls the appropriate media-specific link configuration
 14.2037 + *  function.  Assuming the adapter has a valid link partner, a valid link
 14.2038 + *  should be established.  Assumes the hardware has previously been reset
 14.2039 + *  and the transmitter and receiver are not enabled.
 14.2040 + **/
 14.2041 +static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
 14.2042 +{
 14.2043 +	s32 ret_val;
 14.2044 +
 14.2045 +	if (e1000_check_reset_block(hw))
 14.2046 +		return 0;
 14.2047 +
 14.2048 +	/*
 14.2049 +	 * ICH parts do not have a word in the NVM to determine
 14.2050 +	 * the default flow control setting, so we explicitly
 14.2051 +	 * set it to full.
 14.2052 +	 */
 14.2053 +	if (hw->fc.type == e1000_fc_default)
 14.2054 +		hw->fc.type = e1000_fc_full;
 14.2055 +
 14.2056 +	hw->fc.original_type = hw->fc.type;
 14.2057 +
 14.2058 +	hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
 14.2059 +
 14.2060 +	/* Continue to configure the copper link. */
 14.2061 +	ret_val = e1000_setup_copper_link_ich8lan(hw);
 14.2062 +	if (ret_val)
 14.2063 +		return ret_val;
 14.2064 +
 14.2065 +	ew32(FCTTV, hw->fc.pause_time);
 14.2066 +
 14.2067 +	return e1000e_set_fc_watermarks(hw);
 14.2068 +}
 14.2069 +
 14.2070 +/**
 14.2071 + *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
 14.2072 + *  @hw: pointer to the HW structure
 14.2073 + *
 14.2074 + *  Configures the kumeran interface to the PHY to wait the appropriate time
 14.2075 + *  when polling the PHY, then call the generic setup_copper_link to finish
 14.2076 + *  configuring the copper link.
 14.2077 + **/
 14.2078 +static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
 14.2079 +{
 14.2080 +	u32 ctrl;
 14.2081 +	s32 ret_val;
 14.2082 +	u16 reg_data;
 14.2083 +
 14.2084 +	ctrl = er32(CTRL);
 14.2085 +	ctrl |= E1000_CTRL_SLU;
 14.2086 +	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 14.2087 +	ew32(CTRL, ctrl);
 14.2088 +
 14.2089 +	/*
 14.2090 +	 * Set the mac to wait the maximum time between each iteration
 14.2091 +	 * and increase the max iterations when polling the phy;
 14.2092 +	 * this fixes erroneous timeouts at 10Mbps.
 14.2093 +	 */
 14.2094 +	ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
 14.2095 +	if (ret_val)
 14.2096 +		return ret_val;
 14.2097 +	ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
 14.2098 +	if (ret_val)
 14.2099 +		return ret_val;
 14.2100 +	reg_data |= 0x3F;
 14.2101 +	ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
 14.2102 +	if (ret_val)
 14.2103 +		return ret_val;
 14.2104 +
 14.2105 +	if (hw->phy.type == e1000_phy_igp_3) {
 14.2106 +		ret_val = e1000e_copper_link_setup_igp(hw);
 14.2107 +		if (ret_val)
 14.2108 +			return ret_val;
 14.2109 +	} else if (hw->phy.type == e1000_phy_bm) {
 14.2110 +		ret_val = e1000e_copper_link_setup_m88(hw);
 14.2111 +		if (ret_val)
 14.2112 +			return ret_val;
 14.2113 +	}
 14.2114 +
 14.2115 +	if (hw->phy.type == e1000_phy_ife) {
 14.2116 +		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
 14.2117 +		if (ret_val)
 14.2118 +			return ret_val;
 14.2119 +
 14.2120 +		reg_data &= ~IFE_PMC_AUTO_MDIX;
 14.2121 +
 14.2122 +		switch (hw->phy.mdix) {
 14.2123 +		case 1:
 14.2124 +			reg_data &= ~IFE_PMC_FORCE_MDIX;
 14.2125 +			break;
 14.2126 +		case 2:
 14.2127 +			reg_data |= IFE_PMC_FORCE_MDIX;
 14.2128 +			break;
 14.2129 +		case 0:
 14.2130 +		default:
 14.2131 +			reg_data |= IFE_PMC_AUTO_MDIX;
 14.2132 +			break;
 14.2133 +		}
 14.2134 +		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
 14.2135 +		if (ret_val)
 14.2136 +			return ret_val;
 14.2137 +	}
 14.2138 +	return e1000e_setup_copper_link(hw);
 14.2139 +}
 14.2140 +
 14.2141 +/**
 14.2142 + *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
 14.2143 + *  @hw: pointer to the HW structure
 14.2144 + *  @speed: pointer to store current link speed
 14.2145 + *  @duplex: pointer to store the current link duplex
 14.2146 + *
 14.2147 + *  Calls the generic get_speed_and_duplex to retrieve the current link
 14.2148 + *  information and then calls the Kumeran lock loss workaround for links at
 14.2149 + *  gigabit speeds.
 14.2150 + **/
 14.2151 +static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
 14.2152 +					  u16 *duplex)
 14.2153 +{
 14.2154 +	s32 ret_val;
 14.2155 +
 14.2156 +	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 14.2157 +	if (ret_val)
 14.2158 +		return ret_val;
 14.2159 +
 14.2160 +	if ((hw->mac.type == e1000_ich8lan) &&
 14.2161 +	    (hw->phy.type == e1000_phy_igp_3) &&
 14.2162 +	    (*speed == SPEED_1000)) {
 14.2163 +		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
 14.2164 +	}
 14.2165 +
 14.2166 +	return ret_val;
 14.2167 +}
 14.2168 +
 14.2169 +/**
 14.2170 + *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
 14.2171 + *  @hw: pointer to the HW structure
 14.2172 + *
 14.2173 + *  Work-around for 82566 Kumeran PCS lock loss:
 14.2174 + *  On link status change (i.e. PCI reset, speed change) and link is up and
 14.2175 + *  speed is gigabit-
 14.2176 + *    0) if workaround is optionally disabled do nothing
 14.2177 + *    1) wait 1ms for Kumeran link to come up
 14.2178 + *    2) check Kumeran Diagnostic register PCS lock loss bit
 14.2179 + *    3) if not set the link is locked (all is good), otherwise...
 14.2180 + *    4) reset the PHY
 14.2181 + *    5) repeat up to 10 times
 14.2182 + *  Note: this is only called for IGP3 copper when speed is 1gb.
 14.2183 + **/
 14.2184 +static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
 14.2185 +{
 14.2186 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 14.2187 +	u32 phy_ctrl;
 14.2188 +	s32 ret_val;
 14.2189 +	u16 i, data;
 14.2190 +	bool link;
 14.2191 +
 14.2192 +	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
 14.2193 +		return 0;
 14.2194 +
 14.2195 +	/*
 14.2196 +	 * Make sure link is up before proceeding.  If not just return.
 14.2197 +	 * Attempting this while link is negotiating fouled up link
 14.2198 +	 * stability
 14.2199 +	 */
 14.2200 +	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 14.2201 +	if (!link)
 14.2202 +		return 0;
 14.2203 +
 14.2204 +	for (i = 0; i < 10; i++) {
 14.2205 +		/* read once to clear */
 14.2206 +		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
 14.2207 +		if (ret_val)
 14.2208 +			return ret_val;
 14.2209 +		/* and again to get new status */
 14.2210 +		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
 14.2211 +		if (ret_val)
 14.2212 +			return ret_val;
 14.2213 +
 14.2214 +		/* check for PCS lock */
 14.2215 +		if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
 14.2216 +			return 0;
 14.2217 +
 14.2218 +		/* Issue PHY reset */
 14.2219 +		e1000_phy_hw_reset(hw);
 14.2220 +		mdelay(5);
 14.2221 +	}
 14.2222 +	/* Disable GigE link negotiation */
 14.2223 +	phy_ctrl = er32(PHY_CTRL);
 14.2224 +	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
 14.2225 +		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 14.2226 +	ew32(PHY_CTRL, phy_ctrl);
 14.2227 +
 14.2228 +	/*
 14.2229 +	 * Call gig speed drop workaround on Gig disable before accessing
 14.2230 +	 * any PHY registers
 14.2231 +	 */
 14.2232 +	e1000e_gig_downshift_workaround_ich8lan(hw);
 14.2233 +
 14.2234 +	/* unable to acquire PCS lock */
 14.2235 +	return -E1000_ERR_PHY;
 14.2236 +}
 14.2237 +
 14.2238 +/**
 14.2239 + *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
 14.2240 + *  @hw: pointer to the HW structure
 14.2241 + *  @state: boolean value used to set the current Kumeran workaround state
 14.2242 + *
 14.2243 + *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
 14.2244 + *  /disabled - FALSE).
 14.2245 + **/
 14.2246 +void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 14.2247 +						 bool state)
 14.2248 +{
 14.2249 +	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 14.2250 +
 14.2251 +	if (hw->mac.type != e1000_ich8lan) {
 14.2252 +		hw_dbg(hw, "Workaround applies to ICH8 only.\n");
 14.2253 +		return;
 14.2254 +	}
 14.2255 +
 14.2256 +	dev_spec->kmrn_lock_loss_workaround_enabled = state;
 14.2257 +}
 14.2258 +
 14.2259 +/**
 14.2260 + *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
 14.2261 + *  @hw: pointer to the HW structure
 14.2262 + *
 14.2263 + *  Workaround for 82566 power-down on D3 entry:
 14.2264 + *    1) disable gigabit link
 14.2265 + *    2) write VR power-down enable
 14.2266 + *    3) read it back
 14.2267 + *  Continue if successful, else issue LCD reset and repeat
 14.2268 + **/
 14.2269 +void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
 14.2270 +{
 14.2271 +	u32 reg;
 14.2272 +	u16 data;
 14.2273 +	u8  retry = 0;
 14.2274 +
 14.2275 +	if (hw->phy.type != e1000_phy_igp_3)
 14.2276 +		return;
 14.2277 +
 14.2278 +	/* Try the workaround twice (if needed) */
 14.2279 +	do {
 14.2280 +		/* Disable link */
 14.2281 +		reg = er32(PHY_CTRL);
 14.2282 +		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
 14.2283 +			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 14.2284 +		ew32(PHY_CTRL, reg);
 14.2285 +
 14.2286 +		/*
 14.2287 +		 * Call gig speed drop workaround on Gig disable before
 14.2288 +		 * accessing any PHY registers
 14.2289 +		 */
 14.2290 +		if (hw->mac.type == e1000_ich8lan)
 14.2291 +			e1000e_gig_downshift_workaround_ich8lan(hw);
 14.2292 +
 14.2293 +		/* Write VR power-down enable */
 14.2294 +		e1e_rphy(hw, IGP3_VR_CTRL, &data);
 14.2295 +		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
 14.2296 +		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
 14.2297 +
 14.2298 +		/* Read it back and test */
 14.2299 +		e1e_rphy(hw, IGP3_VR_CTRL, &data);
 14.2300 +		data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
 14.2301 +		if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
 14.2302 +			break;
 14.2303 +
 14.2304 +		/* Issue PHY reset and repeat at most one more time */
 14.2305 +		reg = er32(CTRL);
 14.2306 +		ew32(CTRL, reg | E1000_CTRL_PHY_RST);
 14.2307 +		retry++;
 14.2308 +	} while (retry);
 14.2309 +}
 14.2310 +
 14.2311 +/**
 14.2312 + *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
 14.2313 + *  @hw: pointer to the HW structure
 14.2314 + *
 14.2315 + *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
 14.2316 + *  LPLU, Gig disable, MDIC PHY reset):
 14.2317 + *    1) Set Kumeran Near-end loopback
 14.2318 + *    2) Clear Kumeran Near-end loopback
 14.2319 + *  Should only be called for ICH8[m] devices with IGP_3 Phy.
 14.2320 + **/
 14.2321 +void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 14.2322 +{
 14.2323 +	s32 ret_val;
 14.2324 +	u16 reg_data;
 14.2325 +
 14.2326 +	if ((hw->mac.type != e1000_ich8lan) ||
 14.2327 +	    (hw->phy.type != e1000_phy_igp_3))
 14.2328 +		return;
 14.2329 +
 14.2330 +	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
 14.2331 +				      &reg_data);
 14.2332 +	if (ret_val)
 14.2333 +		return;
 14.2334 +	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
 14.2335 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
 14.2336 +				       reg_data);
 14.2337 +	if (ret_val)
 14.2338 +		return;
 14.2339 +	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
 14.2340 +	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
 14.2341 +				       reg_data);
 14.2342 +}
 14.2343 +
 14.2344 +/**
 14.2345 + *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
 14.2346 + *  @hw: pointer to the HW structure
 14.2347 + *
 14.2348 + *  During S0 to Sx transition, it is possible the link remains at gig
 14.2349 + *  instead of negotiating to a lower speed.  Before going to Sx, set
 14.2350 + *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
 14.2351 + *  to a lower speed.
 14.2352 + *
 14.2353 + *  Should only be called for ICH9 and ICH10 devices.
 14.2354 + **/
 14.2355 +void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
 14.2356 +{
 14.2357 +	u32 phy_ctrl;
 14.2358 +
 14.2359 +	if ((hw->mac.type == e1000_ich10lan) ||
 14.2360 +	    (hw->mac.type == e1000_ich9lan)) {
 14.2361 +		phy_ctrl = er32(PHY_CTRL);
 14.2362 +		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
 14.2363 +		            E1000_PHY_CTRL_GBE_DISABLE;
 14.2364 +		ew32(PHY_CTRL, phy_ctrl);
 14.2365 +	}
 14.2366 +
 14.2367 +	return;
 14.2368 +}
 14.2369 +
 14.2370 +/**
 14.2371 + *  e1000_cleanup_led_ich8lan - Restore the default LED operation
 14.2372 + *  @hw: pointer to the HW structure
 14.2373 + *
 14.2374 + *  Return the LED back to the default configuration.
 14.2375 + **/
 14.2376 +static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
 14.2377 +{
 14.2378 +	if (hw->phy.type == e1000_phy_ife)
 14.2379 +		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
 14.2380 +
 14.2381 +	ew32(LEDCTL, hw->mac.ledctl_default);
 14.2382 +	return 0;
 14.2383 +}
 14.2384 +
 14.2385 +/**
 14.2386 + *  e1000_led_on_ich8lan - Turn LEDs on
 14.2387 + *  @hw: pointer to the HW structure
 14.2388 + *
 14.2389 + *  Turn on the LEDs.
 14.2390 + **/
 14.2391 +static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
 14.2392 +{
 14.2393 +	if (hw->phy.type == e1000_phy_ife)
 14.2394 +		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
 14.2395 +				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
 14.2396 +
 14.2397 +	ew32(LEDCTL, hw->mac.ledctl_mode2);
 14.2398 +	return 0;
 14.2399 +}
 14.2400 +
 14.2401 +/**
 14.2402 + *  e1000_led_off_ich8lan - Turn LEDs off
 14.2403 + *  @hw: pointer to the HW structure
 14.2404 + *
 14.2405 + *  Turn off the LEDs.
 14.2406 + **/
 14.2407 +static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
 14.2408 +{
 14.2409 +	if (hw->phy.type == e1000_phy_ife)
 14.2410 +		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
 14.2411 +			       (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
 14.2412 +
 14.2413 +	ew32(LEDCTL, hw->mac.ledctl_mode1);
 14.2414 +	return 0;
 14.2415 +}
 14.2416 +
 14.2417 +/**
 14.2418 + *  e1000_get_cfg_done_ich8lan - Read config done bit
 14.2419 + *  @hw: pointer to the HW structure
 14.2420 + *
 14.2421 + *  Read the management control register for the config done bit for
 14.2422 + *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
 14.2423 + *  to read the config done bit, so an error is *ONLY* logged and returns
 14.2424 + *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
 14.2425 + *  would not be able to be reset or change link.
 14.2426 + **/
 14.2427 +static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
 14.2428 +{
 14.2429 +	u32 bank = 0;
 14.2430 +
 14.2431 +	e1000e_get_cfg_done(hw);
 14.2432 +
 14.2433 +	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
 14.2434 +	if (hw->mac.type != e1000_ich10lan) {
 14.2435 +		if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
 14.2436 +		    (hw->phy.type == e1000_phy_igp_3)) {
 14.2437 +			e1000e_phy_init_script_igp3(hw);
 14.2438 +		}
 14.2439 +	} else {
 14.2440 +		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
 14.2441 +			/* Maybe we should do a basic PHY config */
 14.2442 +			hw_dbg(hw, "EEPROM not present\n");
 14.2443 +			return -E1000_ERR_CONFIG;
 14.2444 +		}
 14.2445 +	}
 14.2446 +
 14.2447 +	return 0;
 14.2448 +}
 14.2449 +
 14.2450 +/**
 14.2451 + *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
 14.2452 + *  @hw: pointer to the HW structure
 14.2453 + *
 14.2454 + *  Clears hardware counters specific to the silicon family and calls
 14.2455 + *  clear_hw_cntrs_generic to clear all general purpose counters.
 14.2456 + **/
 14.2457 +static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
 14.2458 +{
 14.2459 +	u32 temp;
 14.2460 +
 14.2461 +	e1000e_clear_hw_cntrs_base(hw);
 14.2462 +
 14.2463 +	temp = er32(ALGNERRC);
 14.2464 +	temp = er32(RXERRC);
 14.2465 +	temp = er32(TNCRS);
 14.2466 +	temp = er32(CEXTERR);
 14.2467 +	temp = er32(TSCTC);
 14.2468 +	temp = er32(TSCTFC);
 14.2469 +
 14.2470 +	temp = er32(MGTPRC);
 14.2471 +	temp = er32(MGTPDC);
 14.2472 +	temp = er32(MGTPTC);
 14.2473 +
 14.2474 +	temp = er32(IAC);
 14.2475 +	temp = er32(ICRXOC);
 14.2476 +
 14.2477 +}
 14.2478 +
 14.2479 +static struct e1000_mac_operations ich8_mac_ops = {
 14.2480 +	.check_mng_mode		= e1000_check_mng_mode_ich8lan,
 14.2481 +	.check_for_link		= e1000e_check_for_copper_link,
 14.2482 +	.cleanup_led		= e1000_cleanup_led_ich8lan,
 14.2483 +	.clear_hw_cntrs		= e1000_clear_hw_cntrs_ich8lan,
 14.2484 +	.get_bus_info		= e1000_get_bus_info_ich8lan,
 14.2485 +	.get_link_up_info	= e1000_get_link_up_info_ich8lan,
 14.2486 +	.led_on			= e1000_led_on_ich8lan,
 14.2487 +	.led_off		= e1000_led_off_ich8lan,
 14.2488 +	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
 14.2489 +	.reset_hw		= e1000_reset_hw_ich8lan,
 14.2490 +	.init_hw		= e1000_init_hw_ich8lan,
 14.2491 +	.setup_link		= e1000_setup_link_ich8lan,
 14.2492 +	.setup_physical_interface= e1000_setup_copper_link_ich8lan,
 14.2493 +};
 14.2494 +
 14.2495 +static struct e1000_phy_operations ich8_phy_ops = {
 14.2496 +	.acquire_phy		= e1000_acquire_swflag_ich8lan,
 14.2497 +	.check_reset_block	= e1000_check_reset_block_ich8lan,
 14.2498 +	.commit_phy		= NULL,
 14.2499 +	.force_speed_duplex	= e1000_phy_force_speed_duplex_ich8lan,
 14.2500 +	.get_cfg_done		= e1000_get_cfg_done_ich8lan,
 14.2501 +	.get_cable_length	= e1000e_get_cable_length_igp_2,
 14.2502 +	.get_phy_info		= e1000_get_phy_info_ich8lan,
 14.2503 +	.read_phy_reg		= e1000e_read_phy_reg_igp,
 14.2504 +	.release_phy		= e1000_release_swflag_ich8lan,
 14.2505 +	.reset_phy		= e1000_phy_hw_reset_ich8lan,
 14.2506 +	.set_d0_lplu_state	= e1000_set_d0_lplu_state_ich8lan,
 14.2507 +	.set_d3_lplu_state	= e1000_set_d3_lplu_state_ich8lan,
 14.2508 +	.write_phy_reg		= e1000e_write_phy_reg_igp,
 14.2509 +};
 14.2510 +
 14.2511 +static struct e1000_nvm_operations ich8_nvm_ops = {
 14.2512 +	.acquire_nvm		= e1000_acquire_swflag_ich8lan,
 14.2513 +	.read_nvm	 	= e1000_read_nvm_ich8lan,
 14.2514 +	.release_nvm		= e1000_release_swflag_ich8lan,
 14.2515 +	.update_nvm		= e1000_update_nvm_checksum_ich8lan,
 14.2516 +	.valid_led_default	= e1000_valid_led_default_ich8lan,
 14.2517 +	.validate_nvm		= e1000_validate_nvm_checksum_ich8lan,
 14.2518 +	.write_nvm		= e1000_write_nvm_ich8lan,
 14.2519 +};
 14.2520 +
 14.2521 +struct e1000_info e1000_ich8_info = {
 14.2522 +	.mac			= e1000_ich8lan,
 14.2523 +	.flags			= FLAG_HAS_WOL
 14.2524 +				  | FLAG_IS_ICH
 14.2525 +				  | FLAG_RX_CSUM_ENABLED
 14.2526 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
 14.2527 +				  | FLAG_HAS_AMT
 14.2528 +				  | FLAG_HAS_FLASH
 14.2529 +				  | FLAG_APME_IN_WUC,
 14.2530 +	.pba			= 8,
 14.2531 +	.get_variants		= e1000_get_variants_ich8lan,
 14.2532 +	.mac_ops		= &ich8_mac_ops,
 14.2533 +	.phy_ops		= &ich8_phy_ops,
 14.2534 +	.nvm_ops		= &ich8_nvm_ops,
 14.2535 +};
 14.2536 +
 14.2537 +struct e1000_info e1000_ich9_info = {
 14.2538 +	.mac			= e1000_ich9lan,
 14.2539 +	.flags			= FLAG_HAS_JUMBO_FRAMES
 14.2540 +				  | FLAG_IS_ICH
 14.2541 +				  | FLAG_HAS_WOL
 14.2542 +				  | FLAG_RX_CSUM_ENABLED
 14.2543 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
 14.2544 +				  | FLAG_HAS_AMT
 14.2545 +				  | FLAG_HAS_ERT
 14.2546 +				  | FLAG_HAS_FLASH
 14.2547 +				  | FLAG_APME_IN_WUC,
 14.2548 +	.pba			= 10,
 14.2549 +	.get_variants		= e1000_get_variants_ich8lan,
 14.2550 +	.mac_ops		= &ich8_mac_ops,
 14.2551 +	.phy_ops		= &ich8_phy_ops,
 14.2552 +	.nvm_ops		= &ich8_nvm_ops,
 14.2553 +};
 14.2554 +
 14.2555 +struct e1000_info e1000_ich10_info = {
 14.2556 +	.mac			= e1000_ich10lan,
 14.2557 +	.flags			= FLAG_HAS_JUMBO_FRAMES
 14.2558 +				  | FLAG_IS_ICH
 14.2559 +				  | FLAG_HAS_WOL
 14.2560 +				  | FLAG_RX_CSUM_ENABLED
 14.2561 +				  | FLAG_HAS_CTRLEXT_ON_LOAD
 14.2562 +				  | FLAG_HAS_AMT
 14.2563 +				  | FLAG_HAS_ERT
 14.2564 +				  | FLAG_HAS_FLASH
 14.2565 +				  | FLAG_APME_IN_WUC,
 14.2566 +	.pba			= 10,
 14.2567 +	.get_variants		= e1000_get_variants_ich8lan,
 14.2568 +	.mac_ops		= &ich8_mac_ops,
 14.2569 +	.phy_ops		= &ich8_phy_ops,
 14.2570 +	.nvm_ops		= &ich8_nvm_ops,
 14.2571 +};
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/drivers/net/e1000e/lib.c	Tue Feb 17 11:25:22 2009 +0000
    15.3 @@ -0,0 +1,2501 @@
    15.4 +/*******************************************************************************
    15.5 +
    15.6 +  Intel PRO/1000 Linux driver
    15.7 +  Copyright(c) 1999 - 2008 Intel Corporation.
    15.8 +
    15.9 +  This program is free software; you can redistribute it and/or modify it
   15.10 +  under the terms and conditions of the GNU General Public License,
   15.11 +  version 2, as published by the Free Software Foundation.
   15.12 +
   15.13 +  This program is distributed in the hope it will be useful, but WITHOUT
   15.14 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   15.15 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   15.16 +  more details.
   15.17 +
   15.18 +  You should have received a copy of the GNU General Public License along with
   15.19 +  this program; if not, write to the Free Software Foundation, Inc.,
   15.20 +  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   15.21 +
   15.22 +  The full GNU General Public License is included in this distribution in
   15.23 +  the file called "COPYING".
   15.24 +
   15.25 +  Contact Information:
   15.26 +  Linux NICS <linux.nics@intel.com>
   15.27