ia64/linux-2.6.18-xen.hg

view drivers/net/sfc/txc43128_phy.c @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents ad4d307bf9ce
children
line source
1 /****************************************************************************
2 * Driver for Solarflare network controllers
3 * (including support for SFE4001 10GBT NIC)
4 *
5 * Copyright 2006-2008: Solarflare Communications Inc,
6 * 9501 Jeronimo Road, Suite 250,
7 * Irvine, CA 92618, USA
8 *
9 * Developed by Solarflare Communications <linux-net-drivers@solarflare.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation, incorporated herein by reference.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ****************************************************************************
24 */
25 /*
26 * Driver for Transwitch/Mysticom CX4 retimer
27 * see www.transwitch.com, part is TXC-43128
28 */
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include "efx.h"
33 #include "debugfs.h"
34 #include "gmii.h"
35 #include "mdio_10g.h"
36 #include "xenpack.h"
37 #include "phy.h"
38 #include "lm87_support.h"
39 #include "falcon.h"
40 #include "workarounds.h"
42 /* We expect these MMDs to be in the package */
43 #define TXC_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PCS | \
44 MDIO_MMDREG_DEVS0_PMAPMD | \
45 MDIO_MMDREG_DEVS0_PHYXS)
47 #define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) | \
48 (1 << LOOPBACK_PMAPMD) | \
49 (1 << LOOPBACK_NETWORK))
51 /**************************************************************************
52 *
53 * Compile-time config
54 *
55 **************************************************************************
56 */
57 #define TXCNAME "TXC43128"
58 /* Total length of time we'll wait for the PHY to come out of reset */
59 #define TXC_MAX_RESET_TIME 500
60 /* Interval between checks */
61 #define TXC_RESET_WAIT 10
62 /* How long to run BIST: At 10Gbps 50 microseconds should be plenty to get
63 * some stats */
64 #define TXC_BIST_DURATION (50)
66 #define BER_INTERVAL (10 * efx_monitor_interval)
68 /**************************************************************************
69 *
70 * Register definitions
71 *
72 **************************************************************************
73 */
74 #define XAUI_NUM_LANES (4)
76 /*** Global register bank */
77 /* Silicon ID register */
78 #define TXC_GLRGS_SLID (0xc000)
79 #define TXC_GLRGS_SLID_MASK (0x1f)
81 /* Command register */
82 #define TXC_GLRGS_GLCMD (0xc004)
83 /* Useful bits in command register */
84 /* Lane power-down */
85 #define TXC_GLCMD_L01PD_LBN (5)
86 #define TXC_GLCMD_L23PD_LBN (6)
87 /* Limited SW reset: preserves configuration but
88 * initiates a logic reset. Self-clearing */
89 #define TXC_GLCMD_LMTSWRST_LBN (14)
91 /* Signal Quality Control */
92 #define TXC_GLRGS_GSGQLCTL (0xc01a)
93 /* Enable bit */
94 #define TXC_GSGQLCT_SGQLEN_LBN (15)
95 /* Lane selection */
96 #define TXC_GSGQLCT_LNSL_LBN (13)
97 #define TXC_GSGQLCT_LNSL_WIDTH (2)
99 /* Signal Quality Input */
100 #define TXC_GLRGS_GSGQLIN (0xc01b)
101 /* Signal Quality Grade */
102 #define TXC_GLRGS_GSGQLGRD (0xc01c)
103 /* Drift sign */
104 #define TXC_GSGQLGRD_DRFTSGN_LBN (15)
105 /* Grade valid flag */
106 #define TXC_GSGQLGRD_GRDVAL_LBN (14)
107 /* Remaining bits are the actual grade */
108 #define TXC_GSGQLGRD_GRADE_LBN (0)
109 #define TXC_GSGQLGRD_GRADE_WIDTH (14)
111 /* Signal Quality Drift: 16-bit drift value */
112 #define TXC_GLRGS_GSGQLDRFT (0xc01d)
114 /**** Analog register bank */
115 #define TXC_ALRGS_ATXCTL (0xc040)
116 /* Lane power-down */
117 #define TXC_ATXCTL_TXPD3_LBN (15)
118 #define TXC_ATXCTL_TXPD2_LBN (14)
119 #define TXC_ATXCTL_TXPD1_LBN (13)
120 #define TXC_ATXCTL_TXPD0_LBN (12)
122 /* Amplitude on lanes 0, 1 */
123 #define TXC_ALRGS_ATXAMP0 (0xc041)
124 /* Amplitude on lanes 2, 3 */
125 #define TXC_ALRGS_ATXAMP1 (0xc042)
126 /* Bit position of value for lane 0 (or 2) */
127 #define TXC_ATXAMP_LANE02_LBN (3)
128 /* Bit position of value for lane 1 (or 3) */
129 #define TXC_ATXAMP_LANE13_LBN (11)
131 #define TXC_ATXAMP_1280_mV (0)
132 #define TXC_ATXAMP_1200_mV (8)
133 #define TXC_ATXAMP_1120_mV (12)
134 #define TXC_ATXAMP_1060_mV (14)
135 #define TXC_ATXAMP_0820_mV (25)
136 #define TXC_ATXAMP_0720_mV (26)
137 #define TXC_ATXAMP_0580_mV (27)
138 #define TXC_ATXAMP_0440_mV (28)
140 #define TXC_ATXAMP_0820_BOTH \
141 ((TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) \
142 | (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN))
144 #define TXC_ATXAMP_DEFAULT (0x6060) /* From databook */
146 /* Preemphasis on lanes 0, 1 */
147 #define TXC_ALRGS_ATXPRE0 (0xc043)
148 /* Preemphasis on lanes 2, 3 */
149 #define TXC_ALRGS_ATXPRE1 (0xc044)
151 #define TXC_ATXPRE_NONE (0)
152 #define TXC_ATXPRE_DEFAULT (0x1010) /* From databook */
154 #define TXC_ALRGS_ARXCTL (0xc045)
155 /* Lane power-down */
156 #define TXC_ARXCTL_RXPD3_LBN (15)
157 #define TXC_ARXCTL_RXPD2_LBN (14)
158 #define TXC_ARXCTL_RXPD1_LBN (13)
159 #define TXC_ARXCTL_RXPD0_LBN (12)
161 /*** receiver control registers: Bit Error Rate measurement */
162 /* Per lane BER timers */
163 #define TXC_RXCTL_BERTMR0 (0xc0d4)
164 #define TXC_RXCTL_BERTMR1 (0xc154)
165 #define TXC_RXCTL_BERTMR2 (0xc1d4)
166 #define TXC_RXCTL_BERTMR3 (0xc254)
167 /* Per lane BER counters */
168 #define TXC_RXCTL_BERCNT0 (0xc0d5)
169 #define TXC_RXCTL_BERCNT1 (0xc155)
170 #define TXC_RXCTL_BERCNT2 (0xc1d5)
171 #define TXC_RXCTL_BERCNT3 (0xc255)
173 #define BER_REG_SPACING (TXC_RXCTL_BERTMR1 - TXC_RXCTL_BERTMR0)
175 /*** Main user-defined register set */
176 /* Main control */
177 #define TXC_MRGS_CTL (0xc340)
178 /* Bits in main control */
179 #define TXC_MCTL_RESET_LBN (15) /* Self clear */
180 #define TXC_MCTL_TXLED_LBN (14) /* 1 to show align status */
181 #define TXC_MCTL_RXLED_LBN (13) /* 1 to show align status */
183 /* GPIO output */
184 #define TXC_GPIO_OUTPUT (0xc346)
185 #define TXC_GPIO_DIR (0xc348)
187 /*** Vendor-specific BIST registers */
188 #define TXC_BIST_CTL (0xc280)
189 #define TXC_BIST_TXFRMCNT (0xc281)
190 #define TXC_BIST_RX0FRMCNT (0xc282)
191 #define TXC_BIST_RX1FRMCNT (0xc283)
192 #define TXC_BIST_RX2FRMCNT (0xc284)
193 #define TXC_BIST_RX3FRMCNT (0xc285)
194 #define TXC_BIST_RX0ERRCNT (0xc286)
195 #define TXC_BIST_RX1ERRCNT (0xc287)
196 #define TXC_BIST_RX2ERRCNT (0xc288)
197 #define TXC_BIST_RX3ERRCNT (0xc289)
199 /*** BIST control bits */
200 /* BIST type (controls bit patter in test) */
201 #define TXC_BIST_CTRL_TYPE_LBN (10)
202 #define TXC_BIST_CTRL_TYPE_TSD (0) /* TranSwitch Deterministic */
203 #define TXC_BIST_CTRL_TYPE_CRP (1) /* CRPAT standard */
204 #define TXC_BIST_CTRL_TYPE_CJP (2) /* CJPAT standard */
205 #define TXC_BIST_CTRL_TYPE_TSR (3) /* TranSwitch pseudo-random */
206 /* Set this to 1 for 10 bit and 0 for 8 bit */
207 #define TXC_BIST_CTRL_B10EN_LBN (12)
208 /* Enable BIST (write 0 to disable) */
209 #define TXC_BIST_CTRL_ENAB_LBN (13)
210 /*Stop BIST (self-clears when stop complete) */
211 #define TXC_BIST_CTRL_STOP_LBN (14)
212 /* Start BIST (cleared by writing 1 to STOP) */
213 #define TXC_BIST_CTRL_STRT_LBN (15)
215 /* Mt. Diablo test configuration */
216 #define TXC_MTDIABLO_CTRL (0xc34f)
217 #define TXC_MTDIABLO_CTRL_PMA_LOOP_LBN (10)
219 struct txc43128_data {
220 #ifdef CONFIG_SFC_DEBUGFS
221 /* BER stats update from check_hw. Note that this is in errors/second,
222 * converting it to errors/bit is left as an exercise for user-space.
223 */
224 unsigned phy_ber_pcs[4];
225 unsigned phy_ber_phyxs[4];
226 #endif
227 unsigned bug10934_timer;
228 int phy_powered;
229 int tx_disabled;
230 enum efx_loopback_mode loopback_mode;
231 };
233 /* Perform the bug 10934 workaround every 5s */
234 #define BUG10934_RESET_INTERVAL (5 * HZ)
237 /* Perform a reset that doesn't clear configuration changes */
238 static void txc_reset_logic(struct efx_nic *efx);
240 /* Set the output value of a gpio */
241 void txc_set_gpio_val(struct efx_nic *efx, int pin, int on)
242 {
243 int outputs;
245 outputs = mdio_clause45_read(efx, efx->mii.phy_id,
246 MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT);
248 outputs = (outputs & ~(1 << pin)) | (on << pin);
250 mdio_clause45_write(efx, efx->mii.phy_id,
251 MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT,
252 outputs);
253 }
255 /* Set up the GPIO direction register */
256 void txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir)
257 {
258 int dirs;
260 if (efx->board_info.minor < 3 &&
261 efx->board_info.major == 0)
262 return;
264 dirs = mdio_clause45_read(efx, efx->mii.phy_id,
265 MDIO_MMD_PHYXS, TXC_GPIO_DIR);
266 dirs = (dir & ~(1 << pin)) | (dir << pin);
267 mdio_clause45_write(efx, efx->mii.phy_id,
268 MDIO_MMD_PHYXS, TXC_GPIO_DIR, dirs);
270 }
272 /* Reset the PMA/PMD MMD. The documentation is explicit that this does a
273 * global reset (it's less clear what reset of other MMDs does).*/
274 static int txc_reset_phy(struct efx_nic *efx)
275 {
276 int rc = mdio_clause45_reset_mmd(efx, MDIO_MMD_PMAPMD,
277 TXC_MAX_RESET_TIME / TXC_RESET_WAIT,
278 TXC_RESET_WAIT);
279 if (rc < 0)
280 goto fail;
282 /* Check that all the MMDs we expect are present and responding. We
283 * expect faults on some if the link is down, but not on the PHY XS */
284 rc = mdio_clause45_check_mmds(efx, TXC_REQUIRED_DEVS, 0);
285 if (rc < 0)
286 goto fail;
288 return 0;
290 fail:
291 EFX_ERR(efx, TXCNAME ": reset timed out!\n");
292 return rc;
293 }
295 /* Run a single BIST on one MMD*/
296 static int txc_bist_one(struct efx_nic *efx, int mmd, int test)
297 {
298 int phy = efx->mii.phy_id;
299 int ctrl, bctl;
300 int lane;
301 int rc = 0;
303 EFX_INFO(efx, "" TXCNAME ": running BIST on %s MMD\n",
304 mdio_clause45_mmd_name(mmd));
306 /* Set PMA to test into loopback using Mt Diablo reg as per app note */
307 ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
308 TXC_MTDIABLO_CTRL);
309 ctrl |= (1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
310 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
311 TXC_MTDIABLO_CTRL, ctrl);
314 /* The BIST app. note lists these as 3 distinct steps. */
315 /* Set the BIST type */
316 bctl = (test << TXC_BIST_CTRL_TYPE_LBN);
317 mdio_clause45_write(efx, phy, mmd, TXC_BIST_CTL, bctl);
319 /* Set the BSTEN bit in the BIST Control register to enable */
320 bctl |= (1 << TXC_BIST_CTRL_ENAB_LBN);
321 mdio_clause45_write(efx, phy, mmd, TXC_BIST_CTL, bctl);
323 /* Set the BSTRT bit in the BIST Control register */
324 mdio_clause45_write(efx, phy, mmd, TXC_BIST_CTL, bctl |
325 (1 << TXC_BIST_CTRL_STRT_LBN));
327 /* Wait. */
328 udelay(TXC_BIST_DURATION);
330 /* Set the BSTOP bit in the BIST Control register */
331 bctl |= (1 << TXC_BIST_CTRL_STOP_LBN);
332 mdio_clause45_write(efx, phy, mmd, TXC_BIST_CTL, bctl);
334 /* The STOP bit should go off when things have stopped */
335 while (bctl & (1 << TXC_BIST_CTRL_STOP_LBN))
336 bctl = mdio_clause45_read(efx, phy, mmd, TXC_BIST_CTL);
338 /* Check all the error counts are 0 and all the frame counts are
339 non-zero */
340 for (lane = 0; lane < 4; lane++) {
341 int count = mdio_clause45_read(efx, phy, mmd,
342 TXC_BIST_RX0ERRCNT + lane);
343 if (count != 0) {
344 EFX_ERR(efx, ""TXCNAME": BIST error. "
345 "Lane %d had %d errs\n", lane, count);
346 rc = -EIO;
347 }
348 count = mdio_clause45_read(efx, phy, mmd,
349 TXC_BIST_RX0FRMCNT + lane);
350 if (count == 0) {
351 EFX_ERR(efx, ""TXCNAME": BIST error. "
352 "Lane %d got 0 frames\n", lane);
353 rc = -EIO;
354 }
355 }
357 if (rc == 0)
358 EFX_INFO(efx, ""TXCNAME": BIST pass\n");
360 /* Disable BIST */
361 mdio_clause45_write(efx, phy, mmd, TXC_BIST_CTL, 0);
363 /* Turn off loopback */
364 ctrl &= ~(1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
365 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
366 TXC_MTDIABLO_CTRL, ctrl);
368 return rc;
369 }
371 /* Run all the desired BIST tests for the PHY */
372 static int txc_bist(struct efx_nic *efx)
373 {
374 int rc;
375 /*!\todo: experiment with running more of the BIST patterns to
376 * see if it actually shows up more problems. */
377 rc = txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD);
378 return rc;
379 }
381 #ifdef CONFIG_SFC_DEBUGFS
383 /* debugfs entries for this PHY */
384 static struct efx_debugfs_parameter debug_entries[] = {
385 EFX_PER_LANE_PARAMETER("phy_ber_lane", "_pcs",
386 struct txc43128_data, phy_ber_pcs,
387 unsigned, efx_debugfs_read_uint),
388 EFX_PER_LANE_PARAMETER("phy_ber_lane", "_phyxs",
389 struct txc43128_data, phy_ber_phyxs,
390 unsigned, efx_debugfs_read_uint),
391 EFX_INT_PARAMETER(struct txc43128_data, phy_powered),
392 {NULL}
393 };
395 #endif /* CONFIG_SFC_DEBUGFS */
397 /* Push the non-configurable defaults into the PHY. This must be
398 * done after every full reset */
399 static void txc_apply_defaults(struct efx_nic *efx)
400 {
401 int mctrl;
403 /* Turn amplitude down and preemphasis off on the host side
404 * (PHY<->MAC) as this is believed less likely to upset Falcon
405 * and no adverse effects have been noted. It probably also
406 * saves a picowatt or two */
408 /* Turn off preemphasis */
409 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PHYXS,
410 TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE);
411 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PHYXS,
412 TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE);
414 /* Turn down the amplitude */
415 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PHYXS,
416 TXC_ALRGS_ATXAMP0, TXC_ATXAMP_0820_BOTH);
417 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PHYXS,
418 TXC_ALRGS_ATXAMP1, TXC_ATXAMP_0820_BOTH);
420 /* Set the line side amplitude and preemphasis to the databook
421 * defaults as an erratum causes them to be 0 on at least some
422 * PHY rev.s */
423 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
424 TXC_ALRGS_ATXPRE0, TXC_ATXPRE_DEFAULT);
425 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
426 TXC_ALRGS_ATXPRE1, TXC_ATXPRE_DEFAULT);
427 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
428 TXC_ALRGS_ATXAMP0, TXC_ATXAMP_DEFAULT);
429 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
430 TXC_ALRGS_ATXAMP1, TXC_ATXAMP_DEFAULT);
432 /* Set up the LEDs */
433 mctrl = mdio_clause45_read(efx, efx->mii.phy_id,
434 MDIO_MMD_PHYXS, TXC_MRGS_CTL);
436 /* Set the Green and Red LEDs to their default modes */
437 mctrl &= ~((1 << TXC_MCTL_TXLED_LBN) | (1 << TXC_MCTL_RXLED_LBN));
438 mdio_clause45_write(efx, efx->mii.phy_id,
439 MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl);
441 /* Databook recommends doing this after configuration changes */
442 txc_reset_logic(efx);
444 efx->board_info.init_leds(efx);
445 }
447 /* Initialisation entry point for this PHY driver */
448 static int txc43128_phy_init(struct efx_nic *efx)
449 {
450 u32 devid;
451 int rc = 0;
452 struct txc43128_data *phy_data;
454 devid = mdio_clause45_read_id(efx, MDIO_MMD_PHYXS);
456 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
457 efx->phy_data = phy_data;
459 /* This is the default after reset */
460 phy_data->phy_powered = efx->phy_powered;
461 phy_data->tx_disabled = efx->tx_disabled;
463 #ifdef CONFIG_SFC_DEBUGFS
464 rc = efx_extend_debugfs_port(efx, phy_data, debug_entries);
465 if (rc < 0)
466 goto fail1;
467 #endif
468 EFX_INFO(efx, ""TXCNAME ": PHY ID reg %x (OUI %x model %x "
469 "revision %x)\n", devid, MDIO_ID_OUI(devid),
470 MDIO_ID_MODEL(devid), MDIO_ID_REV(devid));
472 EFX_INFO(efx, ""TXCNAME ": Silicon ID %x\n",
473 mdio_clause45_read(efx, efx->mii.phy_id,
474 MDIO_MMD_PHYXS, TXC_GLRGS_SLID) &
475 TXC_GLRGS_SLID_MASK);
477 rc = txc_reset_phy(efx);
478 if (rc < 0)
479 goto fail2;
481 rc = txc_bist(efx);
482 if (rc < 0)
483 goto fail2;
485 txc_apply_defaults(efx);
487 return 0;
489 fail2:
490 #ifdef CONFIG_SFC_DEBUGFS
491 efx_trim_debugfs_port(efx, debug_entries);
492 /* fall-thru */
493 fail1:
494 #endif
495 kfree(efx->phy_data);
496 efx->phy_data = NULL;
497 return rc;
498 }
500 /* Set the lane power down state in the global registers */
501 static void txc_glrgs_lane_power(struct efx_nic *efx, int mmd)
502 {
503 int pd = (1 << TXC_GLCMD_L01PD_LBN) | (1 << TXC_GLCMD_L23PD_LBN);
504 int ctl = mdio_clause45_read(efx, efx->mii.phy_id,
505 mmd, TXC_GLRGS_GLCMD);
507 if (efx->phy_powered)
508 ctl &= ~pd;
509 else
510 ctl |= pd;
512 mdio_clause45_write(efx, efx->mii.phy_id,
513 mmd, TXC_GLRGS_GLCMD, ctl);
514 }
516 /* Set the lane power down state in the analog control registers */
517 static void txc_analog_lane_power(struct efx_nic *efx, int mmd)
518 {
519 int txpd = (1 << TXC_ATXCTL_TXPD3_LBN) | (1 << TXC_ATXCTL_TXPD2_LBN)
520 | (1 << TXC_ATXCTL_TXPD1_LBN) | (1 << TXC_ATXCTL_TXPD0_LBN);
522 int rxpd = (1 << TXC_ATXCTL_TXPD3_LBN) | (1 << TXC_ATXCTL_TXPD2_LBN)
523 | (1 << TXC_ATXCTL_TXPD1_LBN) | (1 << TXC_ATXCTL_TXPD0_LBN);
525 int txctl = mdio_clause45_read(efx, efx->mii.phy_id,
526 mmd, TXC_ALRGS_ATXCTL);
527 int rxctl = mdio_clause45_read(efx, efx->mii.phy_id,
528 mmd, TXC_ALRGS_ARXCTL);
530 if (efx->phy_powered) {
531 txctl &= ~txpd;
532 rxctl &= ~rxpd;
533 } else {
534 txctl |= txpd;
535 rxctl |= rxpd;
536 }
538 mdio_clause45_write(efx, efx->mii.phy_id,
539 mmd, TXC_ALRGS_ATXCTL, txctl);
540 mdio_clause45_write(efx, efx->mii.phy_id,
541 mmd, TXC_ALRGS_ARXCTL, rxctl);
542 }
544 static void txc_set_power(struct efx_nic *efx)
545 {
546 /* According to the data book, all the MMDs can do low power */
547 mdio_clause45_set_mmds_lpower(efx, !efx->phy_powered,
548 TXC_REQUIRED_DEVS);
550 /* Global register bank is in PCS, PHY XS. These control the host
551 * side and line side settings respectively. */
552 txc_glrgs_lane_power(efx, MDIO_MMD_PCS);
553 txc_glrgs_lane_power(efx, MDIO_MMD_PHYXS);
555 /* Analog register bank in PMA/PMD, PHY XS */
556 txc_analog_lane_power(efx, MDIO_MMD_PMAPMD);
557 txc_analog_lane_power(efx, MDIO_MMD_PHYXS);
558 }
561 static void txc_reset_logic_mmd(struct efx_nic *efx, int mmd)
562 {
563 int portid = efx->mii.phy_id;
564 int val = mdio_clause45_read(efx, portid, mmd, TXC_GLRGS_GLCMD);
565 int tries = 50;
566 val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
567 mdio_clause45_write(efx, portid, mmd, TXC_GLRGS_GLCMD, val);
568 while (tries--) {
569 val = mdio_clause45_read(efx, portid, mmd,
570 TXC_GLRGS_GLCMD);
571 if (!(val & (1 << TXC_GLCMD_LMTSWRST_LBN)))
572 break;
573 udelay(1);
574 }
575 if (!tries)
576 EFX_INFO(efx, TXCNAME " Logic reset timed out!\n");
577 }
580 /* Perform a logic reset. This preserves the configuration registers
581 * and is needed for some configuration changes to take effect */
582 static void txc_reset_logic(struct efx_nic *efx)
583 {
584 /* The data sheet claims we can do the logic reset on either the
585 * PCS or the PHYXS and the result is a reset of both host- and
586 * line-side logic. */
587 txc_reset_logic_mmd(efx, MDIO_MMD_PCS);
588 }
590 static int txc43128_phy_read_link(struct efx_nic *efx)
591 {
592 return mdio_clause45_links_ok(efx, TXC_REQUIRED_DEVS);
593 }
595 static void txc43128_phy_reconfigure(struct efx_nic *efx)
596 {
597 struct txc43128_data *phy_data = efx->phy_data;
598 int power_change = (efx->phy_powered != phy_data->phy_powered);
599 int loop_change = LOOPBACK_CHANGED(phy_data, efx, TXC_LOOPBACKS);
600 int disable_change = (efx->tx_disabled != phy_data->tx_disabled);
602 if (!phy_data->tx_disabled && efx->tx_disabled) {
603 txc_reset_phy(efx);
604 txc_apply_defaults(efx);
605 falcon_reset_xaui(efx);
606 disable_change = 0;
607 }
609 mdio_clause45_transmit_disable(efx, efx->tx_disabled);
610 mdio_clause45_phy_reconfigure(efx);
611 if (power_change)
612 txc_set_power(efx);
614 /* The data sheet claims this is required after every reconfiguration
615 * (note at end of 7.1), but we mustn't do it when nothing changes as
616 * it glitches the link, and reconfigure gets called on link change,
617 * so we get an IRQ storm on link up. */
618 if (loop_change || power_change || disable_change)
619 txc_reset_logic(efx);
621 phy_data->phy_powered = efx->phy_powered;
622 phy_data->loopback_mode = efx->loopback_mode;
623 phy_data->tx_disabled = efx->tx_disabled;
624 efx->link_up = txc43128_phy_read_link(efx);
625 efx->link_options = GM_LPA_10000FULL;
626 }
628 static void txc43128_phy_fini(struct efx_nic *efx)
629 {
630 efx->board_info.blink(efx, 0);
632 /* Disable link events */
633 xenpack_disable_lasi_irqs(efx);
635 #ifdef CONFIG_SFC_DEBUGFS
636 /* Remove the extra debug entries and free data */
637 efx_trim_debugfs_port(efx, debug_entries);
638 #endif
639 kfree(efx->phy_data);
640 efx->phy_data = NULL;
641 }
643 /* Periodic callback: this exists mainly to poll link status as we currently
644 * don't use LASI interrupts. Also update the BER counters and poll the lm87 */
645 static int txc43128_phy_check_hw(struct efx_nic *efx)
646 {
647 struct txc43128_data *data = efx->phy_data;
648 #ifdef CONFIG_SFC_DEBUGFS
649 int phy = efx->mii.phy_id;
650 int timer, count, i, mmd;
651 #endif
652 int rc = 0;
653 int link_up = txc43128_phy_read_link(efx);
655 /* Simulate a PHY event if link state has changed */
656 if (link_up != efx->link_up)
657 efx->mac_op->fake_phy_event(efx);
658 else if (EFX_WORKAROUND_10934(efx)) {
659 if (link_up || (efx->loopback_mode != LOOPBACK_NONE))
660 data->bug10934_timer = jiffies;
661 else {
662 int delta = jiffies - data->bug10934_timer;
663 if (delta >= BUG10934_RESET_INTERVAL) {
664 data->bug10934_timer = jiffies;
665 txc_reset_logic(efx);
666 }
667 }
668 }
670 rc = efx->board_info.monitor(efx);
671 if (rc) {
672 EFX_ERR(efx, "" TXCNAME
673 ": sensor alert! Putting PHY into low power.\n");
674 efx->phy_powered = 0;
675 txc_set_power(efx);
676 }
678 #ifdef CONFIG_SFC_DEBUGFS
679 /* There are 2 MMDs with RX BER counters: PCS and PHY XS,
680 * which happen to be consecutively numbered */
681 for (mmd = MDIO_MMD_PCS; mmd <= MDIO_MMD_PHYXS; mmd++) {
682 for (i = 0; i < XAUI_NUM_LANES; i++) {
683 timer = mdio_clause45_read(efx, phy, mmd,
684 TXC_RXCTL_BERTMR0 +
685 i * BER_REG_SPACING);
686 count = mdio_clause45_read(efx, phy, mmd,
687 TXC_RXCTL_BERCNT0 +
688 i * BER_REG_SPACING);
689 /* The BER timer counts down in seconds. If it would
690 * expire before the next check_hw, update the stats &
691 * restart the timer (clears the count) */
692 if (timer * HZ < efx_monitor_interval) {
693 /* Record count, allowing for the fact that the
694 * timer may not have reached zero */
695 unsigned ber = (count * BER_INTERVAL) /
696 (BER_INTERVAL - timer * HZ);
697 if (mmd == MDIO_MMD_PCS)
698 data->phy_ber_pcs[i] = ber;
699 else
700 data->phy_ber_phyxs[i] = ber;
701 /* Reprogram the timer */
702 mdio_clause45_write(efx, phy, mmd,
703 TXC_RXCTL_BERTMR0 +
704 i * BER_REG_SPACING,
705 BER_INTERVAL / HZ);
706 }
707 }
708 mmd = (mmd == MDIO_MMD_PCS) ? MDIO_MMD_PHYXS : 0;
709 }
710 #endif /* CONFIG_SFC_DEBUGFS */
711 return rc;
712 }
714 struct efx_phy_operations falcon_txc_phy_ops = {
715 .init = txc43128_phy_init,
716 .reconfigure = txc43128_phy_reconfigure,
717 .check_hw = txc43128_phy_check_hw,
718 .fini = txc43128_phy_fini,
719 .clear_interrupt = efx_port_dummy_op_void,
720 .reset_xaui = efx_port_dummy_op_void,
721 .mmds = TXC_REQUIRED_DEVS,
722 .loopbacks = TXC_LOOPBACKS,
723 .startup_loopback = LOOPBACK_PMAPMD,
724 };