ia64/linux-2.6.18-xen.hg

view drivers/net/s2io.h @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
line source
1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13 #ifndef _S2IO_H
14 #define _S2IO_H
16 #define TBD 0
17 #define BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19 #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
21 #ifndef BOOL
22 #define BOOL int
23 #endif
25 #ifndef TRUE
26 #define TRUE 1
27 #define FALSE 0
28 #endif
30 #undef SUCCESS
31 #define SUCCESS 0
32 #define FAILURE -1
34 #define CHECKBIT(value, nbit) (value & (1 << nbit))
36 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
37 #define MAX_FLICKER_TIME 60000 /* 60 Secs */
39 /* Maximum outstanding splits to be configured into xena. */
40 typedef enum xena_max_outstanding_splits {
41 XENA_ONE_SPLIT_TRANSACTION = 0,
42 XENA_TWO_SPLIT_TRANSACTION = 1,
43 XENA_THREE_SPLIT_TRANSACTION = 2,
44 XENA_FOUR_SPLIT_TRANSACTION = 3,
45 XENA_EIGHT_SPLIT_TRANSACTION = 4,
46 XENA_TWELVE_SPLIT_TRANSACTION = 5,
47 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
48 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
49 } xena_max_outstanding_splits;
50 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
52 /* OS concerned variables and constants */
53 #define WATCH_DOG_TIMEOUT 15*HZ
54 #define EFILL 0x1234
55 #define ALIGN_SIZE 127
56 #define PCIX_COMMAND_REGISTER 0x62
58 /*
59 * Debug related variables.
60 */
61 /* different debug levels. */
62 #define ERR_DBG 0
63 #define INIT_DBG 1
64 #define INFO_DBG 2
65 #define TX_DBG 3
66 #define INTR_DBG 4
68 /* Global variable that defines the present debug level of the driver. */
69 static int debug_level = ERR_DBG;
71 /* DEBUG message print. */
72 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
74 /* Protocol assist features of the NIC */
75 #define L3_CKSUM_OK 0xFFFF
76 #define L4_CKSUM_OK 0xFFFF
77 #define S2IO_JUMBO_SIZE 9600
79 /* Driver statistics maintained by driver */
80 typedef struct {
81 unsigned long long single_ecc_errs;
82 unsigned long long double_ecc_errs;
83 unsigned long long parity_err_cnt;
84 unsigned long long serious_err_cnt;
85 unsigned long long soft_reset_cnt;
86 unsigned long long fifo_full_cnt;
87 unsigned long long ring_full_cnt;
88 /* LRO statistics */
89 unsigned long long clubbed_frms_cnt;
90 unsigned long long sending_both;
91 unsigned long long outof_sequence_pkts;
92 unsigned long long flush_max_pkts;
93 unsigned long long sum_avg_pkts_aggregated;
94 unsigned long long num_aggregations;
95 } swStat_t;
97 /* Xpak releated alarm and warnings */
98 typedef struct {
99 u64 alarm_transceiver_temp_high;
100 u64 alarm_transceiver_temp_low;
101 u64 alarm_laser_bias_current_high;
102 u64 alarm_laser_bias_current_low;
103 u64 alarm_laser_output_power_high;
104 u64 alarm_laser_output_power_low;
105 u64 warn_transceiver_temp_high;
106 u64 warn_transceiver_temp_low;
107 u64 warn_laser_bias_current_high;
108 u64 warn_laser_bias_current_low;
109 u64 warn_laser_output_power_high;
110 u64 warn_laser_output_power_low;
111 u64 xpak_regs_stat;
112 u32 xpak_timer_count;
113 } xpakStat_t;
116 /* The statistics block of Xena */
117 typedef struct stat_block {
118 /* Tx MAC statistics counters. */
119 u32 tmac_data_octets;
120 u32 tmac_frms;
121 u64 tmac_drop_frms;
122 u32 tmac_bcst_frms;
123 u32 tmac_mcst_frms;
124 u64 tmac_pause_ctrl_frms;
125 u32 tmac_ucst_frms;
126 u32 tmac_ttl_octets;
127 u32 tmac_any_err_frms;
128 u32 tmac_nucst_frms;
129 u64 tmac_ttl_less_fb_octets;
130 u64 tmac_vld_ip_octets;
131 u32 tmac_drop_ip;
132 u32 tmac_vld_ip;
133 u32 tmac_rst_tcp;
134 u32 tmac_icmp;
135 u64 tmac_tcp;
136 u32 reserved_0;
137 u32 tmac_udp;
139 /* Rx MAC Statistics counters. */
140 u32 rmac_data_octets;
141 u32 rmac_vld_frms;
142 u64 rmac_fcs_err_frms;
143 u64 rmac_drop_frms;
144 u32 rmac_vld_bcst_frms;
145 u32 rmac_vld_mcst_frms;
146 u32 rmac_out_rng_len_err_frms;
147 u32 rmac_in_rng_len_err_frms;
148 u64 rmac_long_frms;
149 u64 rmac_pause_ctrl_frms;
150 u64 rmac_unsup_ctrl_frms;
151 u32 rmac_accepted_ucst_frms;
152 u32 rmac_ttl_octets;
153 u32 rmac_discarded_frms;
154 u32 rmac_accepted_nucst_frms;
155 u32 reserved_1;
156 u32 rmac_drop_events;
157 u64 rmac_ttl_less_fb_octets;
158 u64 rmac_ttl_frms;
159 u64 reserved_2;
160 u32 rmac_usized_frms;
161 u32 reserved_3;
162 u32 rmac_frag_frms;
163 u32 rmac_osized_frms;
164 u32 reserved_4;
165 u32 rmac_jabber_frms;
166 u64 rmac_ttl_64_frms;
167 u64 rmac_ttl_65_127_frms;
168 u64 reserved_5;
169 u64 rmac_ttl_128_255_frms;
170 u64 rmac_ttl_256_511_frms;
171 u64 reserved_6;
172 u64 rmac_ttl_512_1023_frms;
173 u64 rmac_ttl_1024_1518_frms;
174 u32 rmac_ip;
175 u32 reserved_7;
176 u64 rmac_ip_octets;
177 u32 rmac_drop_ip;
178 u32 rmac_hdr_err_ip;
179 u32 reserved_8;
180 u32 rmac_icmp;
181 u64 rmac_tcp;
182 u32 rmac_err_drp_udp;
183 u32 rmac_udp;
184 u64 rmac_xgmii_err_sym;
185 u64 rmac_frms_q0;
186 u64 rmac_frms_q1;
187 u64 rmac_frms_q2;
188 u64 rmac_frms_q3;
189 u64 rmac_frms_q4;
190 u64 rmac_frms_q5;
191 u64 rmac_frms_q6;
192 u64 rmac_frms_q7;
193 u16 rmac_full_q3;
194 u16 rmac_full_q2;
195 u16 rmac_full_q1;
196 u16 rmac_full_q0;
197 u16 rmac_full_q7;
198 u16 rmac_full_q6;
199 u16 rmac_full_q5;
200 u16 rmac_full_q4;
201 u32 reserved_9;
202 u32 rmac_pause_cnt;
203 u64 rmac_xgmii_data_err_cnt;
204 u64 rmac_xgmii_ctrl_err_cnt;
205 u32 rmac_err_tcp;
206 u32 rmac_accepted_ip;
208 /* PCI/PCI-X Read transaction statistics. */
209 u32 new_rd_req_cnt;
210 u32 rd_req_cnt;
211 u32 rd_rtry_cnt;
212 u32 new_rd_req_rtry_cnt;
214 /* PCI/PCI-X Write/Read transaction statistics. */
215 u32 wr_req_cnt;
216 u32 wr_rtry_rd_ack_cnt;
217 u32 new_wr_req_rtry_cnt;
218 u32 new_wr_req_cnt;
219 u32 wr_disc_cnt;
220 u32 wr_rtry_cnt;
222 /* PCI/PCI-X Write / DMA Transaction statistics. */
223 u32 txp_wr_cnt;
224 u32 rd_rtry_wr_ack_cnt;
225 u32 txd_wr_cnt;
226 u32 txd_rd_cnt;
227 u32 rxd_wr_cnt;
228 u32 rxd_rd_cnt;
229 u32 rxf_wr_cnt;
230 u32 txf_rd_cnt;
232 /* Tx MAC statistics overflow counters. */
233 u32 tmac_data_octets_oflow;
234 u32 tmac_frms_oflow;
235 u32 tmac_bcst_frms_oflow;
236 u32 tmac_mcst_frms_oflow;
237 u32 tmac_ucst_frms_oflow;
238 u32 tmac_ttl_octets_oflow;
239 u32 tmac_any_err_frms_oflow;
240 u32 tmac_nucst_frms_oflow;
241 u64 tmac_vlan_frms;
242 u32 tmac_drop_ip_oflow;
243 u32 tmac_vld_ip_oflow;
244 u32 tmac_rst_tcp_oflow;
245 u32 tmac_icmp_oflow;
246 u32 tpa_unknown_protocol;
247 u32 tmac_udp_oflow;
248 u32 reserved_10;
249 u32 tpa_parse_failure;
251 /* Rx MAC Statistics overflow counters. */
252 u32 rmac_data_octets_oflow;
253 u32 rmac_vld_frms_oflow;
254 u32 rmac_vld_bcst_frms_oflow;
255 u32 rmac_vld_mcst_frms_oflow;
256 u32 rmac_accepted_ucst_frms_oflow;
257 u32 rmac_ttl_octets_oflow;
258 u32 rmac_discarded_frms_oflow;
259 u32 rmac_accepted_nucst_frms_oflow;
260 u32 rmac_usized_frms_oflow;
261 u32 rmac_drop_events_oflow;
262 u32 rmac_frag_frms_oflow;
263 u32 rmac_osized_frms_oflow;
264 u32 rmac_ip_oflow;
265 u32 rmac_jabber_frms_oflow;
266 u32 rmac_icmp_oflow;
267 u32 rmac_drop_ip_oflow;
268 u32 rmac_err_drp_udp_oflow;
269 u32 rmac_udp_oflow;
270 u32 reserved_11;
271 u32 rmac_pause_cnt_oflow;
272 u64 rmac_ttl_1519_4095_frms;
273 u64 rmac_ttl_4096_8191_frms;
274 u64 rmac_ttl_8192_max_frms;
275 u64 rmac_ttl_gt_max_frms;
276 u64 rmac_osized_alt_frms;
277 u64 rmac_jabber_alt_frms;
278 u64 rmac_gt_max_alt_frms;
279 u64 rmac_vlan_frms;
280 u32 rmac_len_discard;
281 u32 rmac_fcs_discard;
282 u32 rmac_pf_discard;
283 u32 rmac_da_discard;
284 u32 rmac_red_discard;
285 u32 rmac_rts_discard;
286 u32 reserved_12;
287 u32 rmac_ingm_full_discard;
288 u32 reserved_13;
289 u32 rmac_accepted_ip_oflow;
290 u32 reserved_14;
291 u32 link_fault_cnt;
292 u8 buffer[20];
293 swStat_t sw_stat;
294 xpakStat_t xpak_stat;
295 } StatInfo_t;
297 /*
298 * Structures representing different init time configuration
299 * parameters of the NIC.
300 */
302 #define MAX_TX_FIFOS 8
303 #define MAX_RX_RINGS 8
305 /* FIFO mappings for all possible number of fifos configured */
306 static int fifo_map[][MAX_TX_FIFOS] = {
307 {0, 0, 0, 0, 0, 0, 0, 0},
308 {0, 0, 0, 0, 1, 1, 1, 1},
309 {0, 0, 0, 1, 1, 1, 2, 2},
310 {0, 0, 1, 1, 2, 2, 3, 3},
311 {0, 0, 1, 1, 2, 2, 3, 4},
312 {0, 0, 1, 1, 2, 3, 4, 5},
313 {0, 0, 1, 2, 3, 4, 5, 6},
314 {0, 1, 2, 3, 4, 5, 6, 7},
315 };
317 /* Maintains Per FIFO related information. */
318 typedef struct tx_fifo_config {
319 #define MAX_AVAILABLE_TXDS 8192
320 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
321 /* Priority definition */
322 #define TX_FIFO_PRI_0 0 /*Highest */
323 #define TX_FIFO_PRI_1 1
324 #define TX_FIFO_PRI_2 2
325 #define TX_FIFO_PRI_3 3
326 #define TX_FIFO_PRI_4 4
327 #define TX_FIFO_PRI_5 5
328 #define TX_FIFO_PRI_6 6
329 #define TX_FIFO_PRI_7 7 /*lowest */
330 u8 fifo_priority; /* specifies pointer level for FIFO */
331 /* user should not set twos fifos with same pri */
332 u8 f_no_snoop;
333 #define NO_SNOOP_TXD 0x01
334 #define NO_SNOOP_TXD_BUFFER 0x02
335 } tx_fifo_config_t;
338 /* Maintains per Ring related information */
339 typedef struct rx_ring_config {
340 u32 num_rxd; /*No of RxDs per Rx Ring */
341 #define RX_RING_PRI_0 0 /* highest */
342 #define RX_RING_PRI_1 1
343 #define RX_RING_PRI_2 2
344 #define RX_RING_PRI_3 3
345 #define RX_RING_PRI_4 4
346 #define RX_RING_PRI_5 5
347 #define RX_RING_PRI_6 6
348 #define RX_RING_PRI_7 7 /* lowest */
350 u8 ring_priority; /*Specifies service priority of ring */
351 /* OSM should not set any two rings with same priority */
352 u8 ring_org; /*Organization of ring */
353 #define RING_ORG_BUFF1 0x01
354 #define RX_RING_ORG_BUFF3 0x03
355 #define RX_RING_ORG_BUFF5 0x05
357 u8 f_no_snoop;
358 #define NO_SNOOP_RXD 0x01
359 #define NO_SNOOP_RXD_BUFFER 0x02
360 } rx_ring_config_t;
362 /* This structure provides contains values of the tunable parameters
363 * of the H/W
364 */
365 struct config_param {
366 /* Tx Side */
367 u32 tx_fifo_num; /*Number of Tx FIFOs */
369 u8 fifo_mapping[MAX_TX_FIFOS];
370 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
371 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
372 u64 tx_intr_type;
373 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
375 /* Rx Side */
376 u32 rx_ring_num; /*Number of receive rings */
377 #define MAX_RX_BLOCKS_PER_RING 150
379 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
380 u8 bimodal; /*Flag for setting bimodal interrupts*/
382 #define HEADER_ETHERNET_II_802_3_SIZE 14
383 #define HEADER_802_2_SIZE 3
384 #define HEADER_SNAP_SIZE 5
385 #define HEADER_VLAN_SIZE 4
387 #define MIN_MTU 46
388 #define MAX_PYLD 1500
389 #define MAX_MTU (MAX_PYLD+18)
390 #define MAX_MTU_VLAN (MAX_PYLD+22)
391 #define MAX_PYLD_JUMBO 9600
392 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
393 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
394 u16 bus_speed;
395 };
397 /* Structure representing MAC Addrs */
398 typedef struct mac_addr {
399 u8 mac_addr[ETH_ALEN];
400 } macaddr_t;
402 /* Structure that represent every FIFO element in the BAR1
403 * Address location.
404 */
405 typedef struct _TxFIFO_element {
406 u64 TxDL_Pointer;
408 u64 List_Control;
409 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
410 #define TX_FIFO_FIRST_LIST BIT(14)
411 #define TX_FIFO_LAST_LIST BIT(15)
412 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
413 #define TX_FIFO_SPECIAL_FUNC BIT(23)
414 #define TX_FIFO_DS_NO_SNOOP BIT(31)
415 #define TX_FIFO_BUFF_NO_SNOOP BIT(30)
416 } TxFIFO_element_t;
418 /* Tx descriptor structure */
419 typedef struct _TxD {
420 u64 Control_1;
421 /* bit mask */
422 #define TXD_LIST_OWN_XENA BIT(7)
423 #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
424 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
425 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
426 #define TXD_GATHER_CODE (BIT(22) | BIT(23))
427 #define TXD_GATHER_CODE_FIRST BIT(22)
428 #define TXD_GATHER_CODE_LAST BIT(23)
429 #define TXD_TCP_LSO_EN BIT(30)
430 #define TXD_UDP_COF_EN BIT(31)
431 #define TXD_UFO_EN BIT(31) | BIT(30)
432 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
433 #define TXD_UFO_MSS(val) vBIT(val,34,14)
434 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
436 u64 Control_2;
437 #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
438 #define TXD_TX_CKO_IPV4_EN BIT(5)
439 #define TXD_TX_CKO_TCP_EN BIT(6)
440 #define TXD_TX_CKO_UDP_EN BIT(7)
441 #define TXD_VLAN_ENABLE BIT(15)
442 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
443 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
444 #define TXD_INT_TYPE_PER_LIST BIT(47)
445 #define TXD_INT_TYPE_UTILZ BIT(46)
446 #define TXD_SET_MARKER vBIT(0x6,0,4)
448 u64 Buffer_Pointer;
449 u64 Host_Control; /* reserved for host */
450 } TxD_t;
452 /* Structure to hold the phy and virt addr of every TxDL. */
453 typedef struct list_info_hold {
454 dma_addr_t list_phy_addr;
455 void *list_virt_addr;
456 } list_info_hold_t;
458 /* Rx descriptor structure for 1 buffer mode */
459 typedef struct _RxD_t {
460 u64 Host_Control; /* reserved for host */
461 u64 Control_1;
462 #define RXD_OWN_XENA BIT(7)
463 #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
464 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
465 #define RXD_FRAME_PROTO_IPV4 BIT(27)
466 #define RXD_FRAME_PROTO_IPV6 BIT(28)
467 #define RXD_FRAME_IP_FRAG BIT(29)
468 #define RXD_FRAME_PROTO_TCP BIT(30)
469 #define RXD_FRAME_PROTO_UDP BIT(31)
470 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
471 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
472 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
474 u64 Control_2;
475 #define THE_RXD_MARK 0x3
476 #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
477 #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
479 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
480 #define SET_VLAN_TAG(val) vBIT(val,48,16)
481 #define SET_NUM_TAG(val) vBIT(val,16,32)
484 } RxD_t;
485 /* Rx descriptor structure for 1 buffer mode */
486 typedef struct _RxD1_t {
487 struct _RxD_t h;
489 #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
490 #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
491 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
492 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
493 u64 Buffer0_ptr;
494 } RxD1_t;
495 /* Rx descriptor structure for 3 or 2 buffer mode */
497 typedef struct _RxD3_t {
498 struct _RxD_t h;
500 #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
501 #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
502 #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
503 #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
504 #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
505 #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
506 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
507 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
508 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
509 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
510 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
511 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
512 #define BUF0_LEN 40
513 #define BUF1_LEN 1
515 u64 Buffer0_ptr;
516 u64 Buffer1_ptr;
517 u64 Buffer2_ptr;
518 } RxD3_t;
521 /* Structure that represents the Rx descriptor block which contains
522 * 128 Rx descriptors.
523 */
524 typedef struct _RxD_block {
525 #define MAX_RXDS_PER_BLOCK_1 127
526 RxD1_t rxd[MAX_RXDS_PER_BLOCK_1];
528 u64 reserved_0;
529 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
530 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
531 * Rxd in this blk */
532 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
533 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
534 * the upper 32 bits should
535 * be 0 */
536 } RxD_block_t;
538 #define SIZE_OF_BLOCK 4096
540 #define RXD_MODE_1 0
541 #define RXD_MODE_3A 1
542 #define RXD_MODE_3B 2
544 /* Structure to hold virtual addresses of Buf0 and Buf1 in
545 * 2buf mode. */
546 typedef struct bufAdd {
547 void *ba_0_org;
548 void *ba_1_org;
549 void *ba_0;
550 void *ba_1;
551 } buffAdd_t;
553 /* Structure which stores all the MAC control parameters */
555 /* This structure stores the offset of the RxD in the ring
556 * from which the Rx Interrupt processor can start picking
557 * up the RxDs for processing.
558 */
559 typedef struct _rx_curr_get_info_t {
560 u32 block_index;
561 u32 offset;
562 u32 ring_len;
563 } rx_curr_get_info_t;
565 typedef rx_curr_get_info_t rx_curr_put_info_t;
567 /* This structure stores the offset of the TxDl in the FIFO
568 * from which the Tx Interrupt processor can start picking
569 * up the TxDLs for send complete interrupt processing.
570 */
571 typedef struct {
572 u32 offset;
573 u32 fifo_len;
574 } tx_curr_get_info_t;
576 typedef tx_curr_get_info_t tx_curr_put_info_t;
579 typedef struct rxd_info {
580 void *virt_addr;
581 dma_addr_t dma_addr;
582 }rxd_info_t;
584 /* Structure that holds the Phy and virt addresses of the Blocks */
585 typedef struct rx_block_info {
586 void *block_virt_addr;
587 dma_addr_t block_dma_addr;
588 rxd_info_t *rxds;
589 } rx_block_info_t;
591 /* pre declaration of the nic structure */
592 typedef struct s2io_nic nic_t;
594 /* Ring specific structure */
595 typedef struct ring_info {
596 /* The ring number */
597 int ring_no;
599 /*
600 * Place holders for the virtual and physical addresses of
601 * all the Rx Blocks
602 */
603 rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
604 int block_count;
605 int pkt_cnt;
607 /*
608 * Put pointer info which indictes which RxD has to be replenished
609 * with a new buffer.
610 */
611 rx_curr_put_info_t rx_curr_put_info;
613 /*
614 * Get pointer info which indictes which is the last RxD that was
615 * processed by the driver.
616 */
617 rx_curr_get_info_t rx_curr_get_info;
619 #ifndef CONFIG_S2IO_NAPI
620 /* Index to the absolute position of the put pointer of Rx ring */
621 int put_pos;
622 #endif
624 /* Buffer Address store. */
625 buffAdd_t **ba;
626 nic_t *nic;
627 } ring_info_t;
629 /* Fifo specific structure */
630 typedef struct fifo_info {
631 /* FIFO number */
632 int fifo_no;
634 /* Maximum TxDs per TxDL */
635 int max_txds;
637 /* Place holder of all the TX List's Phy and Virt addresses. */
638 list_info_hold_t *list_info;
640 /*
641 * Current offset within the tx FIFO where driver would write
642 * new Tx frame
643 */
644 tx_curr_put_info_t tx_curr_put_info;
646 /*
647 * Current offset within tx FIFO from where the driver would start freeing
648 * the buffers
649 */
650 tx_curr_get_info_t tx_curr_get_info;
652 nic_t *nic;
653 }fifo_info_t;
655 /* Information related to the Tx and Rx FIFOs and Rings of Xena
656 * is maintained in this structure.
657 */
658 typedef struct mac_info {
659 /* tx side stuff */
660 /* logical pointer of start of each Tx FIFO */
661 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
663 /* Fifo specific structure */
664 fifo_info_t fifos[MAX_TX_FIFOS];
666 /* Save virtual address of TxD page with zero DMA addr(if any) */
667 void *zerodma_virt_addr;
669 /* rx side stuff */
670 /* Ring specific structure */
671 ring_info_t rings[MAX_RX_RINGS];
673 u16 rmac_pause_time;
674 u16 mc_pause_threshold_q0q3;
675 u16 mc_pause_threshold_q4q7;
677 void *stats_mem; /* orignal pointer to allocated mem */
678 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
679 u32 stats_mem_sz;
680 StatInfo_t *stats_info; /* Logical address of the stat block */
681 } mac_info_t;
683 /* structure representing the user defined MAC addresses */
684 typedef struct {
685 char addr[ETH_ALEN];
686 int usage_cnt;
687 } usr_addr_t;
689 /* Default Tunable parameters of the NIC. */
690 #define DEFAULT_FIFO_0_LEN 4096
691 #define DEFAULT_FIFO_1_7_LEN 512
692 #define SMALL_BLK_CNT 30
693 #define LARGE_BLK_CNT 100
695 /*
696 * Structure to keep track of the MSI-X vectors and the corresponding
697 * argument registered against each vector
698 */
699 #define MAX_REQUESTED_MSI_X 17
700 struct s2io_msix_entry
701 {
702 u16 vector;
703 u16 entry;
704 void *arg;
706 u8 type;
707 #define MSIX_FIFO_TYPE 1
708 #define MSIX_RING_TYPE 2
710 u8 in_use;
711 #define MSIX_REGISTERED_SUCCESS 0xAA
712 };
714 struct msix_info_st {
715 u64 addr;
716 u64 data;
717 };
719 /* Data structure to represent a LRO session */
720 typedef struct lro {
721 struct sk_buff *parent;
722 struct sk_buff *last_frag;
723 u8 *l2h;
724 struct iphdr *iph;
725 struct tcphdr *tcph;
726 u32 tcp_next_seq;
727 u32 tcp_ack;
728 int total_len;
729 int frags_len;
730 int sg_num;
731 int in_use;
732 u16 window;
733 u32 cur_tsval;
734 u32 cur_tsecr;
735 u8 saw_ts;
736 }lro_t;
738 /* Structure representing one instance of the NIC */
739 struct s2io_nic {
740 int rxd_mode;
741 #ifdef CONFIG_S2IO_NAPI
742 /*
743 * Count of packets to be processed in a given iteration, it will be indicated
744 * by the quota field of the device structure when NAPI is enabled.
745 */
746 int pkts_to_process;
747 #endif
748 struct net_device *dev;
749 mac_info_t mac_control;
750 struct config_param config;
751 struct pci_dev *pdev;
752 void __iomem *bar0;
753 void __iomem *bar1;
754 #define MAX_MAC_SUPPORTED 16
755 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
757 macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
758 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
760 struct net_device_stats stats;
761 int high_dma_flag;
762 int device_close_flag;
763 int device_enabled_once;
765 char name[60];
766 struct tasklet_struct task;
767 volatile unsigned long tasklet_status;
769 /* Timer that handles I/O errors/exceptions */
770 struct timer_list alarm_timer;
772 /* Space to back up the PCI config space */
773 u32 config_space[256 / sizeof(u32)];
775 atomic_t rx_bufs_left[MAX_RX_RINGS];
777 spinlock_t tx_lock;
778 #ifndef CONFIG_S2IO_NAPI
779 spinlock_t put_lock;
780 #endif
782 #define PROMISC 1
783 #define ALL_MULTI 2
785 #define MAX_ADDRS_SUPPORTED 64
786 u16 usr_addr_count;
787 u16 mc_addr_count;
788 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
790 u16 m_cast_flg;
791 u16 all_multi_pos;
792 u16 promisc_flg;
794 u16 tx_pkt_count;
795 u16 rx_pkt_count;
796 u16 tx_err_count;
797 u16 rx_err_count;
799 /* Id timer, used to blink NIC to physically identify NIC. */
800 struct timer_list id_timer;
802 /* Restart timer, used to restart NIC if the device is stuck and
803 * a schedule task that will set the correct Link state once the
804 * NIC's PHY has stabilized after a state change.
805 */
806 struct work_struct rst_timer_task;
807 struct work_struct set_link_task;
809 /* Flag that can be used to turn on or turn off the Rx checksum
810 * offload feature.
811 */
812 int rx_csum;
814 /* after blink, the adapter must be restored with original
815 * values.
816 */
817 u64 adapt_ctrl_org;
819 /* Last known link state. */
820 u16 last_link_state;
821 #define LINK_DOWN 1
822 #define LINK_UP 2
824 int task_flag;
825 #define CARD_DOWN 1
826 #define CARD_UP 2
827 atomic_t card_state;
828 volatile unsigned long link_state;
829 struct vlan_group *vlgrp;
830 #define MSIX_FLG 0xA5
831 struct msix_entry *entries;
832 struct s2io_msix_entry *s2io_entries;
833 char desc[MAX_REQUESTED_MSI_X][25];
835 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
837 struct msix_info_st msix_info[0x3f];
839 #define XFRAME_I_DEVICE 1
840 #define XFRAME_II_DEVICE 2
841 u8 device_type;
843 #define MAX_LRO_SESSIONS 32
844 lro_t lro0_n[MAX_LRO_SESSIONS];
845 unsigned long clubbed_frms_cnt;
846 unsigned long sending_both;
847 u8 lro;
848 u16 lro_max_aggr_per_sess;
850 #define INTA 0
851 #define MSI 1
852 #define MSI_X 2
853 u8 intr_type;
855 spinlock_t rx_lock;
856 atomic_t isr_cnt;
857 u64 *ufo_in_band_v;
858 #define VPD_PRODUCT_NAME_LEN 50
859 u8 product_name[VPD_PRODUCT_NAME_LEN];
860 };
862 #define RESET_ERROR 1;
863 #define CMD_ERROR 2;
865 /* OS related system calls */
866 #ifndef readq
867 static inline u64 readq(void __iomem *addr)
868 {
869 u64 ret = 0;
870 ret = readl(addr + 4);
871 ret <<= 32;
872 ret |= readl(addr);
874 return ret;
875 }
876 #endif
878 #ifndef writeq
879 static inline void writeq(u64 val, void __iomem *addr)
880 {
881 writel((u32) (val), addr);
882 writel((u32) (val >> 32), (addr + 4));
883 }
884 #endif
886 /*
887 * Some registers have to be written in a particular order to
888 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
889 * is used to perform such ordered writes. Defines UF (Upper First)
890 * and LF (Lower First) will be used to specify the required write order.
891 */
892 #define UF 1
893 #define LF 2
894 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
895 {
896 u32 ret;
898 if (order == LF) {
899 writel((u32) (val), addr);
900 ret = readl(addr);
901 writel((u32) (val >> 32), (addr + 4));
902 ret = readl(addr + 4);
903 } else {
904 writel((u32) (val >> 32), (addr + 4));
905 ret = readl(addr + 4);
906 writel((u32) (val), addr);
907 ret = readl(addr);
908 }
909 }
911 /* Interrupt related values of Xena */
913 #define ENABLE_INTRS 1
914 #define DISABLE_INTRS 2
916 /* Highest level interrupt blocks */
917 #define TX_PIC_INTR (0x0001<<0)
918 #define TX_DMA_INTR (0x0001<<1)
919 #define TX_MAC_INTR (0x0001<<2)
920 #define TX_XGXS_INTR (0x0001<<3)
921 #define TX_TRAFFIC_INTR (0x0001<<4)
922 #define RX_PIC_INTR (0x0001<<5)
923 #define RX_DMA_INTR (0x0001<<6)
924 #define RX_MAC_INTR (0x0001<<7)
925 #define RX_XGXS_INTR (0x0001<<8)
926 #define RX_TRAFFIC_INTR (0x0001<<9)
927 #define MC_INTR (0x0001<<10)
928 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
929 TX_DMA_INTR | \
930 TX_MAC_INTR | \
931 TX_XGXS_INTR | \
932 TX_TRAFFIC_INTR | \
933 RX_PIC_INTR | \
934 RX_DMA_INTR | \
935 RX_MAC_INTR | \
936 RX_XGXS_INTR | \
937 RX_TRAFFIC_INTR | \
938 MC_INTR )
940 /* Interrupt masks for the general interrupt mask register */
941 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
943 #define TXPIC_INT_M BIT(0)
944 #define TXDMA_INT_M BIT(1)
945 #define TXMAC_INT_M BIT(2)
946 #define TXXGXS_INT_M BIT(3)
947 #define TXTRAFFIC_INT_M BIT(8)
948 #define PIC_RX_INT_M BIT(32)
949 #define RXDMA_INT_M BIT(33)
950 #define RXMAC_INT_M BIT(34)
951 #define MC_INT_M BIT(35)
952 #define RXXGXS_INT_M BIT(36)
953 #define RXTRAFFIC_INT_M BIT(40)
955 /* PIC level Interrupts TODO*/
957 /* DMA level Inressupts */
958 #define TXDMA_PFC_INT_M BIT(0)
959 #define TXDMA_PCC_INT_M BIT(2)
961 /* PFC block interrupts */
962 #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
964 /* PCC block interrupts. */
965 #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
966 PCC_FB_ECC Error. */
968 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
969 /*
970 * Prototype declaration.
971 */
972 static int __devinit s2io_init_nic(struct pci_dev *pdev,
973 const struct pci_device_id *pre);
974 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
975 static int init_shared_mem(struct s2io_nic *sp);
976 static void free_shared_mem(struct s2io_nic *sp);
977 static int init_nic(struct s2io_nic *nic);
978 static void rx_intr_handler(ring_info_t *ring_data);
979 static void tx_intr_handler(fifo_info_t *fifo_data);
980 static void alarm_intr_handler(struct s2io_nic *sp);
982 static int s2io_starter(void);
983 static void s2io_tx_watchdog(struct net_device *dev);
984 static void s2io_tasklet(unsigned long dev_addr);
985 static void s2io_set_multicast(struct net_device *dev);
986 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
987 static void s2io_link(nic_t * sp, int link);
988 #if defined(CONFIG_S2IO_NAPI)
989 static int s2io_poll(struct net_device *dev, int *budget);
990 #endif
991 static void s2io_init_pci(nic_t * sp);
992 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
993 static void s2io_alarm_handle(unsigned long data);
994 static int s2io_enable_msi(nic_t *nic);
995 static irqreturn_t s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs);
996 static irqreturn_t
997 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs);
998 static irqreturn_t
999 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs);
1000 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
1001 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
1002 static struct ethtool_ops netdev_ethtool_ops;
1003 static void s2io_set_link(unsigned long data);
1004 static int s2io_set_swapper(nic_t * sp);
1005 static void s2io_card_down(nic_t *nic);
1006 static int s2io_card_up(nic_t *nic);
1007 static int get_xena_rev_id(struct pci_dev *pdev);
1008 static void restore_xmsi_data(nic_t *nic);
1010 static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp);
1011 static void clear_lro_session(lro_t *lro);
1012 static void queue_rx_frame(struct sk_buff *skb);
1013 static void update_L3L4_header(nic_t *sp, lro_t *lro);
1014 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len);
1016 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1017 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1018 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1020 #define S2IO_PARM_INT(X, def_val) \
1021 static unsigned int X = def_val;\
1022 module_param(X , uint, 0);
1024 #endif /* _S2IO_H */