ia64/linux-2.6.18-xen.hg

view drivers/net/depca.h @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
line source
1 /*
2 Written 1994 by David C. Davies.
4 Copyright 1994 David C. Davies. This software may be used and distributed
5 according to the terms of the GNU General Public License, incorporated herein by
6 reference.
7 */
9 /*
10 ** I/O addresses. Note that the 2k buffer option is not supported in
11 ** this driver.
12 */
13 #define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
14 #define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
15 #define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
16 #define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
17 #define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
18 #define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
19 #define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
20 #define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
22 /*
23 ** These are LANCE registers addressable through DEPCA_ADDR
24 */
25 #define CSR0 0
26 #define CSR1 1
27 #define CSR2 2
28 #define CSR3 3
30 /*
31 ** NETWORK INTERFACE CSR (NI_CSR) bit definitions
32 */
34 #define TO 0x0100 /* Time Out for remote boot */
35 #define SHE 0x0080 /* SHadow memory Enable */
36 #define BS 0x0040 /* Bank Select */
37 #define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
38 #define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
39 #define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
40 #define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
41 #define IM 0x0004 /* Interrupt Mask (1->mask) */
42 #define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
43 #define LED 0x0001 /* LED control */
45 /*
46 ** Control and Status Register 0 (CSR0) bit definitions
47 */
49 #define ERR 0x8000 /* Error summary */
50 #define BABL 0x4000 /* Babble transmitter timeout error */
51 #define CERR 0x2000 /* Collision Error */
52 #define MISS 0x1000 /* Missed packet */
53 #define MERR 0x0800 /* Memory Error */
54 #define RINT 0x0400 /* Receiver Interrupt */
55 #define TINT 0x0200 /* Transmit Interrupt */
56 #define IDON 0x0100 /* Initialization Done */
57 #define INTR 0x0080 /* Interrupt Flag */
58 #define INEA 0x0040 /* Interrupt Enable */
59 #define RXON 0x0020 /* Receiver on */
60 #define TXON 0x0010 /* Transmitter on */
61 #define TDMD 0x0008 /* Transmit Demand */
62 #define STOP 0x0004 /* Stop */
63 #define STRT 0x0002 /* Start */
64 #define INIT 0x0001 /* Initialize */
65 #define INTM 0xff00 /* Interrupt Mask */
66 #define INTE 0xfff0 /* Interrupt Enable */
68 /*
69 ** CONTROL AND STATUS REGISTER 3 (CSR3)
70 */
72 #define BSWP 0x0004 /* Byte SWaP */
73 #define ACON 0x0002 /* ALE control */
74 #define BCON 0x0001 /* Byte CONtrol */
76 /*
77 ** Initialization Block Mode Register
78 */
80 #define PROM 0x8000 /* Promiscuous Mode */
81 #define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
82 #define INTL 0x0040 /* Internal Loopback */
83 #define DRTY 0x0020 /* Disable Retry */
84 #define COLL 0x0010 /* Force Collision */
85 #define DTCR 0x0008 /* Disable Transmit CRC */
86 #define LOOP 0x0004 /* Loopback */
87 #define DTX 0x0002 /* Disable the Transmitter */
88 #define DRX 0x0001 /* Disable the Receiver */
90 /*
91 ** Receive Message Descriptor 1 (RMD1) bit definitions.
92 */
94 #define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
95 #define R_ERR 0x4000 /* Error Summary */
96 #define R_FRAM 0x2000 /* Framing Error */
97 #define R_OFLO 0x1000 /* Overflow Error */
98 #define R_CRC 0x0800 /* CRC Error */
99 #define R_BUFF 0x0400 /* Buffer Error */
100 #define R_STP 0x0200 /* Start of Packet */
101 #define R_ENP 0x0100 /* End of Packet */
103 /*
104 ** Transmit Message Descriptor 1 (TMD1) bit definitions.
105 */
107 #define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
108 #define T_ERR 0x4000 /* Error Summary */
109 #define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
110 #define T_MORE 0x1000 /* >1 retry to transmit packet */
111 #define T_ONE 0x0800 /* 1 try needed to transmit the packet */
112 #define T_DEF 0x0400 /* Deferred */
113 #define T_STP 0x02000000 /* Start of Packet */
114 #define T_ENP 0x01000000 /* End of Packet */
115 #define T_FLAGS 0xff000000 /* TX Flags Field */
117 /*
118 ** Transmit Message Descriptor 3 (TMD3) bit definitions.
119 */
121 #define TMD3_BUFF 0x8000 /* BUFFer error */
122 #define TMD3_UFLO 0x4000 /* UnderFLOw error */
123 #define TMD3_RES 0x2000 /* REServed */
124 #define TMD3_LCOL 0x1000 /* Late COLlision */
125 #define TMD3_LCAR 0x0800 /* Loss of CARrier */
126 #define TMD3_RTRY 0x0400 /* ReTRY error */
128 /*
129 ** EISA configuration Register (CNFG) bit definitions
130 */
132 #define TIMEOUT 0x0100 /* 0:2.5 mins, 1: 30 secs */
133 #define REMOTE 0x0080 /* Remote Boot Enable -> 1 */
134 #define IRQ11 0x0040 /* Enable -> 1 */
135 #define IRQ10 0x0020 /* Enable -> 1 */
136 #define IRQ9 0x0010 /* Enable -> 1 */
137 #define IRQ5 0x0008 /* Enable -> 1 */
138 #define BUFF 0x0004 /* 0: 64kB or 128kB, 1: 32kB */
139 #define PADR16 0x0002 /* RAM on 64kB boundary */
140 #define PADR17 0x0001 /* RAM on 128kB boundary */
142 /*
143 ** Miscellaneous
144 */
145 #define HASH_TABLE_LEN 64 /* Bits */
146 #define HASH_BITS 0x003f /* 6 LS bits */
148 #define MASK_INTERRUPTS 1
149 #define UNMASK_INTERRUPTS 0
151 #define EISA_EN 0x0001 /* Enable EISA bus buffers */
152 #define EISA_ID iobase+0x0080 /* ID long word for EISA card */
153 #define EISA_CTRL iobase+0x0084 /* Control word for EISA card */
155 /*
156 ** Include the IOCTL stuff
157 */
158 #include <linux/sockios.h>
160 #define DEPCAIOCTL SIOCDEVPRIVATE
162 struct depca_ioctl {
163 unsigned short cmd; /* Command to run */
164 unsigned short len; /* Length of the data buffer */
165 unsigned char __user *data; /* Pointer to the data buffer */
166 };
168 /*
169 ** Recognised commands for the driver
170 */
171 #define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */
172 #define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */
173 #define DEPCA_SET_PROM 0x03 /* Set Promiscuous Mode */
174 #define DEPCA_CLR_PROM 0x04 /* Clear Promiscuous Mode */
175 #define DEPCA_SAY_BOO 0x05 /* Say "Boo!" to the kernel log file */
176 #define DEPCA_GET_MCA 0x06 /* Get a multicast address */
177 #define DEPCA_SET_MCA 0x07 /* Set a multicast address */
178 #define DEPCA_CLR_MCA 0x08 /* Clear a multicast address */
179 #define DEPCA_MCA_EN 0x09 /* Enable a multicast address group */
180 #define DEPCA_GET_STATS 0x0a /* Get the driver statistics */
181 #define DEPCA_CLR_STATS 0x0b /* Zero out the driver statistics */
182 #define DEPCA_GET_REG 0x0c /* Get the Register contents */
183 #define DEPCA_SET_REG 0x0d /* Set the Register contents */
184 #define DEPCA_DUMP 0x0f /* Dump the DEPCA Status */