ia64/linux-2.6.18-xen.hg

view drivers/char/rio/cirrus.h @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
line source
1 /****************************************************************************
2 ******* *******
3 ******* CIRRUS.H *******
4 ******* *******
5 ****************************************************************************
7 Author : Jeremy Rolls
8 Date : 3 Aug 1990
10 *
11 * (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 Version : 0.01
30 Mods
31 ----------------------------------------------------------------------------
32 Date By Description
33 ----------------------------------------------------------------------------
35 ***************************************************************************/
37 #ifndef _cirrus_h
38 #ifndef lint
39 /* static char* _cirrus_h_sccs = "@(#)cirrus.h 1.16"; */
40 #endif
41 #define _cirrus_h 1
43 /* Bit fields for particular registers shared with driver */
45 /* COR1 - driver and RTA */
46 #define COR1_ODD 0x80 /* Odd parity */
47 #define COR1_EVEN 0x00 /* Even parity */
48 #define COR1_NOP 0x00 /* No parity */
49 #define COR1_FORCE 0x20 /* Force parity */
50 #define COR1_NORMAL 0x40 /* With parity */
51 #define COR1_1STOP 0x00 /* 1 stop bit */
52 #define COR1_15STOP 0x04 /* 1.5 stop bits */
53 #define COR1_2STOP 0x08 /* 2 stop bits */
54 #define COR1_5BITS 0x00 /* 5 data bits */
55 #define COR1_6BITS 0x01 /* 6 data bits */
56 #define COR1_7BITS 0x02 /* 7 data bits */
57 #define COR1_8BITS 0x03 /* 8 data bits */
59 #define COR1_HOST 0xef /* Safe host bits */
61 /* RTA only */
62 #define COR1_CINPCK 0x00 /* Check parity of received characters */
63 #define COR1_CNINPCK 0x10 /* Don't check parity */
65 /* COR2 bits for both RTA and driver use */
66 #define COR2_IXANY 0x80 /* IXANY - any character is XON */
67 #define COR2_IXON 0x40 /* IXON - enable tx soft flowcontrol */
68 #define COR2_RTSFLOW 0x02 /* Enable tx hardware flow control */
70 /* Additional driver bits */
71 #define COR2_HUPCL 0x20 /* Hang up on close */
72 #define COR2_CTSFLOW 0x04 /* Enable rx hardware flow control */
73 #define COR2_IXOFF 0x01 /* Enable rx software flow control */
74 #define COR2_DTRFLOW 0x08 /* Enable tx hardware flow control */
76 /* RTA use only */
77 #define COR2_ETC 0x20 /* Embedded transmit options */
78 #define COR2_LOCAL 0x10 /* Local loopback mode */
79 #define COR2_REMOTE 0x08 /* Remote loopback mode */
80 #define COR2_HOST 0xc2 /* Safe host bits */
82 /* COR3 - RTA use only */
83 #define COR3_SCDRNG 0x80 /* Enable special char detect for range */
84 #define COR3_SCD34 0x40 /* Special character detect for SCHR's 3 + 4 */
85 #define COR3_FCT 0x20 /* Flow control transparency */
86 #define COR3_SCD12 0x10 /* Special character detect for SCHR's 1 + 2 */
87 #define COR3_FIFO12 0x0c /* 12 chars for receive FIFO threshold */
88 #define COR3_FIFO10 0x0a /* 10 chars for receive FIFO threshold */
89 #define COR3_FIFO8 0x08 /* 8 chars for receive FIFO threshold */
90 #define COR3_FIFO6 0x06 /* 6 chars for receive FIFO threshold */
92 #define COR3_THRESHOLD COR3_FIFO8 /* MUST BE LESS THAN MCOR_THRESHOLD */
94 #define COR3_DEFAULT (COR3_FCT | COR3_THRESHOLD)
95 /* Default bits for COR3 */
97 /* COR4 driver and RTA use */
98 #define COR4_IGNCR 0x80 /* Throw away CR's on input */
99 #define COR4_ICRNL 0x40 /* Map CR -> NL on input */
100 #define COR4_INLCR 0x20 /* Map NL -> CR on input */
101 #define COR4_IGNBRK 0x10 /* Ignore Break */
102 #define COR4_NBRKINT 0x08 /* No interrupt on break (-BRKINT) */
103 #define COR4_RAISEMOD 0x01 /* Raise modem output lines on non-zero baud */
106 /* COR4 driver only */
107 #define COR4_IGNPAR 0x04 /* IGNPAR (ignore characters with errors) */
108 #define COR4_PARMRK 0x02 /* PARMRK */
110 #define COR4_HOST 0xf8 /* Safe host bits */
112 /* COR4 RTA only */
113 #define COR4_CIGNPAR 0x02 /* Thrown away bad characters */
114 #define COR4_CPARMRK 0x04 /* PARMRK characters */
115 #define COR4_CNPARMRK 0x03 /* Don't PARMRK */
117 /* COR5 driver and RTA use */
118 #define COR5_ISTRIP 0x80 /* Strip input chars to 7 bits */
119 #define COR5_LNE 0x40 /* Enable LNEXT processing */
120 #define COR5_CMOE 0x20 /* Match good and errored characters */
121 #define COR5_ONLCR 0x02 /* NL -> CR NL on output */
122 #define COR5_OCRNL 0x01 /* CR -> NL on output */
124 /*
125 ** Spare bits - these are not used in the CIRRUS registers, so we use
126 ** them to set various other features.
127 */
128 /*
129 ** tstop and tbusy indication
130 */
131 #define COR5_TSTATE_ON 0x08 /* Turn on monitoring of tbusy and tstop */
132 #define COR5_TSTATE_OFF 0x04 /* Turn off monitoring of tbusy and tstop */
133 /*
134 ** TAB3
135 */
136 #define COR5_TAB3 0x10 /* TAB3 mode */
138 #define COR5_HOST 0xc3 /* Safe host bits */
140 /* CCSR */
141 #define CCSR_TXFLOFF 0x04 /* Tx is xoffed */
143 /* MSVR1 */
144 /* NB. DTR / CD swapped from Cirrus spec as the pins are also reversed on the
145 RTA. This is because otherwise DCD would get lost on the 1 parallel / 3
146 serial option.
147 */
148 #define MSVR1_CD 0x80 /* CD (DSR on Cirrus) */
149 #define MSVR1_RTS 0x40 /* RTS (CTS on Cirrus) */
150 #define MSVR1_RI 0x20 /* RI */
151 #define MSVR1_DTR 0x10 /* DTR (CD on Cirrus) */
152 #define MSVR1_CTS 0x01 /* CTS output pin (RTS on Cirrus) */
153 /* Next two used to indicate state of tbusy and tstop to driver */
154 #define MSVR1_TSTOP 0x08 /* Set if port flow controlled */
155 #define MSVR1_TEMPTY 0x04 /* Set if port tx buffer empty */
157 #define MSVR1_HOST 0xf3 /* The bits the host wants */
159 /* Defines for the subscripts of a CONFIG packet */
160 #define CONFIG_COR1 1 /* Option register 1 */
161 #define CONFIG_COR2 2 /* Option register 2 */
162 #define CONFIG_COR4 3 /* Option register 4 */
163 #define CONFIG_COR5 4 /* Option register 5 */
164 #define CONFIG_TXXON 5 /* Tx XON character */
165 #define CONFIG_TXXOFF 6 /* Tx XOFF character */
166 #define CONFIG_RXXON 7 /* Rx XON character */
167 #define CONFIG_RXXOFF 8 /* Rx XOFF character */
168 #define CONFIG_LNEXT 9 /* LNEXT character */
169 #define CONFIG_TXBAUD 10 /* Tx baud rate */
170 #define CONFIG_RXBAUD 11 /* Rx baud rate */
172 #define PRE_EMPTIVE 0x80 /* Pre-emptive bit in command field */
174 /* Packet types going from Host to remote - with the exception of OPEN, MOPEN,
175 CONFIG, SBREAK and MEMDUMP the remaining bytes of the data array will not
176 be used
177 */
178 #define OPEN 0x00 /* Open a port */
179 #define CONFIG 0x01 /* Configure a port */
180 #define MOPEN 0x02 /* Modem open (block for DCD) */
181 #define CLOSE 0x03 /* Close a port */
182 #define WFLUSH (0x04 | PRE_EMPTIVE) /* Write flush */
183 #define RFLUSH (0x05 | PRE_EMPTIVE) /* Read flush */
184 #define RESUME (0x06 | PRE_EMPTIVE) /* Resume if xoffed */
185 #define SBREAK 0x07 /* Start break */
186 #define EBREAK 0x08 /* End break */
187 #define SUSPEND (0x09 | PRE_EMPTIVE) /* Susp op (behave as tho xoffed) */
188 #define FCLOSE (0x0a | PRE_EMPTIVE) /* Force close */
189 #define XPRINT 0x0b /* Xprint packet */
190 #define MBIS (0x0c | PRE_EMPTIVE) /* Set modem lines */
191 #define MBIC (0x0d | PRE_EMPTIVE) /* Clear modem lines */
192 #define MSET (0x0e | PRE_EMPTIVE) /* Set modem lines */
193 #define PCLOSE 0x0f /* Pseudo close - Leaves rx/tx enabled */
194 #define MGET (0x10 | PRE_EMPTIVE) /* Force update of modem status */
195 #define MEMDUMP (0x11 | PRE_EMPTIVE) /* Send back mem from addr supplied */
196 #define READ_REGISTER (0x12 | PRE_EMPTIVE) /* Read CD1400 register (debug) */
198 /* "Command" packets going from remote to host COMPLETE and MODEM_STATUS
199 use data[4] / data[3] to indicate current state and modem status respectively
200 */
202 #define COMPLETE (0x20 | PRE_EMPTIVE)
203 /* Command complete */
204 #define BREAK_RECEIVED (0x21 | PRE_EMPTIVE)
205 /* Break received */
206 #define MODEM_STATUS (0x22 | PRE_EMPTIVE)
207 /* Change in modem status */
209 /* "Command" packet that could go either way - handshake wake-up */
210 #define HANDSHAKE (0x23 | PRE_EMPTIVE)
211 /* Wake-up to HOST / RTA */
213 #endif