ia64/linux-2.6.18-xen.hg

view arch/alpha/kernel/sys_rawhide.c @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
line source
1 /*
2 * linux/arch/alpha/kernel/sys_rawhide.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Code supporting the RAWHIDE.
9 */
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/mm.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
18 #include <asm/ptrace.h>
19 #include <asm/system.h>
20 #include <asm/dma.h>
21 #include <asm/irq.h>
22 #include <asm/mmu_context.h>
23 #include <asm/io.h>
24 #include <asm/pgtable.h>
25 #include <asm/core_mcpcia.h>
26 #include <asm/tlbflush.h>
28 #include "proto.h"
29 #include "irq_impl.h"
30 #include "pci_impl.h"
31 #include "machvec_impl.h"
34 /*
35 * HACK ALERT! only the boot cpu is used for interrupts.
36 */
39 /* Note mask bit is true for ENABLED irqs. */
41 static unsigned int hose_irq_masks[4] = {
42 0xff0000, 0xfe0000, 0xff0000, 0xff0000
43 };
44 static unsigned int cached_irq_masks[4];
45 DEFINE_SPINLOCK(rawhide_irq_lock);
47 static inline void
48 rawhide_update_irq_hw(int hose, int mask)
49 {
50 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
51 mb();
52 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
53 }
55 static inline void
56 rawhide_enable_irq(unsigned int irq)
57 {
58 unsigned int mask, hose;
60 irq -= 16;
61 hose = irq / 24;
62 irq -= hose * 24;
63 mask = 1 << irq;
65 spin_lock(&rawhide_irq_lock);
66 mask |= cached_irq_masks[hose];
67 cached_irq_masks[hose] = mask;
68 rawhide_update_irq_hw(hose, mask);
69 spin_unlock(&rawhide_irq_lock);
70 }
72 static void
73 rawhide_disable_irq(unsigned int irq)
74 {
75 unsigned int mask, hose;
77 irq -= 16;
78 hose = irq / 24;
79 irq -= hose * 24;
80 mask = ~(1 << irq) | hose_irq_masks[hose];
82 spin_lock(&rawhide_irq_lock);
83 mask &= cached_irq_masks[hose];
84 cached_irq_masks[hose] = mask;
85 rawhide_update_irq_hw(hose, mask);
86 spin_unlock(&rawhide_irq_lock);
87 }
89 static void
90 rawhide_mask_and_ack_irq(unsigned int irq)
91 {
92 unsigned int mask, mask1, hose;
94 irq -= 16;
95 hose = irq / 24;
96 irq -= hose * 24;
97 mask1 = 1 << irq;
98 mask = ~mask1 | hose_irq_masks[hose];
100 spin_lock(&rawhide_irq_lock);
102 mask &= cached_irq_masks[hose];
103 cached_irq_masks[hose] = mask;
104 rawhide_update_irq_hw(hose, mask);
106 /* Clear the interrupt. */
107 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;
109 spin_unlock(&rawhide_irq_lock);
110 }
112 static unsigned int
113 rawhide_startup_irq(unsigned int irq)
114 {
115 rawhide_enable_irq(irq);
116 return 0;
117 }
119 static void
120 rawhide_end_irq(unsigned int irq)
121 {
122 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
123 rawhide_enable_irq(irq);
124 }
126 static struct hw_interrupt_type rawhide_irq_type = {
127 .typename = "RAWHIDE",
128 .startup = rawhide_startup_irq,
129 .shutdown = rawhide_disable_irq,
130 .enable = rawhide_enable_irq,
131 .disable = rawhide_disable_irq,
132 .ack = rawhide_mask_and_ack_irq,
133 .end = rawhide_end_irq,
134 };
136 static void
137 rawhide_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
138 {
139 int irq;
141 irq = (vector - 0x800) >> 4;
143 /*
144 * The RAWHIDE SRM console reports PCI interrupts with a vector
145 * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0)
146 * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have
147 * it line up with the actual bit numbers from the REQ registers,
148 * which is how we manage the interrupts/mask. Sigh...
149 *
150 * Also, PCI #1 interrupts are offset some more... :-(
151 */
153 if (irq == 52) {
154 /* SCSI on PCI1 is special. */
155 irq = 72;
156 }
158 /* Adjust by which hose it is from. */
159 irq -= ((irq + 16) >> 2) & 0x38;
161 handle_irq(irq, regs);
162 }
164 static void __init
165 rawhide_init_irq(void)
166 {
167 struct pci_controller *hose;
168 long i;
170 mcpcia_init_hoses();
172 for (hose = hose_head; hose; hose = hose->next) {
173 unsigned int h = hose->index;
174 unsigned int mask = hose_irq_masks[h];
176 cached_irq_masks[h] = mask;
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;
178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;
179 }
181 for (i = 16; i < 128; ++i) {
182 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
183 irq_desc[i].chip = &rawhide_irq_type;
184 }
186 init_i8259a_irqs();
187 common_init_isa_dma();
188 }
190 /*
191 * PCI Fixup configuration.
192 *
193 * Summary @ MCPCIA_PCI0_INT_REQ:
194 * Bit Meaning
195 * 0 Interrupt Line A from slot 2 PCI0
196 * 1 Interrupt Line B from slot 2 PCI0
197 * 2 Interrupt Line C from slot 2 PCI0
198 * 3 Interrupt Line D from slot 2 PCI0
199 * 4 Interrupt Line A from slot 3 PCI0
200 * 5 Interrupt Line B from slot 3 PCI0
201 * 6 Interrupt Line C from slot 3 PCI0
202 * 7 Interrupt Line D from slot 3 PCI0
203 * 8 Interrupt Line A from slot 4 PCI0
204 * 9 Interrupt Line B from slot 4 PCI0
205 * 10 Interrupt Line C from slot 4 PCI0
206 * 11 Interrupt Line D from slot 4 PCI0
207 * 12 Interrupt Line A from slot 5 PCI0
208 * 13 Interrupt Line B from slot 5 PCI0
209 * 14 Interrupt Line C from slot 5 PCI0
210 * 15 Interrupt Line D from slot 5 PCI0
211 * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
212 * 17-23 NA
213 *
214 * IdSel
215 * 1 EISA bridge (PCI bus 0 only)
216 * 2 PCI option slot 2
217 * 3 PCI option slot 3
218 * 4 PCI option slot 4
219 * 5 PCI option slot 5
220 *
221 */
223 static int __init
224 rawhide_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
225 {
226 static char irq_tab[5][5] __initdata = {
227 /*INT INTA INTB INTC INTD */
228 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */
229 { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */
230 { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */
231 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */
232 { 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */
233 };
234 const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5;
236 struct pci_controller *hose = dev->sysdata;
237 int irq = COMMON_TABLE_LOOKUP;
238 if (irq >= 0)
239 irq += 24 * hose->index;
240 return irq;
241 }
244 /*
245 * The System Vector
246 */
248 struct alpha_machine_vector rawhide_mv __initmv = {
249 .vector_name = "Rawhide",
250 DO_EV5_MMU,
251 DO_DEFAULT_RTC,
252 DO_MCPCIA_IO,
253 .machine_check = mcpcia_machine_check,
254 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
255 .min_io_address = DEFAULT_IO_BASE,
256 .min_mem_address = MCPCIA_DEFAULT_MEM_BASE,
257 .pci_dac_offset = MCPCIA_DAC_OFFSET,
259 .nr_irqs = 128,
260 .device_interrupt = rawhide_srm_device_interrupt,
262 .init_arch = mcpcia_init_arch,
263 .init_irq = rawhide_init_irq,
264 .init_rtc = common_init_rtc,
265 .init_pci = common_init_pci,
266 .kill_arch = NULL,
267 .pci_map_irq = rawhide_map_irq,
268 .pci_swizzle = common_swizzle,
269 };
270 ALIAS_MV(rawhide)