ia64/linux-2.6.18-xen.hg

view drivers/serial/vr41xx_siu.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * Driver for NEC VR4100 series Serial Interface Unit.
3 *
4 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * Based on drivers/serial/8250.c, by Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
23 #if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
27 #include <linux/console.h>
28 #include <linux/platform_device.h>
29 #include <linux/err.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/module.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial_reg.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
40 #include <asm/io.h>
41 #include <asm/vr41xx/irq.h>
42 #include <asm/vr41xx/siu.h>
43 #include <asm/vr41xx/vr41xx.h>
45 #define SIU_PORTS_MAX 2
46 #define SIU_BAUD_BASE 1152000
47 #define SIU_MAJOR 204
48 #define SIU_MINOR_BASE 82
50 #define RX_MAX_COUNT 256
51 #define TX_MAX_COUNT 15
53 #define SIUIRSEL 0x08
54 #define TMICMODE 0x20
55 #define TMICTX 0x10
56 #define IRMSEL 0x0c
57 #define IRMSEL_HP 0x08
58 #define IRMSEL_TEMIC 0x04
59 #define IRMSEL_SHARP 0x00
60 #define IRUSESEL 0x02
61 #define SIRSEL 0x01
63 struct siu_port {
64 unsigned int type;
65 unsigned int irq;
66 unsigned long start;
67 };
69 static const struct siu_port siu_type1_ports[] = {
70 { .type = PORT_VR41XX_SIU,
71 .irq = SIU_IRQ,
72 .start = 0x0c000000UL, },
73 };
75 #define SIU_TYPE1_NR_PORTS (sizeof(siu_type1_ports) / sizeof(struct siu_port))
77 static const struct siu_port siu_type2_ports[] = {
78 { .type = PORT_VR41XX_SIU,
79 .irq = SIU_IRQ,
80 .start = 0x0f000800UL, },
81 { .type = PORT_VR41XX_DSIU,
82 .irq = DSIU_IRQ,
83 .start = 0x0f000820UL, },
84 };
86 #define SIU_TYPE2_NR_PORTS (sizeof(siu_type2_ports) / sizeof(struct siu_port))
88 static struct uart_port siu_uart_ports[SIU_PORTS_MAX];
89 static uint8_t lsr_break_flag[SIU_PORTS_MAX];
91 #define siu_read(port, offset) readb((port)->membase + (offset))
92 #define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
94 void vr41xx_select_siu_interface(siu_interface_t interface)
95 {
96 struct uart_port *port;
97 unsigned long flags;
98 uint8_t irsel;
100 port = &siu_uart_ports[0];
102 spin_lock_irqsave(&port->lock, flags);
104 irsel = siu_read(port, SIUIRSEL);
105 if (interface == SIU_INTERFACE_IRDA)
106 irsel |= SIRSEL;
107 else
108 irsel &= ~SIRSEL;
109 siu_write(port, SIUIRSEL, irsel);
111 spin_unlock_irqrestore(&port->lock, flags);
112 }
114 EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
116 void vr41xx_use_irda(irda_use_t use)
117 {
118 struct uart_port *port;
119 unsigned long flags;
120 uint8_t irsel;
122 port = &siu_uart_ports[0];
124 spin_lock_irqsave(&port->lock, flags);
126 irsel = siu_read(port, SIUIRSEL);
127 if (use == FIR_USE_IRDA)
128 irsel |= IRUSESEL;
129 else
130 irsel &= ~IRUSESEL;
131 siu_write(port, SIUIRSEL, irsel);
133 spin_unlock_irqrestore(&port->lock, flags);
134 }
136 EXPORT_SYMBOL_GPL(vr41xx_use_irda);
138 void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
139 {
140 struct uart_port *port;
141 unsigned long flags;
142 uint8_t irsel;
144 port = &siu_uart_ports[0];
146 spin_lock_irqsave(&port->lock, flags);
148 irsel = siu_read(port, SIUIRSEL);
149 irsel &= ~(IRMSEL | TMICTX | TMICMODE);
150 switch (module) {
151 case SHARP_IRDA:
152 irsel |= IRMSEL_SHARP;
153 break;
154 case TEMIC_IRDA:
155 irsel |= IRMSEL_TEMIC | TMICMODE;
156 if (speed == IRDA_TX_4MBPS)
157 irsel |= TMICTX;
158 break;
159 case HP_IRDA:
160 irsel |= IRMSEL_HP;
161 break;
162 default:
163 break;
164 }
165 siu_write(port, SIUIRSEL, irsel);
167 spin_unlock_irqrestore(&port->lock, flags);
168 }
170 EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
172 static inline void siu_clear_fifo(struct uart_port *port)
173 {
174 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO);
175 siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
176 UART_FCR_CLEAR_XMIT);
177 siu_write(port, UART_FCR, 0);
178 }
180 static inline int siu_probe_ports(void)
181 {
182 switch (current_cpu_data.cputype) {
183 case CPU_VR4111:
184 case CPU_VR4121:
185 return SIU_TYPE1_NR_PORTS;
186 case CPU_VR4122:
187 case CPU_VR4131:
188 case CPU_VR4133:
189 return SIU_TYPE2_NR_PORTS;
190 }
192 return 0;
193 }
195 static inline unsigned long siu_port_size(struct uart_port *port)
196 {
197 switch (port->type) {
198 case PORT_VR41XX_SIU:
199 return 11UL;
200 case PORT_VR41XX_DSIU:
201 return 8UL;
202 }
204 return 0;
205 }
207 static inline unsigned int siu_check_type(struct uart_port *port)
208 {
209 switch (current_cpu_data.cputype) {
210 case CPU_VR4111:
211 case CPU_VR4121:
212 if (port->line == 0)
213 return PORT_VR41XX_SIU;
214 break;
215 case CPU_VR4122:
216 case CPU_VR4131:
217 case CPU_VR4133:
218 if (port->line == 0)
219 return PORT_VR41XX_SIU;
220 else if (port->line == 1)
221 return PORT_VR41XX_DSIU;
222 break;
223 }
225 return PORT_UNKNOWN;
226 }
228 static inline const char *siu_type_name(struct uart_port *port)
229 {
230 switch (port->type) {
231 case PORT_VR41XX_SIU:
232 return "SIU";
233 case PORT_VR41XX_DSIU:
234 return "DSIU";
235 }
237 return NULL;
238 }
240 static unsigned int siu_tx_empty(struct uart_port *port)
241 {
242 uint8_t lsr;
244 lsr = siu_read(port, UART_LSR);
245 if (lsr & UART_LSR_TEMT)
246 return TIOCSER_TEMT;
248 return 0;
249 }
251 static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl)
252 {
253 uint8_t mcr = 0;
255 if (mctrl & TIOCM_DTR)
256 mcr |= UART_MCR_DTR;
257 if (mctrl & TIOCM_RTS)
258 mcr |= UART_MCR_RTS;
259 if (mctrl & TIOCM_OUT1)
260 mcr |= UART_MCR_OUT1;
261 if (mctrl & TIOCM_OUT2)
262 mcr |= UART_MCR_OUT2;
263 if (mctrl & TIOCM_LOOP)
264 mcr |= UART_MCR_LOOP;
266 siu_write(port, UART_MCR, mcr);
267 }
269 static unsigned int siu_get_mctrl(struct uart_port *port)
270 {
271 uint8_t msr;
272 unsigned int mctrl = 0;
274 msr = siu_read(port, UART_MSR);
275 if (msr & UART_MSR_DCD)
276 mctrl |= TIOCM_CAR;
277 if (msr & UART_MSR_RI)
278 mctrl |= TIOCM_RNG;
279 if (msr & UART_MSR_DSR)
280 mctrl |= TIOCM_DSR;
281 if (msr & UART_MSR_CTS)
282 mctrl |= TIOCM_CTS;
284 return mctrl;
285 }
287 static void siu_stop_tx(struct uart_port *port)
288 {
289 unsigned long flags;
290 uint8_t ier;
292 spin_lock_irqsave(&port->lock, flags);
294 ier = siu_read(port, UART_IER);
295 ier &= ~UART_IER_THRI;
296 siu_write(port, UART_IER, ier);
298 spin_unlock_irqrestore(&port->lock, flags);
299 }
301 static void siu_start_tx(struct uart_port *port)
302 {
303 unsigned long flags;
304 uint8_t ier;
306 spin_lock_irqsave(&port->lock, flags);
308 ier = siu_read(port, UART_IER);
309 ier |= UART_IER_THRI;
310 siu_write(port, UART_IER, ier);
312 spin_unlock_irqrestore(&port->lock, flags);
313 }
315 static void siu_stop_rx(struct uart_port *port)
316 {
317 unsigned long flags;
318 uint8_t ier;
320 spin_lock_irqsave(&port->lock, flags);
322 ier = siu_read(port, UART_IER);
323 ier &= ~UART_IER_RLSI;
324 siu_write(port, UART_IER, ier);
326 port->read_status_mask &= ~UART_LSR_DR;
328 spin_unlock_irqrestore(&port->lock, flags);
329 }
331 static void siu_enable_ms(struct uart_port *port)
332 {
333 unsigned long flags;
334 uint8_t ier;
336 spin_lock_irqsave(&port->lock, flags);
338 ier = siu_read(port, UART_IER);
339 ier |= UART_IER_MSI;
340 siu_write(port, UART_IER, ier);
342 spin_unlock_irqrestore(&port->lock, flags);
343 }
345 static void siu_break_ctl(struct uart_port *port, int ctl)
346 {
347 unsigned long flags;
348 uint8_t lcr;
350 spin_lock_irqsave(&port->lock, flags);
352 lcr = siu_read(port, UART_LCR);
353 if (ctl == -1)
354 lcr |= UART_LCR_SBC;
355 else
356 lcr &= ~UART_LCR_SBC;
357 siu_write(port, UART_LCR, lcr);
359 spin_unlock_irqrestore(&port->lock, flags);
360 }
362 static inline void receive_chars(struct uart_port *port, uint8_t *status,
363 struct pt_regs *regs)
364 {
365 struct tty_struct *tty;
366 uint8_t lsr, ch;
367 char flag;
368 int max_count = RX_MAX_COUNT;
370 tty = port->info->tty;
371 lsr = *status;
373 do {
374 ch = siu_read(port, UART_RX);
375 port->icount.rx++;
376 flag = TTY_NORMAL;
378 #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
379 lsr |= lsr_break_flag[port->line];
380 lsr_break_flag[port->line] = 0;
381 #endif
382 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE |
383 UART_LSR_PE | UART_LSR_OE))) {
384 if (lsr & UART_LSR_BI) {
385 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
386 port->icount.brk++;
388 if (uart_handle_break(port))
389 goto ignore_char;
390 }
392 if (lsr & UART_LSR_FE)
393 port->icount.frame++;
394 if (lsr & UART_LSR_PE)
395 port->icount.parity++;
396 if (lsr & UART_LSR_OE)
397 port->icount.overrun++;
399 lsr &= port->read_status_mask;
400 if (lsr & UART_LSR_BI)
401 flag = TTY_BREAK;
402 if (lsr & UART_LSR_FE)
403 flag = TTY_FRAME;
404 if (lsr & UART_LSR_PE)
405 flag = TTY_PARITY;
406 }
408 if (uart_handle_sysrq_char(port, ch, regs))
409 goto ignore_char;
411 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
413 ignore_char:
414 lsr = siu_read(port, UART_LSR);
415 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
417 tty_flip_buffer_push(tty);
419 *status = lsr;
420 }
422 static inline void check_modem_status(struct uart_port *port)
423 {
424 uint8_t msr;
426 msr = siu_read(port, UART_MSR);
427 if ((msr & UART_MSR_ANY_DELTA) == 0)
428 return;
429 if (msr & UART_MSR_DDCD)
430 uart_handle_dcd_change(port, msr & UART_MSR_DCD);
431 if (msr & UART_MSR_TERI)
432 port->icount.rng++;
433 if (msr & UART_MSR_DDSR)
434 port->icount.dsr++;
435 if (msr & UART_MSR_DCTS)
436 uart_handle_cts_change(port, msr & UART_MSR_CTS);
438 wake_up_interruptible(&port->info->delta_msr_wait);
439 }
441 static inline void transmit_chars(struct uart_port *port)
442 {
443 struct circ_buf *xmit;
444 int max_count = TX_MAX_COUNT;
446 xmit = &port->info->xmit;
448 if (port->x_char) {
449 siu_write(port, UART_TX, port->x_char);
450 port->icount.tx++;
451 port->x_char = 0;
452 return;
453 }
455 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
456 siu_stop_tx(port);
457 return;
458 }
460 do {
461 siu_write(port, UART_TX, xmit->buf[xmit->tail]);
462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
463 port->icount.tx++;
464 if (uart_circ_empty(xmit))
465 break;
466 } while (max_count-- > 0);
468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
469 uart_write_wakeup(port);
471 if (uart_circ_empty(xmit))
472 siu_stop_tx(port);
473 }
475 static irqreturn_t siu_interrupt(int irq, void *dev_id, struct pt_regs *regs)
476 {
477 struct uart_port *port;
478 uint8_t iir, lsr;
480 port = (struct uart_port *)dev_id;
482 iir = siu_read(port, UART_IIR);
483 if (iir & UART_IIR_NO_INT)
484 return IRQ_NONE;
486 lsr = siu_read(port, UART_LSR);
487 if (lsr & UART_LSR_DR)
488 receive_chars(port, &lsr, regs);
490 check_modem_status(port);
492 if (lsr & UART_LSR_THRE)
493 transmit_chars(port);
495 return IRQ_HANDLED;
496 }
498 static int siu_startup(struct uart_port *port)
499 {
500 int retval;
502 if (port->membase == NULL)
503 return -ENODEV;
505 siu_clear_fifo(port);
507 (void)siu_read(port, UART_LSR);
508 (void)siu_read(port, UART_RX);
509 (void)siu_read(port, UART_IIR);
510 (void)siu_read(port, UART_MSR);
512 if (siu_read(port, UART_LSR) == 0xff)
513 return -ENODEV;
515 retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
516 if (retval)
517 return retval;
519 if (port->type == PORT_VR41XX_DSIU)
520 vr41xx_enable_dsiuint(DSIUINT_ALL);
522 siu_write(port, UART_LCR, UART_LCR_WLEN8);
524 spin_lock_irq(&port->lock);
525 siu_set_mctrl(port, port->mctrl);
526 spin_unlock_irq(&port->lock);
528 siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
530 (void)siu_read(port, UART_LSR);
531 (void)siu_read(port, UART_RX);
532 (void)siu_read(port, UART_IIR);
533 (void)siu_read(port, UART_MSR);
535 return 0;
536 }
538 static void siu_shutdown(struct uart_port *port)
539 {
540 unsigned long flags;
541 uint8_t lcr;
543 siu_write(port, UART_IER, 0);
545 spin_lock_irqsave(&port->lock, flags);
547 port->mctrl &= ~TIOCM_OUT2;
548 siu_set_mctrl(port, port->mctrl);
550 spin_unlock_irqrestore(&port->lock, flags);
552 lcr = siu_read(port, UART_LCR);
553 lcr &= ~UART_LCR_SBC;
554 siu_write(port, UART_LCR, lcr);
556 siu_clear_fifo(port);
558 (void)siu_read(port, UART_RX);
560 if (port->type == PORT_VR41XX_DSIU)
561 vr41xx_disable_dsiuint(DSIUINT_ALL);
563 free_irq(port->irq, port);
564 }
566 static void siu_set_termios(struct uart_port *port, struct termios *new,
567 struct termios *old)
568 {
569 tcflag_t c_cflag, c_iflag;
570 uint8_t lcr, fcr, ier;
571 unsigned int baud, quot;
572 unsigned long flags;
574 c_cflag = new->c_cflag;
575 switch (c_cflag & CSIZE) {
576 case CS5:
577 lcr = UART_LCR_WLEN5;
578 break;
579 case CS6:
580 lcr = UART_LCR_WLEN6;
581 break;
582 case CS7:
583 lcr = UART_LCR_WLEN7;
584 break;
585 default:
586 lcr = UART_LCR_WLEN8;
587 break;
588 }
590 if (c_cflag & CSTOPB)
591 lcr |= UART_LCR_STOP;
592 if (c_cflag & PARENB)
593 lcr |= UART_LCR_PARITY;
594 if ((c_cflag & PARODD) != PARODD)
595 lcr |= UART_LCR_EPAR;
596 if (c_cflag & CMSPAR)
597 lcr |= UART_LCR_SPAR;
599 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
600 quot = uart_get_divisor(port, baud);
602 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
604 spin_lock_irqsave(&port->lock, flags);
606 uart_update_timeout(port, c_cflag, baud);
608 c_iflag = new->c_iflag;
610 port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
611 if (c_iflag & INPCK)
612 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
613 if (c_iflag & (BRKINT | PARMRK))
614 port->read_status_mask |= UART_LSR_BI;
616 port->ignore_status_mask = 0;
617 if (c_iflag & IGNPAR)
618 port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
619 if (c_iflag & IGNBRK) {
620 port->ignore_status_mask |= UART_LSR_BI;
621 if (c_iflag & IGNPAR)
622 port->ignore_status_mask |= UART_LSR_OE;
623 }
625 if ((c_cflag & CREAD) == 0)
626 port->ignore_status_mask |= UART_LSR_DR;
628 ier = siu_read(port, UART_IER);
629 ier &= ~UART_IER_MSI;
630 if (UART_ENABLE_MS(port, c_cflag))
631 ier |= UART_IER_MSI;
632 siu_write(port, UART_IER, ier);
634 siu_write(port, UART_LCR, lcr | UART_LCR_DLAB);
636 siu_write(port, UART_DLL, (uint8_t)quot);
637 siu_write(port, UART_DLM, (uint8_t)(quot >> 8));
639 siu_write(port, UART_LCR, lcr);
641 siu_write(port, UART_FCR, fcr);
643 siu_set_mctrl(port, port->mctrl);
645 spin_unlock_irqrestore(&port->lock, flags);
646 }
648 static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
649 {
650 switch (state) {
651 case 0:
652 switch (port->type) {
653 case PORT_VR41XX_SIU:
654 vr41xx_supply_clock(SIU_CLOCK);
655 break;
656 case PORT_VR41XX_DSIU:
657 vr41xx_supply_clock(DSIU_CLOCK);
658 break;
659 }
660 break;
661 case 3:
662 switch (port->type) {
663 case PORT_VR41XX_SIU:
664 vr41xx_mask_clock(SIU_CLOCK);
665 break;
666 case PORT_VR41XX_DSIU:
667 vr41xx_mask_clock(DSIU_CLOCK);
668 break;
669 }
670 break;
671 }
672 }
674 static const char *siu_type(struct uart_port *port)
675 {
676 return siu_type_name(port);
677 }
679 static void siu_release_port(struct uart_port *port)
680 {
681 unsigned long size;
683 if (port->flags & UPF_IOREMAP) {
684 iounmap(port->membase);
685 port->membase = NULL;
686 }
688 size = siu_port_size(port);
689 release_mem_region(port->mapbase, size);
690 }
692 static int siu_request_port(struct uart_port *port)
693 {
694 unsigned long size;
695 struct resource *res;
697 size = siu_port_size(port);
698 res = request_mem_region(port->mapbase, size, siu_type_name(port));
699 if (res == NULL)
700 return -EBUSY;
702 if (port->flags & UPF_IOREMAP) {
703 port->membase = ioremap(port->mapbase, size);
704 if (port->membase == NULL) {
705 release_resource(res);
706 return -ENOMEM;
707 }
708 }
710 return 0;
711 }
713 static void siu_config_port(struct uart_port *port, int flags)
714 {
715 if (flags & UART_CONFIG_TYPE) {
716 port->type = siu_check_type(port);
717 (void)siu_request_port(port);
718 }
719 }
721 static int siu_verify_port(struct uart_port *port, struct serial_struct *serial)
722 {
723 if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU)
724 return -EINVAL;
725 if (port->irq != serial->irq)
726 return -EINVAL;
727 if (port->iotype != serial->io_type)
728 return -EINVAL;
729 if (port->mapbase != (unsigned long)serial->iomem_base)
730 return -EINVAL;
732 return 0;
733 }
735 static struct uart_ops siu_uart_ops = {
736 .tx_empty = siu_tx_empty,
737 .set_mctrl = siu_set_mctrl,
738 .get_mctrl = siu_get_mctrl,
739 .stop_tx = siu_stop_tx,
740 .start_tx = siu_start_tx,
741 .stop_rx = siu_stop_rx,
742 .enable_ms = siu_enable_ms,
743 .break_ctl = siu_break_ctl,
744 .startup = siu_startup,
745 .shutdown = siu_shutdown,
746 .set_termios = siu_set_termios,
747 .pm = siu_pm,
748 .type = siu_type,
749 .release_port = siu_release_port,
750 .request_port = siu_request_port,
751 .config_port = siu_config_port,
752 .verify_port = siu_verify_port,
753 };
755 static int siu_init_ports(void)
756 {
757 const struct siu_port *siu;
758 struct uart_port *port;
759 int i, num;
761 switch (current_cpu_data.cputype) {
762 case CPU_VR4111:
763 case CPU_VR4121:
764 siu = siu_type1_ports;
765 break;
766 case CPU_VR4122:
767 case CPU_VR4131:
768 case CPU_VR4133:
769 siu = siu_type2_ports;
770 break;
771 default:
772 return 0;
773 }
775 port = siu_uart_ports;
776 num = siu_probe_ports();
777 for (i = 0; i < num; i++) {
778 spin_lock_init(&port->lock);
779 port->irq = siu->irq;
780 port->uartclk = SIU_BAUD_BASE * 16;
781 port->fifosize = 16;
782 port->regshift = 0;
783 port->iotype = UPIO_MEM;
784 port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
785 port->type = siu->type;
786 port->line = i;
787 port->mapbase = siu->start;
788 siu++;
789 port++;
790 }
792 return num;
793 }
795 #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
797 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
799 static void wait_for_xmitr(struct uart_port *port)
800 {
801 int timeout = 10000;
802 uint8_t lsr, msr;
804 do {
805 lsr = siu_read(port, UART_LSR);
806 if (lsr & UART_LSR_BI)
807 lsr_break_flag[port->line] = UART_LSR_BI;
809 if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
810 break;
811 } while (timeout-- > 0);
813 if (port->flags & UPF_CONS_FLOW) {
814 timeout = 1000000;
816 do {
817 msr = siu_read(port, UART_MSR);
818 if ((msr & UART_MSR_CTS) != 0)
819 break;
820 } while (timeout-- > 0);
821 }
822 }
824 static void siu_console_putchar(struct uart_port *port, int ch)
825 {
826 wait_for_xmitr(port);
827 siu_write(port, UART_TX, ch);
828 }
830 static void siu_console_write(struct console *con, const char *s, unsigned count)
831 {
832 struct uart_port *port;
833 uint8_t ier;
835 port = &siu_uart_ports[con->index];
837 ier = siu_read(port, UART_IER);
838 siu_write(port, UART_IER, 0);
840 uart_console_write(port, s, count, siu_console_putchar);
842 wait_for_xmitr(port);
843 siu_write(port, UART_IER, ier);
844 }
846 static int siu_console_setup(struct console *con, char *options)
847 {
848 struct uart_port *port;
849 int baud = 9600;
850 int parity = 'n';
851 int bits = 8;
852 int flow = 'n';
854 if (con->index >= SIU_PORTS_MAX)
855 con->index = 0;
857 port = &siu_uart_ports[con->index];
858 if (port->membase == NULL) {
859 if (port->mapbase == 0)
860 return -ENODEV;
861 port->membase = ioremap(port->mapbase, siu_port_size(port));
862 }
864 vr41xx_select_siu_interface(SIU_INTERFACE_RS232C);
866 if (options != NULL)
867 uart_parse_options(options, &baud, &parity, &bits, &flow);
869 return uart_set_options(port, con, baud, parity, bits, flow);
870 }
872 static struct uart_driver siu_uart_driver;
874 static struct console siu_console = {
875 .name = "ttyVR",
876 .write = siu_console_write,
877 .device = uart_console_device,
878 .setup = siu_console_setup,
879 .flags = CON_PRINTBUFFER,
880 .index = -1,
881 .data = &siu_uart_driver,
882 };
884 static int __devinit siu_console_init(void)
885 {
886 struct uart_port *port;
887 int num, i;
889 num = siu_init_ports();
890 if (num <= 0)
891 return -ENODEV;
893 for (i = 0; i < num; i++) {
894 port = &siu_uart_ports[i];
895 port->ops = &siu_uart_ops;
896 }
898 register_console(&siu_console);
900 return 0;
901 }
903 console_initcall(siu_console_init);
905 #define SERIAL_VR41XX_CONSOLE &siu_console
906 #else
907 #define SERIAL_VR41XX_CONSOLE NULL
908 #endif
910 static struct uart_driver siu_uart_driver = {
911 .owner = THIS_MODULE,
912 .driver_name = "SIU",
913 .dev_name = "ttyVR",
914 .major = SIU_MAJOR,
915 .minor = SIU_MINOR_BASE,
916 .cons = SERIAL_VR41XX_CONSOLE,
917 };
919 static int __devinit siu_probe(struct platform_device *dev)
920 {
921 struct uart_port *port;
922 int num, i, retval;
924 num = siu_init_ports();
925 if (num <= 0)
926 return -ENODEV;
928 siu_uart_driver.nr = num;
929 retval = uart_register_driver(&siu_uart_driver);
930 if (retval)
931 return retval;
933 for (i = 0; i < num; i++) {
934 port = &siu_uart_ports[i];
935 port->ops = &siu_uart_ops;
936 port->dev = &dev->dev;
938 retval = uart_add_one_port(&siu_uart_driver, port);
939 if (retval < 0) {
940 port->dev = NULL;
941 break;
942 }
943 }
945 if (i == 0 && retval < 0) {
946 uart_unregister_driver(&siu_uart_driver);
947 return retval;
948 }
950 return 0;
951 }
953 static int __devexit siu_remove(struct platform_device *dev)
954 {
955 struct uart_port *port;
956 int i;
958 for (i = 0; i < siu_uart_driver.nr; i++) {
959 port = &siu_uart_ports[i];
960 if (port->dev == &dev->dev) {
961 uart_remove_one_port(&siu_uart_driver, port);
962 port->dev = NULL;
963 }
964 }
966 uart_unregister_driver(&siu_uart_driver);
968 return 0;
969 }
971 static int siu_suspend(struct platform_device *dev, pm_message_t state)
972 {
973 struct uart_port *port;
974 int i;
976 for (i = 0; i < siu_uart_driver.nr; i++) {
977 port = &siu_uart_ports[i];
978 if ((port->type == PORT_VR41XX_SIU ||
979 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
980 uart_suspend_port(&siu_uart_driver, port);
982 }
984 return 0;
985 }
987 static int siu_resume(struct platform_device *dev)
988 {
989 struct uart_port *port;
990 int i;
992 for (i = 0; i < siu_uart_driver.nr; i++) {
993 port = &siu_uart_ports[i];
994 if ((port->type == PORT_VR41XX_SIU ||
995 port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
996 uart_resume_port(&siu_uart_driver, port);
997 }
999 return 0;
1002 static struct platform_device *siu_platform_device;
1004 static struct platform_driver siu_device_driver = {
1005 .probe = siu_probe,
1006 .remove = __devexit_p(siu_remove),
1007 .suspend = siu_suspend,
1008 .resume = siu_resume,
1009 .driver = {
1010 .name = "SIU",
1011 .owner = THIS_MODULE,
1012 },
1013 };
1015 static int __init vr41xx_siu_init(void)
1017 int retval;
1019 siu_platform_device = platform_device_alloc("SIU", -1);
1020 if (!siu_platform_device)
1021 return -ENOMEM;
1023 retval = platform_device_add(siu_platform_device);
1024 if (retval < 0) {
1025 platform_device_put(siu_platform_device);
1026 return retval;
1029 retval = platform_driver_register(&siu_device_driver);
1030 if (retval < 0)
1031 platform_device_unregister(siu_platform_device);
1033 return retval;
1036 static void __exit vr41xx_siu_exit(void)
1038 platform_driver_unregister(&siu_device_driver);
1039 platform_device_unregister(siu_platform_device);
1042 module_init(vr41xx_siu_init);
1043 module_exit(vr41xx_siu_exit);