ia64/linux-2.6.18-xen.hg

view drivers/serial/sunzilog.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 #ifndef _SUNZILOG_H
2 #define _SUNZILOG_H
4 struct zilog_channel {
5 volatile unsigned char control;
6 volatile unsigned char __pad1;
7 volatile unsigned char data;
8 volatile unsigned char __pad2;
9 };
11 struct zilog_layout {
12 struct zilog_channel channelB;
13 struct zilog_channel channelA;
14 };
16 #define NUM_ZSREGS 16
18 /* Conversion routines to/from brg time constants from/to bits
19 * per second.
20 */
21 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
22 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
24 /* The Zilog register set */
26 #define FLAG 0x7e
28 /* Write Register 0 */
29 #define R0 0 /* Register selects */
30 #define R1 1
31 #define R2 2
32 #define R3 3
33 #define R4 4
34 #define R5 5
35 #define R6 6
36 #define R7 7
37 #define R8 8
38 #define R9 9
39 #define R10 10
40 #define R11 11
41 #define R12 12
42 #define R13 13
43 #define R14 14
44 #define R15 15
46 #define NULLCODE 0 /* Null Code */
47 #define POINT_HIGH 0x8 /* Select upper half of registers */
48 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
49 #define SEND_ABORT 0x18 /* HDLC Abort */
50 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
51 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
52 #define ERR_RES 0x30 /* Error Reset */
53 #define RES_H_IUS 0x38 /* Reset highest IUS */
55 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
56 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
57 #define RES_EOM_L 0xC0 /* Reset EOM latch */
59 /* Write Register 1 */
61 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
62 #define TxINT_ENAB 0x2 /* Tx Int Enable */
63 #define PAR_SPEC 0x4 /* Parity is special condition */
65 #define RxINT_DISAB 0 /* Rx Int Disable */
66 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
67 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
68 #define INT_ERR_Rx 0x18 /* Int on error only */
69 #define RxINT_MASK 0x18
71 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
72 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
73 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
75 /* Write Register #2 (Interrupt Vector) */
77 /* Write Register 3 */
79 #define RxENAB 0x1 /* Rx Enable */
80 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
81 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
82 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
83 #define ENT_HM 0x10 /* Enter Hunt Mode */
84 #define AUTO_ENAB 0x20 /* Auto Enables */
85 #define Rx5 0x0 /* Rx 5 Bits/Character */
86 #define Rx7 0x40 /* Rx 7 Bits/Character */
87 #define Rx6 0x80 /* Rx 6 Bits/Character */
88 #define Rx8 0xc0 /* Rx 8 Bits/Character */
89 #define RxN_MASK 0xc0
91 /* Write Register 4 */
93 #define PAR_ENAB 0x1 /* Parity Enable */
94 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
96 #define SYNC_ENAB 0 /* Sync Modes Enable */
97 #define SB1 0x4 /* 1 stop bit/char */
98 #define SB15 0x8 /* 1.5 stop bits/char */
99 #define SB2 0xc /* 2 stop bits/char */
101 #define MONSYNC 0 /* 8 Bit Sync character */
102 #define BISYNC 0x10 /* 16 bit sync character */
103 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
104 #define EXTSYNC 0x30 /* External Sync Mode */
106 #define X1CLK 0x0 /* x1 clock mode */
107 #define X16CLK 0x40 /* x16 clock mode */
108 #define X32CLK 0x80 /* x32 clock mode */
109 #define X64CLK 0xC0 /* x64 clock mode */
110 #define XCLK_MASK 0xC0
112 /* Write Register 5 */
114 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
115 #define RTS 0x2 /* RTS */
116 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
117 #define TxENAB 0x8 /* Tx Enable */
118 #define SND_BRK 0x10 /* Send Break */
119 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
120 #define Tx7 0x20 /* Tx 7 bits/character */
121 #define Tx6 0x40 /* Tx 6 bits/character */
122 #define Tx8 0x60 /* Tx 8 bits/character */
123 #define TxN_MASK 0x60
124 #define DTR 0x80 /* DTR */
126 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
128 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
130 /* Write Register 8 (transmit buffer) */
132 /* Write Register 9 (Master interrupt control) */
133 #define VIS 1 /* Vector Includes Status */
134 #define NV 2 /* No Vector */
135 #define DLC 4 /* Disable Lower Chain */
136 #define MIE 8 /* Master Interrupt Enable */
137 #define STATHI 0x10 /* Status high */
138 #define NORESET 0 /* No reset on write to R9 */
139 #define CHRB 0x40 /* Reset channel B */
140 #define CHRA 0x80 /* Reset channel A */
141 #define FHWRES 0xc0 /* Force hardware reset */
143 /* Write Register 10 (misc control bits) */
144 #define BIT6 1 /* 6 bit/8bit sync */
145 #define LOOPMODE 2 /* SDLC Loop mode */
146 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
147 #define MARKIDLE 8 /* Mark/flag on idle */
148 #define GAOP 0x10 /* Go active on poll */
149 #define NRZ 0 /* NRZ mode */
150 #define NRZI 0x20 /* NRZI mode */
151 #define FM1 0x40 /* FM1 (transition = 1) */
152 #define FM0 0x60 /* FM0 (transition = 0) */
153 #define CRCPS 0x80 /* CRC Preset I/O */
155 /* Write Register 11 (Clock Mode control) */
156 #define TRxCXT 0 /* TRxC = Xtal output */
157 #define TRxCTC 1 /* TRxC = Transmit clock */
158 #define TRxCBR 2 /* TRxC = BR Generator Output */
159 #define TRxCDP 3 /* TRxC = DPLL output */
160 #define TRxCOI 4 /* TRxC O/I */
161 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
162 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
163 #define TCBR 0x10 /* Transmit clock = BR Generator output */
164 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
165 #define RCRTxCP 0 /* Receive clock = RTxC pin */
166 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
167 #define RCBR 0x40 /* Receive clock = BR Generator output */
168 #define RCDPLL 0x60 /* Receive clock = DPLL output */
169 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
171 /* Write Register 12 (lower byte of baud rate generator time constant) */
173 /* Write Register 13 (upper byte of baud rate generator time constant) */
175 /* Write Register 14 (Misc control bits) */
176 #define BRENAB 1 /* Baud rate generator enable */
177 #define BRSRC 2 /* Baud rate generator source */
178 #define DTRREQ 4 /* DTR/Request function */
179 #define AUTOECHO 8 /* Auto Echo */
180 #define LOOPBAK 0x10 /* Local loopback */
181 #define SEARCH 0x20 /* Enter search mode */
182 #define RMC 0x40 /* Reset missing clock */
183 #define DISDPLL 0x60 /* Disable DPLL */
184 #define SSBR 0x80 /* Set DPLL source = BR generator */
185 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
186 #define SFMM 0xc0 /* Set FM mode */
187 #define SNRZI 0xe0 /* Set NRZI mode */
189 /* Write Register 15 (external/status interrupt control) */
190 #define ZCIE 2 /* Zero count IE */
191 #define DCDIE 8 /* DCD IE */
192 #define SYNCIE 0x10 /* Sync/hunt IE */
193 #define CTSIE 0x20 /* CTS IE */
194 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
195 #define BRKIE 0x80 /* Break/Abort IE */
198 /* Read Register 0 */
199 #define Rx_CH_AV 0x1 /* Rx Character Available */
200 #define ZCOUNT 0x2 /* Zero count */
201 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
202 #define DCD 0x8 /* DCD */
203 #define SYNC 0x10 /* Sync/hunt */
204 #define CTS 0x20 /* CTS */
205 #define TxEOM 0x40 /* Tx underrun */
206 #define BRK_ABRT 0x80 /* Break/Abort */
208 /* Read Register 1 */
209 #define ALL_SNT 0x1 /* All sent */
210 /* Residue Data for 8 Rx bits/char programmed */
211 #define RES3 0x8 /* 0/3 */
212 #define RES4 0x4 /* 0/4 */
213 #define RES5 0xc /* 0/5 */
214 #define RES6 0x2 /* 0/6 */
215 #define RES7 0xa /* 0/7 */
216 #define RES8 0x6 /* 0/8 */
217 #define RES18 0xe /* 1/8 */
218 #define RES28 0x0 /* 2/8 */
219 /* Special Rx Condition Interrupts */
220 #define PAR_ERR 0x10 /* Parity error */
221 #define Rx_OVR 0x20 /* Rx Overrun Error */
222 #define CRC_ERR 0x40 /* CRC/Framing Error */
223 #define END_FR 0x80 /* End of Frame (SDLC) */
225 /* Read Register 2 (channel b only) - Interrupt vector */
226 #define CHB_Tx_EMPTY 0x00
227 #define CHB_EXT_STAT 0x02
228 #define CHB_Rx_AVAIL 0x04
229 #define CHB_SPECIAL 0x06
230 #define CHA_Tx_EMPTY 0x08
231 #define CHA_EXT_STAT 0x0a
232 #define CHA_Rx_AVAIL 0x0c
233 #define CHA_SPECIAL 0x0e
234 #define STATUS_MASK 0x0e
236 /* Read Register 3 (interrupt pending register) ch a only */
237 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
238 #define CHBTxIP 0x2 /* Channel B Tx IP */
239 #define CHBRxIP 0x4 /* Channel B Rx IP */
240 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
241 #define CHATxIP 0x10 /* Channel A Tx IP */
242 #define CHARxIP 0x20 /* Channel A Rx IP */
244 /* Read Register 8 (receive data register) */
246 /* Read Register 10 (misc status bits) */
247 #define ONLOOP 2 /* On loop */
248 #define LOOPSEND 0x10 /* Loop sending */
249 #define CLK2MIS 0x40 /* Two clocks missing */
250 #define CLK1MIS 0x80 /* One clock missing */
252 /* Read Register 12 (lower byte of baud rate generator constant) */
254 /* Read Register 13 (upper byte of baud rate generator constant) */
256 /* Read Register 15 (value of WR 15) */
258 /* Misc macros */
259 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
260 udelay(5); } while(0)
262 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
263 udelay(5); } while(0)
265 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
266 udelay(2); \
267 sbus_readb(&channel->data); \
268 udelay(2); \
269 sbus_readb(&channel->data); \
270 udelay(2); } while(0)
272 #endif /* _SUNZILOG_H */