ia64/linux-2.6.18-xen.hg

view drivers/serial/sunsab.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
16 */
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/errno.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/major.h>
25 #include <linux/string.h>
26 #include <linux/ptrace.h>
27 #include <linux/ioport.h>
28 #include <linux/circ_buf.h>
29 #include <linux/serial.h>
30 #include <linux/sysrq.h>
31 #include <linux/console.h>
32 #include <linux/spinlock.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/of_device.h>
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
46 #include <linux/serial_core.h>
48 #include "suncore.h"
49 #include "sunsab.h"
51 struct uart_sunsab_port {
52 struct uart_port port; /* Generic UART port */
53 union sab82532_async_regs __iomem *regs; /* Chip registers */
54 unsigned long irqflags; /* IRQ state flags */
55 int dsr; /* Current DSR state */
56 unsigned int cec_timeout; /* Chip poll timeout... */
57 unsigned int tec_timeout; /* likewise */
58 unsigned char interrupt_mask0;/* ISR0 masking */
59 unsigned char interrupt_mask1;/* ISR1 masking */
60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
62 int type; /* SAB82532 version */
64 /* Setting configuration bits while the transmitter is active
65 * can cause garbage characters to get emitted by the chip.
66 * Therefore, we cache such writes here and do the real register
67 * write the next time the transmitter becomes idle.
68 */
69 unsigned int cached_ebrg;
70 unsigned char cached_mode;
71 unsigned char cached_pvr;
72 unsigned char cached_dafo;
73 };
75 /*
76 * This assumes you have a 29.4912 MHz clock for your UART.
77 */
78 #define SAB_BASE_BAUD ( 29491200 / 16 )
80 static char *sab82532_version[16] = {
81 "V1.0", "V2.0", "V3.2", "V(0x03)",
82 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
83 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
84 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
85 };
87 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
88 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
91 #define SAB82532_XMIT_FIFO_SIZE 32
93 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
94 {
95 int timeout = up->tec_timeout;
97 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
98 udelay(1);
99 }
101 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
102 {
103 int timeout = up->cec_timeout;
105 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
106 udelay(1);
107 }
109 static struct tty_struct *
110 receive_chars(struct uart_sunsab_port *up,
111 union sab82532_irq_status *stat,
112 struct pt_regs *regs)
113 {
114 struct tty_struct *tty = NULL;
115 unsigned char buf[32];
116 int saw_console_brk = 0;
117 int free_fifo = 0;
118 int count = 0;
119 int i;
121 if (up->port.info != NULL) /* Unopened serial console */
122 tty = up->port.info->tty;
124 /* Read number of BYTES (Character + Status) available. */
125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126 count = SAB82532_RECV_FIFO_SIZE;
127 free_fifo++;
128 }
130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
132 free_fifo++;
133 }
135 /* Issue a FIFO read command in case we where idle. */
136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
137 sunsab_cec_wait(up);
138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
139 return tty;
140 }
142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
143 free_fifo++;
145 /* Read the FIFO. */
146 for (i = 0; i < count; i++)
147 buf[i] = readb(&up->regs->r.rfifo[i]);
149 /* Issue Receive Message Complete command. */
150 if (free_fifo) {
151 sunsab_cec_wait(up);
152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
153 }
155 /* Count may be zero for BRK, so we check for it here */
156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157 (up->port.line == up->port.cons->index))
158 saw_console_brk = 1;
160 for (i = 0; i < count; i++) {
161 unsigned char ch = buf[i], flag;
163 if (tty == NULL) {
164 uart_handle_sysrq_char(&up->port, ch, regs);
165 continue;
166 }
168 flag = TTY_NORMAL;
169 up->port.icount.rx++;
171 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
172 SAB82532_ISR0_FERR |
173 SAB82532_ISR0_RFO)) ||
174 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
175 /*
176 * For statistics only
177 */
178 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
179 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
180 SAB82532_ISR0_FERR);
181 up->port.icount.brk++;
182 /*
183 * We do the SysRQ and SAK checking
184 * here because otherwise the break
185 * may get masked by ignore_status_mask
186 * or read_status_mask.
187 */
188 if (uart_handle_break(&up->port))
189 continue;
190 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
191 up->port.icount.parity++;
192 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
193 up->port.icount.frame++;
194 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
195 up->port.icount.overrun++;
197 /*
198 * Mask off conditions which should be ingored.
199 */
200 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
201 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
203 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
204 flag = TTY_BREAK;
205 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
206 flag = TTY_PARITY;
207 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
208 flag = TTY_FRAME;
209 }
211 if (uart_handle_sysrq_char(&up->port, ch, regs))
212 continue;
214 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
215 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
216 tty_insert_flip_char(tty, ch, flag);
217 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
218 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
219 }
221 if (saw_console_brk)
222 sun_do_break();
224 return tty;
225 }
227 static void sunsab_stop_tx(struct uart_port *);
228 static void sunsab_tx_idle(struct uart_sunsab_port *);
230 static void transmit_chars(struct uart_sunsab_port *up,
231 union sab82532_irq_status *stat)
232 {
233 struct circ_buf *xmit = &up->port.info->xmit;
234 int i;
236 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
237 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
238 writeb(up->interrupt_mask1, &up->regs->w.imr1);
239 set_bit(SAB82532_ALLS, &up->irqflags);
240 }
242 #if 0 /* bde@nwlink.com says this check causes problems */
243 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
244 return;
245 #endif
247 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
248 return;
250 set_bit(SAB82532_XPR, &up->irqflags);
251 sunsab_tx_idle(up);
253 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
254 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
255 writeb(up->interrupt_mask1, &up->regs->w.imr1);
256 return;
257 }
259 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
260 writeb(up->interrupt_mask1, &up->regs->w.imr1);
261 clear_bit(SAB82532_ALLS, &up->irqflags);
263 /* Stuff 32 bytes into Transmit FIFO. */
264 clear_bit(SAB82532_XPR, &up->irqflags);
265 for (i = 0; i < up->port.fifosize; i++) {
266 writeb(xmit->buf[xmit->tail],
267 &up->regs->w.xfifo[i]);
268 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
269 up->port.icount.tx++;
270 if (uart_circ_empty(xmit))
271 break;
272 }
274 /* Issue a Transmit Frame command. */
275 sunsab_cec_wait(up);
276 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
278 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
279 uart_write_wakeup(&up->port);
281 if (uart_circ_empty(xmit))
282 sunsab_stop_tx(&up->port);
283 }
285 static void check_status(struct uart_sunsab_port *up,
286 union sab82532_irq_status *stat)
287 {
288 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
289 uart_handle_dcd_change(&up->port,
290 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
292 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
293 uart_handle_cts_change(&up->port,
294 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
296 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
297 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
298 up->port.icount.dsr++;
299 }
301 wake_up_interruptible(&up->port.info->delta_msr_wait);
302 }
304 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
305 {
306 struct uart_sunsab_port *up = dev_id;
307 struct tty_struct *tty;
308 union sab82532_irq_status status;
309 unsigned long flags;
311 spin_lock_irqsave(&up->port.lock, flags);
313 status.stat = 0;
314 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
315 status.sreg.isr0 = readb(&up->regs->r.isr0);
316 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
317 status.sreg.isr1 = readb(&up->regs->r.isr1);
319 tty = NULL;
320 if (status.stat) {
321 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
322 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
323 (status.sreg.isr1 & SAB82532_ISR1_BRK))
324 tty = receive_chars(up, &status, regs);
325 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
326 (status.sreg.isr1 & SAB82532_ISR1_CSC))
327 check_status(up, &status);
328 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
329 transmit_chars(up, &status);
330 }
332 spin_unlock(&up->port.lock);
334 if (tty)
335 tty_flip_buffer_push(tty);
337 up++;
339 spin_lock(&up->port.lock);
341 status.stat = 0;
342 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
343 status.sreg.isr0 = readb(&up->regs->r.isr0);
344 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
345 status.sreg.isr1 = readb(&up->regs->r.isr1);
347 tty = NULL;
348 if (status.stat) {
349 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
350 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
351 (status.sreg.isr1 & SAB82532_ISR1_BRK))
353 tty = receive_chars(up, &status, regs);
354 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
355 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
356 check_status(up, &status);
357 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
358 transmit_chars(up, &status);
359 }
361 spin_unlock_irqrestore(&up->port.lock, flags);
363 if (tty)
364 tty_flip_buffer_push(tty);
366 return IRQ_HANDLED;
367 }
369 /* port->lock is not held. */
370 static unsigned int sunsab_tx_empty(struct uart_port *port)
371 {
372 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
373 int ret;
375 /* Do not need a lock for a state test like this. */
376 if (test_bit(SAB82532_ALLS, &up->irqflags))
377 ret = TIOCSER_TEMT;
378 else
379 ret = 0;
381 return ret;
382 }
384 /* port->lock held by caller. */
385 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
386 {
387 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
389 if (mctrl & TIOCM_RTS) {
390 up->cached_mode &= ~SAB82532_MODE_FRTS;
391 up->cached_mode |= SAB82532_MODE_RTS;
392 } else {
393 up->cached_mode |= (SAB82532_MODE_FRTS |
394 SAB82532_MODE_RTS);
395 }
396 if (mctrl & TIOCM_DTR) {
397 up->cached_pvr &= ~(up->pvr_dtr_bit);
398 } else {
399 up->cached_pvr |= up->pvr_dtr_bit;
400 }
402 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
403 if (test_bit(SAB82532_XPR, &up->irqflags))
404 sunsab_tx_idle(up);
405 }
407 /* port->lock is held by caller and interrupts are disabled. */
408 static unsigned int sunsab_get_mctrl(struct uart_port *port)
409 {
410 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
411 unsigned char val;
412 unsigned int result;
414 result = 0;
416 val = readb(&up->regs->r.pvr);
417 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
419 val = readb(&up->regs->r.vstr);
420 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
422 val = readb(&up->regs->r.star);
423 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
425 return result;
426 }
428 /* port->lock held by caller. */
429 static void sunsab_stop_tx(struct uart_port *port)
430 {
431 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
434 writeb(up->interrupt_mask1, &up->regs->w.imr1);
435 }
437 /* port->lock held by caller. */
438 static void sunsab_tx_idle(struct uart_sunsab_port *up)
439 {
440 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
441 u8 tmp;
443 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
444 writeb(up->cached_mode, &up->regs->rw.mode);
445 writeb(up->cached_pvr, &up->regs->rw.pvr);
446 writeb(up->cached_dafo, &up->regs->w.dafo);
448 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
449 tmp = readb(&up->regs->rw.ccr2);
450 tmp &= ~0xc0;
451 tmp |= (up->cached_ebrg >> 2) & 0xc0;
452 writeb(tmp, &up->regs->rw.ccr2);
453 }
454 }
456 /* port->lock held by caller. */
457 static void sunsab_start_tx(struct uart_port *port)
458 {
459 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
460 struct circ_buf *xmit = &up->port.info->xmit;
461 int i;
463 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
464 writeb(up->interrupt_mask1, &up->regs->w.imr1);
466 if (!test_bit(SAB82532_XPR, &up->irqflags))
467 return;
469 clear_bit(SAB82532_ALLS, &up->irqflags);
470 clear_bit(SAB82532_XPR, &up->irqflags);
472 for (i = 0; i < up->port.fifosize; i++) {
473 writeb(xmit->buf[xmit->tail],
474 &up->regs->w.xfifo[i]);
475 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
476 up->port.icount.tx++;
477 if (uart_circ_empty(xmit))
478 break;
479 }
481 /* Issue a Transmit Frame command. */
482 sunsab_cec_wait(up);
483 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
484 }
486 /* port->lock is not held. */
487 static void sunsab_send_xchar(struct uart_port *port, char ch)
488 {
489 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
490 unsigned long flags;
492 spin_lock_irqsave(&up->port.lock, flags);
494 sunsab_tec_wait(up);
495 writeb(ch, &up->regs->w.tic);
497 spin_unlock_irqrestore(&up->port.lock, flags);
498 }
500 /* port->lock held by caller. */
501 static void sunsab_stop_rx(struct uart_port *port)
502 {
503 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
505 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
506 writeb(up->interrupt_mask1, &up->regs->w.imr0);
507 }
509 /* port->lock held by caller. */
510 static void sunsab_enable_ms(struct uart_port *port)
511 {
512 /* For now we always receive these interrupts. */
513 }
515 /* port->lock is not held. */
516 static void sunsab_break_ctl(struct uart_port *port, int break_state)
517 {
518 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
519 unsigned long flags;
520 unsigned char val;
522 spin_lock_irqsave(&up->port.lock, flags);
524 val = up->cached_dafo;
525 if (break_state)
526 val |= SAB82532_DAFO_XBRK;
527 else
528 val &= ~SAB82532_DAFO_XBRK;
529 up->cached_dafo = val;
531 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
532 if (test_bit(SAB82532_XPR, &up->irqflags))
533 sunsab_tx_idle(up);
535 spin_unlock_irqrestore(&up->port.lock, flags);
536 }
538 /* port->lock is not held. */
539 static int sunsab_startup(struct uart_port *port)
540 {
541 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
542 unsigned long flags;
543 unsigned char tmp;
545 spin_lock_irqsave(&up->port.lock, flags);
547 /*
548 * Wait for any commands or immediate characters
549 */
550 sunsab_cec_wait(up);
551 sunsab_tec_wait(up);
553 /*
554 * Clear the FIFO buffers.
555 */
556 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
557 sunsab_cec_wait(up);
558 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
560 /*
561 * Clear the interrupt registers.
562 */
563 (void) readb(&up->regs->r.isr0);
564 (void) readb(&up->regs->r.isr1);
566 /*
567 * Now, initialize the UART
568 */
569 writeb(0, &up->regs->w.ccr0); /* power-down */
570 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
571 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
572 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
573 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
574 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
575 writeb(0, &up->regs->w.ccr3);
576 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
577 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
578 SAB82532_MODE_RAC);
579 writeb(up->cached_mode, &up->regs->w.mode);
580 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
582 tmp = readb(&up->regs->rw.ccr0);
583 tmp |= SAB82532_CCR0_PU; /* power-up */
584 writeb(tmp, &up->regs->rw.ccr0);
586 /*
587 * Finally, enable interrupts
588 */
589 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
590 SAB82532_IMR0_PLLA);
591 writeb(up->interrupt_mask0, &up->regs->w.imr0);
592 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
593 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
594 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
595 SAB82532_IMR1_XPR);
596 writeb(up->interrupt_mask1, &up->regs->w.imr1);
597 set_bit(SAB82532_ALLS, &up->irqflags);
598 set_bit(SAB82532_XPR, &up->irqflags);
600 spin_unlock_irqrestore(&up->port.lock, flags);
602 return 0;
603 }
605 /* port->lock is not held. */
606 static void sunsab_shutdown(struct uart_port *port)
607 {
608 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
609 unsigned long flags;
611 spin_lock_irqsave(&up->port.lock, flags);
613 /* Disable Interrupts */
614 up->interrupt_mask0 = 0xff;
615 writeb(up->interrupt_mask0, &up->regs->w.imr0);
616 up->interrupt_mask1 = 0xff;
617 writeb(up->interrupt_mask1, &up->regs->w.imr1);
619 /* Disable break condition */
620 up->cached_dafo = readb(&up->regs->rw.dafo);
621 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
622 writeb(up->cached_dafo, &up->regs->rw.dafo);
624 /* Disable Receiver */
625 up->cached_mode &= ~SAB82532_MODE_RAC;
626 writeb(up->cached_mode, &up->regs->rw.mode);
628 /*
629 * XXX FIXME
630 *
631 * If the chip is powered down here the system hangs/crashes during
632 * reboot or shutdown. This needs to be investigated further,
633 * similar behaviour occurs in 2.4 when the driver is configured
634 * as a module only. One hint may be that data is sometimes
635 * transmitted at 9600 baud during shutdown (regardless of the
636 * speed the chip was configured for when the port was open).
637 */
638 #if 0
639 /* Power Down */
640 tmp = readb(&up->regs->rw.ccr0);
641 tmp &= ~SAB82532_CCR0_PU;
642 writeb(tmp, &up->regs->rw.ccr0);
643 #endif
645 spin_unlock_irqrestore(&up->port.lock, flags);
646 }
648 /*
649 * This is used to figure out the divisor speeds.
650 *
651 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
652 *
653 * with 0 <= N < 64 and 0 <= M < 16
654 */
656 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
657 {
658 int n, m;
660 if (baud == 0) {
661 *n_ret = 0;
662 *m_ret = 0;
663 return;
664 }
666 /*
667 * We scale numbers by 10 so that we get better accuracy
668 * without having to use floating point. Here we increment m
669 * until n is within the valid range.
670 */
671 n = (SAB_BASE_BAUD * 10) / baud;
672 m = 0;
673 while (n >= 640) {
674 n = n / 2;
675 m++;
676 }
677 n = (n+5) / 10;
678 /*
679 * We try very hard to avoid speeds with M == 0 since they may
680 * not work correctly for XTAL frequences above 10 MHz.
681 */
682 if ((m == 0) && ((n & 1) == 0)) {
683 n = n / 2;
684 m++;
685 }
686 *n_ret = n - 1;
687 *m_ret = m;
688 }
690 /* Internal routine, port->lock is held and local interrupts are disabled. */
691 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
692 unsigned int iflag, unsigned int baud,
693 unsigned int quot)
694 {
695 unsigned char dafo;
696 int bits, n, m;
698 /* Byte size and parity */
699 switch (cflag & CSIZE) {
700 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
701 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
702 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
703 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
704 /* Never happens, but GCC is too dumb to figure it out */
705 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
706 }
708 if (cflag & CSTOPB) {
709 dafo |= SAB82532_DAFO_STOP;
710 bits++;
711 }
713 if (cflag & PARENB) {
714 dafo |= SAB82532_DAFO_PARE;
715 bits++;
716 }
718 if (cflag & PARODD) {
719 dafo |= SAB82532_DAFO_PAR_ODD;
720 } else {
721 dafo |= SAB82532_DAFO_PAR_EVEN;
722 }
723 up->cached_dafo = dafo;
725 calc_ebrg(baud, &n, &m);
727 up->cached_ebrg = n | (m << 6);
729 up->tec_timeout = (10 * 1000000) / baud;
730 up->cec_timeout = up->tec_timeout >> 2;
732 /* CTS flow control flags */
733 /* We encode read_status_mask and ignore_status_mask like so:
734 *
735 * ---------------------
736 * | ... | ISR1 | ISR0 |
737 * ---------------------
738 * .. 15 8 7 0
739 */
741 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
742 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
743 SAB82532_ISR0_CDSC);
744 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
745 SAB82532_ISR1_ALLS |
746 SAB82532_ISR1_XPR) << 8;
747 if (iflag & INPCK)
748 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
749 SAB82532_ISR0_FERR);
750 if (iflag & (BRKINT | PARMRK))
751 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
753 /*
754 * Characteres to ignore
755 */
756 up->port.ignore_status_mask = 0;
757 if (iflag & IGNPAR)
758 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
759 SAB82532_ISR0_FERR);
760 if (iflag & IGNBRK) {
761 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
762 /*
763 * If we're ignoring parity and break indicators,
764 * ignore overruns too (for real raw support).
765 */
766 if (iflag & IGNPAR)
767 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
768 }
770 /*
771 * ignore all characters if CREAD is not set
772 */
773 if ((cflag & CREAD) == 0)
774 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
775 SAB82532_ISR0_TCD);
777 uart_update_timeout(&up->port, cflag,
778 (up->port.uartclk / (16 * quot)));
780 /* Now schedule a register update when the chip's
781 * transmitter is idle.
782 */
783 up->cached_mode |= SAB82532_MODE_RAC;
784 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
785 if (test_bit(SAB82532_XPR, &up->irqflags))
786 sunsab_tx_idle(up);
787 }
789 /* port->lock is not held. */
790 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
791 struct termios *old)
792 {
793 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
794 unsigned long flags;
795 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
796 unsigned int quot = uart_get_divisor(port, baud);
798 spin_lock_irqsave(&up->port.lock, flags);
799 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
800 spin_unlock_irqrestore(&up->port.lock, flags);
801 }
803 static const char *sunsab_type(struct uart_port *port)
804 {
805 struct uart_sunsab_port *up = (void *)port;
806 static char buf[36];
808 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
809 return buf;
810 }
812 static void sunsab_release_port(struct uart_port *port)
813 {
814 }
816 static int sunsab_request_port(struct uart_port *port)
817 {
818 return 0;
819 }
821 static void sunsab_config_port(struct uart_port *port, int flags)
822 {
823 }
825 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
826 {
827 return -EINVAL;
828 }
830 static struct uart_ops sunsab_pops = {
831 .tx_empty = sunsab_tx_empty,
832 .set_mctrl = sunsab_set_mctrl,
833 .get_mctrl = sunsab_get_mctrl,
834 .stop_tx = sunsab_stop_tx,
835 .start_tx = sunsab_start_tx,
836 .send_xchar = sunsab_send_xchar,
837 .stop_rx = sunsab_stop_rx,
838 .enable_ms = sunsab_enable_ms,
839 .break_ctl = sunsab_break_ctl,
840 .startup = sunsab_startup,
841 .shutdown = sunsab_shutdown,
842 .set_termios = sunsab_set_termios,
843 .type = sunsab_type,
844 .release_port = sunsab_release_port,
845 .request_port = sunsab_request_port,
846 .config_port = sunsab_config_port,
847 .verify_port = sunsab_verify_port,
848 };
850 static struct uart_driver sunsab_reg = {
851 .owner = THIS_MODULE,
852 .driver_name = "serial",
853 .dev_name = "ttyS",
854 .major = TTY_MAJOR,
855 };
857 static struct uart_sunsab_port *sunsab_ports;
858 static int num_channels;
860 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
862 static void sunsab_console_putchar(struct uart_port *port, int c)
863 {
864 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
865 unsigned long flags;
867 spin_lock_irqsave(&up->port.lock, flags);
869 sunsab_tec_wait(up);
870 writeb(c, &up->regs->w.tic);
872 spin_unlock_irqrestore(&up->port.lock, flags);
873 }
875 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
876 {
877 struct uart_sunsab_port *up = &sunsab_ports[con->index];
879 uart_console_write(&up->port, s, n, sunsab_console_putchar);
880 sunsab_tec_wait(up);
881 }
883 static int sunsab_console_setup(struct console *con, char *options)
884 {
885 struct uart_sunsab_port *up = &sunsab_ports[con->index];
886 unsigned long flags;
887 unsigned int baud, quot;
889 /*
890 * The console framework calls us for each and every port
891 * registered. Defer the console setup until the requested
892 * port has been properly discovered. A bit of a hack,
893 * though...
894 */
895 if (up->port.type != PORT_SUNSAB)
896 return -1;
898 printk("Console: ttyS%d (SAB82532)\n",
899 (sunsab_reg.minor - 64) + con->index);
901 sunserial_console_termios(con);
903 switch (con->cflag & CBAUD) {
904 case B150: baud = 150; break;
905 case B300: baud = 300; break;
906 case B600: baud = 600; break;
907 case B1200: baud = 1200; break;
908 case B2400: baud = 2400; break;
909 case B4800: baud = 4800; break;
910 default: case B9600: baud = 9600; break;
911 case B19200: baud = 19200; break;
912 case B38400: baud = 38400; break;
913 case B57600: baud = 57600; break;
914 case B115200: baud = 115200; break;
915 case B230400: baud = 230400; break;
916 case B460800: baud = 460800; break;
917 };
919 /*
920 * Temporary fix.
921 */
922 spin_lock_init(&up->port.lock);
924 /*
925 * Initialize the hardware
926 */
927 sunsab_startup(&up->port);
929 spin_lock_irqsave(&up->port.lock, flags);
931 /*
932 * Finally, enable interrupts
933 */
934 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
935 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
936 writeb(up->interrupt_mask0, &up->regs->w.imr0);
937 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
938 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
939 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
940 SAB82532_IMR1_XPR;
941 writeb(up->interrupt_mask1, &up->regs->w.imr1);
943 quot = uart_get_divisor(&up->port, baud);
944 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
945 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
947 spin_unlock_irqrestore(&up->port.lock, flags);
949 return 0;
950 }
952 static struct console sunsab_console = {
953 .name = "ttyS",
954 .write = sunsab_console_write,
955 .device = uart_console_device,
956 .setup = sunsab_console_setup,
957 .flags = CON_PRINTBUFFER,
958 .index = -1,
959 .data = &sunsab_reg,
960 };
962 static inline struct console *SUNSAB_CONSOLE(void)
963 {
964 int i;
966 if (con_is_present())
967 return NULL;
969 for (i = 0; i < num_channels; i++) {
970 int this_minor = sunsab_reg.minor + i;
972 if ((this_minor - 64) == (serial_console - 1))
973 break;
974 }
975 if (i == num_channels)
976 return NULL;
978 sunsab_console.index = i;
980 return &sunsab_console;
981 }
982 #else
983 #define SUNSAB_CONSOLE() (NULL)
984 #define sunsab_console_init() do { } while (0)
985 #endif
987 static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
988 struct of_device *op,
989 unsigned long offset,
990 int line)
991 {
992 up->port.line = line;
993 up->port.dev = &op->dev;
995 up->port.mapbase = op->resource[0].start + offset;
996 up->port.membase = of_ioremap(&op->resource[0], offset,
997 sizeof(union sab82532_async_regs),
998 "sab");
999 if (!up->port.membase)
1000 return -ENOMEM;
1001 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
1003 up->port.irq = op->irqs[0];
1005 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1006 up->port.iotype = UPIO_MEM;
1008 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1010 up->port.ops = &sunsab_pops;
1011 up->port.type = PORT_SUNSAB;
1012 up->port.uartclk = SAB_BASE_BAUD;
1014 up->type = readb(&up->regs->r.vstr) & 0x0f;
1015 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1016 writeb(0xff, &up->regs->w.pim);
1017 if ((up->port.line & 0x1) == 0) {
1018 up->pvr_dsr_bit = (1 << 0);
1019 up->pvr_dtr_bit = (1 << 1);
1020 } else {
1021 up->pvr_dsr_bit = (1 << 3);
1022 up->pvr_dtr_bit = (1 << 2);
1024 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1025 writeb(up->cached_pvr, &up->regs->w.pvr);
1026 up->cached_mode = readb(&up->regs->rw.mode);
1027 up->cached_mode |= SAB82532_MODE_FRTS;
1028 writeb(up->cached_mode, &up->regs->rw.mode);
1029 up->cached_mode |= SAB82532_MODE_RTS;
1030 writeb(up->cached_mode, &up->regs->rw.mode);
1032 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1033 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1035 if (!(up->port.line & 0x01)) {
1036 int err;
1038 err = request_irq(up->port.irq, sunsab_interrupt,
1039 IRQF_SHARED, "sab", up);
1040 if (err) {
1041 of_iounmap(up->port.membase,
1042 sizeof(union sab82532_async_regs));
1043 return err;
1047 return 0;
1050 static int __devinit sab_probe(struct of_device *op, const struct of_device_id *match)
1052 static int inst;
1053 struct uart_sunsab_port *up;
1054 int err;
1056 up = &sunsab_ports[inst * 2];
1058 err = sunsab_init_one(&up[0], op,
1059 0,
1060 (inst * 2) + 0);
1061 if (err)
1062 return err;
1064 err = sunsab_init_one(&up[1], op,
1065 sizeof(union sab82532_async_regs),
1066 (inst * 2) + 1);
1067 if (err) {
1068 of_iounmap(up[0].port.membase,
1069 sizeof(union sab82532_async_regs));
1070 free_irq(up[0].port.irq, &up[0]);
1071 return err;
1074 uart_add_one_port(&sunsab_reg, &up[0].port);
1075 uart_add_one_port(&sunsab_reg, &up[1].port);
1077 dev_set_drvdata(&op->dev, &up[0]);
1079 inst++;
1081 return 0;
1084 static void __devexit sab_remove_one(struct uart_sunsab_port *up)
1086 uart_remove_one_port(&sunsab_reg, &up->port);
1087 if (!(up->port.line & 1))
1088 free_irq(up->port.irq, up);
1089 of_iounmap(up->port.membase,
1090 sizeof(union sab82532_async_regs));
1093 static int __devexit sab_remove(struct of_device *op)
1095 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1097 sab_remove_one(&up[0]);
1098 sab_remove_one(&up[1]);
1100 dev_set_drvdata(&op->dev, NULL);
1102 return 0;
1105 static struct of_device_id sab_match[] = {
1107 .name = "se",
1108 },
1110 .name = "serial",
1111 .compatible = "sab82532",
1112 },
1113 {},
1114 };
1115 MODULE_DEVICE_TABLE(of, sab_match);
1117 static struct of_platform_driver sab_driver = {
1118 .name = "sab",
1119 .match_table = sab_match,
1120 .probe = sab_probe,
1121 .remove = __devexit_p(sab_remove),
1122 };
1124 static int __init sunsab_init(void)
1126 struct device_node *dp;
1127 int err;
1129 num_channels = 0;
1130 for_each_node_by_name(dp, "se")
1131 num_channels += 2;
1132 for_each_node_by_name(dp, "serial") {
1133 if (of_device_is_compatible(dp, "sab82532"))
1134 num_channels += 2;
1137 if (num_channels) {
1138 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1139 num_channels, GFP_KERNEL);
1140 if (!sunsab_ports)
1141 return -ENOMEM;
1143 sunsab_reg.minor = sunserial_current_minor;
1144 sunsab_reg.nr = num_channels;
1146 err = uart_register_driver(&sunsab_reg);
1147 if (err) {
1148 kfree(sunsab_ports);
1149 sunsab_ports = NULL;
1151 return err;
1154 sunsab_reg.tty_driver->name_base = sunsab_reg.minor - 64;
1155 sunsab_reg.cons = SUNSAB_CONSOLE();
1156 sunserial_current_minor += num_channels;
1159 return of_register_driver(&sab_driver, &of_bus_type);
1162 static void __exit sunsab_exit(void)
1164 of_unregister_driver(&sab_driver);
1165 if (num_channels) {
1166 sunserial_current_minor -= num_channels;
1167 uart_unregister_driver(&sunsab_reg);
1170 kfree(sunsab_ports);
1171 sunsab_ports = NULL;
1174 module_init(sunsab_init);
1175 module_exit(sunsab_exit);
1177 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1178 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1179 MODULE_LICENSE("GPL");