ia64/linux-2.6.18-xen.hg

view drivers/serial/sh-sci.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */
13 #include <linux/serial_core.h>
15 #if defined(__H8300H__) || defined(__H8300S__)
16 #include <asm/gpio.h>
17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
18 #include <asm/regs306x.h>
19 #endif
20 #if defined(CONFIG_H8S2678)
21 #include <asm/regs267x.h>
22 #endif
23 #endif
25 /* Offsets into the sci_port->irqs array */
26 #define SCIx_ERI_IRQ 0
27 #define SCIx_RXI_IRQ 1
28 #define SCIx_TXI_IRQ 2
30 /* ERI, RXI, TXI, BRI */
31 #define SCI_IRQS { 23, 24, 25, 0 }
32 #define SH3_SCIF_IRQS { 56, 57, 59, 58 }
33 #define SH3_IRDA_IRQS { 52, 53, 55, 54 }
34 #define SH4_SCIF_IRQS { 40, 41, 43, 42 }
35 #define STB1_SCIF1_IRQS {23, 24, 26, 25 }
36 #define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
37 #define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
38 #define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
39 #define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
40 #define SH73180_SCIF_IRQS {80, 81, 83, 82 }
41 #define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
42 #define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
43 #define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
44 #define H8S_SCI_IRQS0 {88, 89, 90, 0 }
45 #define H8S_SCI_IRQS1 {92, 93, 94, 0 }
46 #define H8S_SCI_IRQS2 {96, 97, 98, 0 }
47 #define SH5_SCIF_IRQS {39, 40, 42, 0 }
48 #define SH7770_SCIF0_IRQS {61, 61, 61, 61 }
49 #define SH7770_SCIF1_IRQS {62, 62, 62, 62 }
50 #define SH7770_SCIF2_IRQS {63, 63, 63, 63 }
51 #define SH7780_SCIF0_IRQS {40, 41, 43, 42 }
52 #define SH7780_SCIF1_IRQS {76, 77, 79, 78 }
54 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
55 # define SCSPTR 0xffffff7c /* 8 bit */
56 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
57 # define SCI_ONLY
58 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
59 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
60 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
61 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
62 # define SCI_AND_SCIF
63 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
64 # define SCIF0 0xA4400000
65 # define SCIF2 0xA4410000
66 # define SCSMR_Ir 0xA44A0000
67 # define IRDA_SCIF SCIF0
68 # define SCPCR 0xA4000116
69 # define SCPDR 0xA4000136
71 /* Set the clock source,
72 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
73 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
74 */
75 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
76 # define SCIF_ONLY
77 #elif defined(CONFIG_SH_RTS7751R2D)
78 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
79 # define SCIF_ORER 0x0001 /* overrun error bit */
80 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
81 # define SCIF_ONLY
82 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
83 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
84 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
85 # define SCIF_ORER 0x0001 /* overrun error bit */
86 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
87 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
88 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
89 # define SCI_AND_SCIF
90 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
91 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
92 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
93 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
94 # define SCIF_ORER 0x0001 /* overrun error bit */
95 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 # define SCIF_ONLY
97 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
98 # define SCPCR 0xA4050116 /* 16 bit SCIF */
99 # define SCPDR 0xA4050136 /* 16 bit SCIF */
100 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
101 # define SCIF_ONLY
102 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
103 # define SCPDR 0xA4050138 /* 16 bit SCIF */
104 # define SCSPTR2 SCPDR
105 # define SCIF_ORER 0x0001 /* overrun error bit */
106 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
107 # define SCIF_ONLY
108 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
109 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
110 # define SCIF_ORER 0x0001 /* overrun error bit */
111 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
112 # define SCIF_ONLY
113 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
114 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
115 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
116 # define SCIF_ORER 0x0001 /* overrun error bit */
117 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118 # define SCIF_ONLY
119 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
120 # include <asm/hardware.h>
121 # define SCIF_BASE_ADDR 0x01030000
122 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
123 # define SCIF_PTR2_OFFS 0x0000020
124 # define SCIF_LSR2_OFFS 0x0000024
125 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
126 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
128 TE=1,RE=1,REIE=1 */
129 # define SCIF_ONLY
130 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
131 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
132 # define SCI_ONLY
133 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
134 #elif defined(CONFIG_H8S2678)
135 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
136 # define SCI_ONLY
137 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
138 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
139 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
140 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
141 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
142 # define SCIF_ORER 0x0001 /* overrun error bit */
143 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
144 # define SCIF_ONLY
145 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
146 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
147 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
148 # define SCIF_OPER 0x0001 /* Overrun error bit */
149 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
150 # define SCIF_ONLY
151 #else
152 # error CPU subtype not defined
153 #endif
155 /* SCSCR */
156 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
157 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
158 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
159 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
160 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
161 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
162 #else
163 #define SCI_CTRL_FLAGS_REIE 0
164 #endif
165 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
166 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
167 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
168 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
170 /* SCxSR SCI */
171 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
172 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
173 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
174 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
175 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
176 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
177 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
178 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
180 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
182 /* SCxSR SCIF */
183 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
184 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
185 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
186 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
187 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
188 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
189 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
190 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
192 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
193 #define SCIF_ORER 0x0200
194 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
195 #define SCIF_RFDC_MASK 0x007f
196 #define SCIF_TXROOM_MAX 64
197 #else
198 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
199 #define SCIF_RFDC_MASK 0x001f
200 #define SCIF_TXROOM_MAX 16
201 #endif
203 #if defined(SCI_ONLY)
204 # define SCxSR_TEND(port) SCI_TEND
205 # define SCxSR_ERRORS(port) SCI_ERRORS
206 # define SCxSR_RDxF(port) SCI_RDRF
207 # define SCxSR_TDxE(port) SCI_TDRE
208 # define SCxSR_ORER(port) SCI_ORER
209 # define SCxSR_FER(port) SCI_FER
210 # define SCxSR_PER(port) SCI_PER
211 # define SCxSR_BRK(port) 0x00
212 # define SCxSR_RDxF_CLEAR(port) 0xbc
213 # define SCxSR_ERROR_CLEAR(port) 0xc4
214 # define SCxSR_TDxE_CLEAR(port) 0x78
215 # define SCxSR_BREAK_CLEAR(port) 0xc4
216 #elif defined(SCIF_ONLY)
217 # define SCxSR_TEND(port) SCIF_TEND
218 # define SCxSR_ERRORS(port) SCIF_ERRORS
219 # define SCxSR_RDxF(port) SCIF_RDF
220 # define SCxSR_TDxE(port) SCIF_TDFE
221 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
222 # define SCxSR_ORER(port) SCIF_ORER
223 #else
224 # define SCxSR_ORER(port) 0x0000
225 #endif
226 # define SCxSR_FER(port) SCIF_FER
227 # define SCxSR_PER(port) SCIF_PER
228 # define SCxSR_BRK(port) SCIF_BRK
229 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
230 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
231 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
232 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
233 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
234 #else
235 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
236 # define SCxSR_RDxF_CLEAR(port) 0x00fc
237 # define SCxSR_ERROR_CLEAR(port) 0x0073
238 # define SCxSR_TDxE_CLEAR(port) 0x00df
239 # define SCxSR_BREAK_CLEAR(port) 0x00e3
240 #endif
241 #else
242 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
243 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
244 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
245 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
246 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
247 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
248 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
249 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
250 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
251 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
252 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
253 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
254 #endif
256 /* SCFCR */
257 #define SCFCR_RFRST 0x0002
258 #define SCFCR_TFRST 0x0004
259 #define SCFCR_TCRST 0x4000
260 #define SCFCR_MCE 0x0008
262 #define SCI_MAJOR 204
263 #define SCI_MINOR_START 8
265 /* Generic serial flags */
266 #define SCI_RX_THROTTLE 0x0000001
268 #define SCI_MAGIC 0xbabeface
270 /*
271 * Events are used to schedule things to happen at timer-interrupt
272 * time, instead of at rs interrupt time.
273 */
274 #define SCI_EVENT_WRITE_WAKEUP 0
276 struct sci_port {
277 struct uart_port port;
278 int type;
279 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
280 void (*init_pins)(struct uart_port *port, unsigned int cflag);
281 int break_flag;
282 struct timer_list break_timer;
283 };
285 #define SCI_IN(size, offset) \
286 unsigned int addr = port->mapbase + (offset); \
287 if ((size) == 8) { \
288 return ctrl_inb(addr); \
289 } else { \
290 return ctrl_inw(addr); \
291 }
292 #define SCI_OUT(size, offset, value) \
293 unsigned int addr = port->mapbase + (offset); \
294 if ((size) == 8) { \
295 ctrl_outb(value, addr); \
296 } else { \
297 ctrl_outw(value, addr); \
298 }
300 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
301 static inline unsigned int sci_##name##_in(struct uart_port *port) \
302 { \
303 if (port->type == PORT_SCI) { \
304 SCI_IN(sci_size, sci_offset) \
305 } else { \
306 SCI_IN(scif_size, scif_offset); \
307 } \
308 } \
309 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
310 { \
311 if (port->type == PORT_SCI) { \
312 SCI_OUT(sci_size, sci_offset, value) \
313 } else { \
314 SCI_OUT(scif_size, scif_offset, value); \
315 } \
316 }
318 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
319 static inline unsigned int sci_##name##_in(struct uart_port *port) \
320 { \
321 SCI_IN(scif_size, scif_offset); \
322 } \
323 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
324 { \
325 SCI_OUT(scif_size, scif_offset, value); \
326 }
328 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
329 static inline unsigned int sci_##name##_in(struct uart_port* port) \
330 { \
331 SCI_IN(sci_size, sci_offset); \
332 } \
333 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
334 { \
335 SCI_OUT(sci_size, sci_offset, value); \
336 }
338 #ifdef CONFIG_CPU_SH3
339 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
340 #define SCIF_FNS(name, scif_offset, scif_size) \
341 CPU_SCIF_FNS(name, scif_offset, scif_size)
342 #else
343 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
344 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
345 h8_sci_offset, h8_sci_size) \
346 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
347 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
348 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
349 #endif
350 #elif defined(__H8300H__) || defined(__H8300S__)
351 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
352 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
353 h8_sci_offset, h8_sci_size) \
354 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
355 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
356 #else
357 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
358 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
359 h8_sci_offset, h8_sci_size) \
360 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
361 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
362 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
363 #endif
365 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
366 SCIF_FNS(SCSMR, 0x00, 16)
367 SCIF_FNS(SCBRR, 0x04, 8)
368 SCIF_FNS(SCSCR, 0x08, 16)
369 SCIF_FNS(SCTDSR, 0x0c, 8)
370 SCIF_FNS(SCFER, 0x10, 16)
371 SCIF_FNS(SCxSR, 0x14, 16)
372 SCIF_FNS(SCFCR, 0x18, 16)
373 SCIF_FNS(SCFDR, 0x1c, 16)
374 SCIF_FNS(SCxTDR, 0x20, 8)
375 SCIF_FNS(SCxRDR, 0x24, 8)
376 SCIF_FNS(SCLSR, 0x24, 16)
377 #else
378 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
379 /* name off sz off sz off sz off sz off sz*/
380 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
381 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
382 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
383 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
384 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
385 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
386 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
387 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
388 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
389 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
390 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
391 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
392 #else
393 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
394 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
395 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
396 #endif
397 #endif
398 #define sci_in(port, reg) sci_##reg##_in(port)
399 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
401 /* H8/300 series SCI pins assignment */
402 #if defined(__H8300H__) || defined(__H8300S__)
403 static const struct __attribute__((packed)) {
404 int port; /* GPIO port no */
405 unsigned short rx,tx; /* GPIO bit no */
406 } h8300_sci_pins[] = {
407 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
408 { /* SCI0 */
409 .port = H8300_GPIO_P9,
410 .rx = H8300_GPIO_B2,
411 .tx = H8300_GPIO_B0,
412 },
413 { /* SCI1 */
414 .port = H8300_GPIO_P9,
415 .rx = H8300_GPIO_B3,
416 .tx = H8300_GPIO_B1,
417 },
418 { /* SCI2 */
419 .port = H8300_GPIO_PB,
420 .rx = H8300_GPIO_B7,
421 .tx = H8300_GPIO_B6,
422 }
423 #elif defined(CONFIG_H8S2678)
424 { /* SCI0 */
425 .port = H8300_GPIO_P3,
426 .rx = H8300_GPIO_B2,
427 .tx = H8300_GPIO_B0,
428 },
429 { /* SCI1 */
430 .port = H8300_GPIO_P3,
431 .rx = H8300_GPIO_B3,
432 .tx = H8300_GPIO_B1,
433 },
434 { /* SCI2 */
435 .port = H8300_GPIO_P5,
436 .rx = H8300_GPIO_B1,
437 .tx = H8300_GPIO_B0,
438 }
439 #endif
440 };
441 #endif
443 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
444 static inline int sci_rxd_in(struct uart_port *port)
445 {
446 if (port->mapbase == 0xfffffe80)
447 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
448 return 1;
449 }
450 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
451 static inline int sci_rxd_in(struct uart_port *port)
452 {
453 if (port->mapbase == 0xfffffe80)
454 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
455 if (port->mapbase == 0xa4000150)
456 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
457 if (port->mapbase == 0xa4000140)
458 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
459 return 1;
460 }
461 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
462 static inline int sci_rxd_in(struct uart_port *port)
463 {
464 if (port->mapbase == SCIF0)
465 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
466 if (port->mapbase == SCIF2)
467 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
468 return 1;
469 }
470 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
471 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
472 defined(CONFIG_CPU_SUBTYPE_SH4_202)
473 static inline int sci_rxd_in(struct uart_port *port)
474 {
475 #ifndef SCIF_ONLY
476 if (port->mapbase == 0xffe00000)
477 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
478 #endif
479 #ifndef SCI_ONLY
480 if (port->mapbase == 0xffe80000)
481 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
482 #endif
483 return 1;
484 }
485 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
486 static inline int sci_rxd_in(struct uart_port *port)
487 {
488 if (port->mapbase == 0xfe600000)
489 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
490 if (port->mapbase == 0xfe610000)
491 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
492 if (port->mapbase == 0xfe620000)
493 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
494 }
495 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
496 static inline int sci_rxd_in(struct uart_port *port)
497 {
498 if (port->mapbase == 0xa4430000)
499 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
500 return 1;
501 }
502 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
503 static inline int sci_rxd_in(struct uart_port *port)
504 {
505 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
506 }
507 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
508 static inline int sci_rxd_in(struct uart_port *port)
509 {
510 if (port->mapbase == 0xffe00000)
511 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
512 else
513 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
515 }
516 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
517 static inline int sci_rxd_in(struct uart_port *port)
518 {
519 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
520 }
521 #elif defined(__H8300H__) || defined(__H8300S__)
522 static inline int sci_rxd_in(struct uart_port *port)
523 {
524 int ch = (port->mapbase - SMR0) >> 3;
525 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
526 }
527 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
528 static inline int sci_rxd_in(struct uart_port *port)
529 {
530 if (port->mapbase == 0xff923000)
531 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
532 if (port->mapbase == 0xff924000)
533 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
534 if (port->mapbase == 0xff925000)
535 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
536 }
537 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
538 static inline int sci_rxd_in(struct uart_port *port)
539 {
540 if (port->mapbase == 0xffe00000)
541 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
542 if (port->mapbase == 0xffe10000)
543 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
544 }
545 #endif
547 /*
548 * Values for the BitRate Register (SCBRR)
549 *
550 * The values are actually divisors for a frequency which can
551 * be internal to the SH3 (14.7456MHz) or derived from an external
552 * clock source. This driver assumes the internal clock is used;
553 * to support using an external clock source, config options or
554 * possibly command-line options would need to be added.
555 *
556 * Also, to support speeds below 2400 (why?) the lower 2 bits of
557 * the SCSMR register would also need to be set to non-zero values.
558 *
559 * -- Greg Banks 27Feb2000
560 *
561 * Answer: The SCBRR register is only eight bits, and the value in
562 * it gets larger with lower baud rates. At around 2400 (depending on
563 * the peripherial module clock) you run out of bits. However the
564 * lower two bits of SCSMR allow the module clock to be divided down,
565 * scaling the value which is needed in SCBRR.
566 *
567 * -- Stuart Menefy - 23 May 2000
568 *
569 * I meant, why would anyone bother with bitrates below 2400.
570 *
571 * -- Greg Banks - 7Jul2000
572 *
573 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
574 * tape reader as a console!
575 *
576 * -- Mitch Davis - 15 Jul 2000
577 */
579 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
580 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
581 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
582 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
583 #elif defined(__H8300H__) || defined(__H8300S__)
584 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
585 #elif defined(CONFIG_SUPERH64)
586 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
587 #else /* Generic SH */
588 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
589 #endif