ia64/linux-2.6.18-xen.hg

view drivers/serial/sa1100.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * linux/drivers/char/sa1100.c
3 *
4 * Driver for SA11x0 serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $
25 *
26 */
28 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29 #define SUPPORT_SYSRQ
30 #endif
32 #include <linux/module.h>
33 #include <linux/ioport.h>
34 #include <linux/init.h>
35 #include <linux/console.h>
36 #include <linux/sysrq.h>
37 #include <linux/platform_device.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/hardware.h>
46 #include <asm/mach/serial_sa1100.h>
48 /* We've been assigned a range on the "Low-density serial ports" major */
49 #define SERIAL_SA1100_MAJOR 204
50 #define MINOR_START 5
52 #define NR_PORTS 3
54 #define SA1100_ISR_PASS_LIMIT 256
56 /*
57 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
58 */
59 #define SM_TO_UTSR0(x) ((x) & 0xff)
60 #define SM_TO_UTSR1(x) ((x) >> 8)
61 #define UTSR0_TO_SM(x) ((x))
62 #define UTSR1_TO_SM(x) ((x) << 8)
64 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
65 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
66 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
67 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
68 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
69 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
70 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
72 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
73 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
74 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
75 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
76 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
77 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
78 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
80 /*
81 * This is the size of our serial port register set.
82 */
83 #define UART_PORT_SIZE 0x24
85 /*
86 * This determines how often we check the modem status signals
87 * for any change. They generally aren't connected to an IRQ
88 * so we have to poll them. We also check immediately before
89 * filling the TX fifo incase CTS has been dropped.
90 */
91 #define MCTRL_TIMEOUT (250*HZ/1000)
93 struct sa1100_port {
94 struct uart_port port;
95 struct timer_list timer;
96 unsigned int old_status;
97 };
99 /*
100 * Handle any change of modem status signal since we were last called.
101 */
102 static void sa1100_mctrl_check(struct sa1100_port *sport)
103 {
104 unsigned int status, changed;
106 status = sport->port.ops->get_mctrl(&sport->port);
107 changed = status ^ sport->old_status;
109 if (changed == 0)
110 return;
112 sport->old_status = status;
114 if (changed & TIOCM_RI)
115 sport->port.icount.rng++;
116 if (changed & TIOCM_DSR)
117 sport->port.icount.dsr++;
118 if (changed & TIOCM_CAR)
119 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
120 if (changed & TIOCM_CTS)
121 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
123 wake_up_interruptible(&sport->port.info->delta_msr_wait);
124 }
126 /*
127 * This is our per-port timeout handler, for checking the
128 * modem status signals.
129 */
130 static void sa1100_timeout(unsigned long data)
131 {
132 struct sa1100_port *sport = (struct sa1100_port *)data;
133 unsigned long flags;
135 if (sport->port.info) {
136 spin_lock_irqsave(&sport->port.lock, flags);
137 sa1100_mctrl_check(sport);
138 spin_unlock_irqrestore(&sport->port.lock, flags);
140 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
141 }
142 }
144 /*
145 * interrupts disabled on entry
146 */
147 static void sa1100_stop_tx(struct uart_port *port)
148 {
149 struct sa1100_port *sport = (struct sa1100_port *)port;
150 u32 utcr3;
152 utcr3 = UART_GET_UTCR3(sport);
153 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
154 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
155 }
157 /*
158 * port locked and interrupts disabled
159 */
160 static void sa1100_start_tx(struct uart_port *port)
161 {
162 struct sa1100_port *sport = (struct sa1100_port *)port;
163 u32 utcr3;
165 utcr3 = UART_GET_UTCR3(sport);
166 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
167 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
168 }
170 /*
171 * Interrupts enabled
172 */
173 static void sa1100_stop_rx(struct uart_port *port)
174 {
175 struct sa1100_port *sport = (struct sa1100_port *)port;
176 u32 utcr3;
178 utcr3 = UART_GET_UTCR3(sport);
179 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
180 }
182 /*
183 * Set the modem control timer to fire immediately.
184 */
185 static void sa1100_enable_ms(struct uart_port *port)
186 {
187 struct sa1100_port *sport = (struct sa1100_port *)port;
189 mod_timer(&sport->timer, jiffies);
190 }
192 static void
193 sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs)
194 {
195 struct tty_struct *tty = sport->port.info->tty;
196 unsigned int status, ch, flg;
198 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
199 UTSR0_TO_SM(UART_GET_UTSR0(sport));
200 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
201 ch = UART_GET_CHAR(sport);
203 sport->port.icount.rx++;
205 flg = TTY_NORMAL;
207 /*
208 * note that the error handling code is
209 * out of the main execution path
210 */
211 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
212 if (status & UTSR1_TO_SM(UTSR1_PRE))
213 sport->port.icount.parity++;
214 else if (status & UTSR1_TO_SM(UTSR1_FRE))
215 sport->port.icount.frame++;
216 if (status & UTSR1_TO_SM(UTSR1_ROR))
217 sport->port.icount.overrun++;
219 status &= sport->port.read_status_mask;
221 if (status & UTSR1_TO_SM(UTSR1_PRE))
222 flg = TTY_PARITY;
223 else if (status & UTSR1_TO_SM(UTSR1_FRE))
224 flg = TTY_FRAME;
226 #ifdef SUPPORT_SYSRQ
227 sport->port.sysrq = 0;
228 #endif
229 }
231 if (uart_handle_sysrq_char(&sport->port, ch, regs))
232 goto ignore_char;
234 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
236 ignore_char:
237 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
238 UTSR0_TO_SM(UART_GET_UTSR0(sport));
239 }
240 tty_flip_buffer_push(tty);
241 }
243 static void sa1100_tx_chars(struct sa1100_port *sport)
244 {
245 struct circ_buf *xmit = &sport->port.info->xmit;
247 if (sport->port.x_char) {
248 UART_PUT_CHAR(sport, sport->port.x_char);
249 sport->port.icount.tx++;
250 sport->port.x_char = 0;
251 return;
252 }
254 /*
255 * Check the modem control lines before
256 * transmitting anything.
257 */
258 sa1100_mctrl_check(sport);
260 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
261 sa1100_stop_tx(&sport->port);
262 return;
263 }
265 /*
266 * Tried using FIFO (not checking TNF) for fifo fill:
267 * still had the '4 bytes repeated' problem.
268 */
269 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
270 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
271 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
272 sport->port.icount.tx++;
273 if (uart_circ_empty(xmit))
274 break;
275 }
277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
278 uart_write_wakeup(&sport->port);
280 if (uart_circ_empty(xmit))
281 sa1100_stop_tx(&sport->port);
282 }
284 static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
285 {
286 struct sa1100_port *sport = dev_id;
287 unsigned int status, pass_counter = 0;
289 spin_lock(&sport->port.lock);
290 status = UART_GET_UTSR0(sport);
291 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
292 do {
293 if (status & (UTSR0_RFS | UTSR0_RID)) {
294 /* Clear the receiver idle bit, if set */
295 if (status & UTSR0_RID)
296 UART_PUT_UTSR0(sport, UTSR0_RID);
297 sa1100_rx_chars(sport, regs);
298 }
300 /* Clear the relevant break bits */
301 if (status & (UTSR0_RBB | UTSR0_REB))
302 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
304 if (status & UTSR0_RBB)
305 sport->port.icount.brk++;
307 if (status & UTSR0_REB)
308 uart_handle_break(&sport->port);
310 if (status & UTSR0_TFS)
311 sa1100_tx_chars(sport);
312 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
313 break;
314 status = UART_GET_UTSR0(sport);
315 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
316 ~UTSR0_TFS;
317 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
318 spin_unlock(&sport->port.lock);
320 return IRQ_HANDLED;
321 }
323 /*
324 * Return TIOCSER_TEMT when transmitter is not busy.
325 */
326 static unsigned int sa1100_tx_empty(struct uart_port *port)
327 {
328 struct sa1100_port *sport = (struct sa1100_port *)port;
330 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
331 }
333 static unsigned int sa1100_get_mctrl(struct uart_port *port)
334 {
335 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
336 }
338 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
339 {
340 }
342 /*
343 * Interrupts always disabled.
344 */
345 static void sa1100_break_ctl(struct uart_port *port, int break_state)
346 {
347 struct sa1100_port *sport = (struct sa1100_port *)port;
348 unsigned long flags;
349 unsigned int utcr3;
351 spin_lock_irqsave(&sport->port.lock, flags);
352 utcr3 = UART_GET_UTCR3(sport);
353 if (break_state == -1)
354 utcr3 |= UTCR3_BRK;
355 else
356 utcr3 &= ~UTCR3_BRK;
357 UART_PUT_UTCR3(sport, utcr3);
358 spin_unlock_irqrestore(&sport->port.lock, flags);
359 }
361 static int sa1100_startup(struct uart_port *port)
362 {
363 struct sa1100_port *sport = (struct sa1100_port *)port;
364 int retval;
366 /*
367 * Allocate the IRQ
368 */
369 retval = request_irq(sport->port.irq, sa1100_int, 0,
370 "sa11x0-uart", sport);
371 if (retval)
372 return retval;
374 /*
375 * Finally, clear and enable interrupts
376 */
377 UART_PUT_UTSR0(sport, -1);
378 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
380 /*
381 * Enable modem status interrupts
382 */
383 spin_lock_irq(&sport->port.lock);
384 sa1100_enable_ms(&sport->port);
385 spin_unlock_irq(&sport->port.lock);
387 return 0;
388 }
390 static void sa1100_shutdown(struct uart_port *port)
391 {
392 struct sa1100_port *sport = (struct sa1100_port *)port;
394 /*
395 * Stop our timer.
396 */
397 del_timer_sync(&sport->timer);
399 /*
400 * Free the interrupt
401 */
402 free_irq(sport->port.irq, sport);
404 /*
405 * Disable all interrupts, port and break condition.
406 */
407 UART_PUT_UTCR3(sport, 0);
408 }
410 static void
411 sa1100_set_termios(struct uart_port *port, struct termios *termios,
412 struct termios *old)
413 {
414 struct sa1100_port *sport = (struct sa1100_port *)port;
415 unsigned long flags;
416 unsigned int utcr0, old_utcr3, baud, quot;
417 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
419 /*
420 * We only support CS7 and CS8.
421 */
422 while ((termios->c_cflag & CSIZE) != CS7 &&
423 (termios->c_cflag & CSIZE) != CS8) {
424 termios->c_cflag &= ~CSIZE;
425 termios->c_cflag |= old_csize;
426 old_csize = CS8;
427 }
429 if ((termios->c_cflag & CSIZE) == CS8)
430 utcr0 = UTCR0_DSS;
431 else
432 utcr0 = 0;
434 if (termios->c_cflag & CSTOPB)
435 utcr0 |= UTCR0_SBS;
436 if (termios->c_cflag & PARENB) {
437 utcr0 |= UTCR0_PE;
438 if (!(termios->c_cflag & PARODD))
439 utcr0 |= UTCR0_OES;
440 }
442 /*
443 * Ask the core to calculate the divisor for us.
444 */
445 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
446 quot = uart_get_divisor(port, baud);
448 spin_lock_irqsave(&sport->port.lock, flags);
450 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
451 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
452 if (termios->c_iflag & INPCK)
453 sport->port.read_status_mask |=
454 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
455 if (termios->c_iflag & (BRKINT | PARMRK))
456 sport->port.read_status_mask |=
457 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
459 /*
460 * Characters to ignore
461 */
462 sport->port.ignore_status_mask = 0;
463 if (termios->c_iflag & IGNPAR)
464 sport->port.ignore_status_mask |=
465 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
466 if (termios->c_iflag & IGNBRK) {
467 sport->port.ignore_status_mask |=
468 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
469 /*
470 * If we're ignoring parity and break indicators,
471 * ignore overruns too (for real raw support).
472 */
473 if (termios->c_iflag & IGNPAR)
474 sport->port.ignore_status_mask |=
475 UTSR1_TO_SM(UTSR1_ROR);
476 }
478 del_timer_sync(&sport->timer);
480 /*
481 * Update the per-port timeout.
482 */
483 uart_update_timeout(port, termios->c_cflag, baud);
485 /*
486 * disable interrupts and drain transmitter
487 */
488 old_utcr3 = UART_GET_UTCR3(sport);
489 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
491 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
492 barrier();
494 /* then, disable everything */
495 UART_PUT_UTCR3(sport, 0);
497 /* set the parity, stop bits and data size */
498 UART_PUT_UTCR0(sport, utcr0);
500 /* set the baud rate */
501 quot -= 1;
502 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
503 UART_PUT_UTCR2(sport, (quot & 0xff));
505 UART_PUT_UTSR0(sport, -1);
507 UART_PUT_UTCR3(sport, old_utcr3);
509 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
510 sa1100_enable_ms(&sport->port);
512 spin_unlock_irqrestore(&sport->port.lock, flags);
513 }
515 static const char *sa1100_type(struct uart_port *port)
516 {
517 struct sa1100_port *sport = (struct sa1100_port *)port;
519 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
520 }
522 /*
523 * Release the memory region(s) being used by 'port'.
524 */
525 static void sa1100_release_port(struct uart_port *port)
526 {
527 struct sa1100_port *sport = (struct sa1100_port *)port;
529 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
530 }
532 /*
533 * Request the memory region(s) being used by 'port'.
534 */
535 static int sa1100_request_port(struct uart_port *port)
536 {
537 struct sa1100_port *sport = (struct sa1100_port *)port;
539 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
540 "sa11x0-uart") != NULL ? 0 : -EBUSY;
541 }
543 /*
544 * Configure/autoconfigure the port.
545 */
546 static void sa1100_config_port(struct uart_port *port, int flags)
547 {
548 struct sa1100_port *sport = (struct sa1100_port *)port;
550 if (flags & UART_CONFIG_TYPE &&
551 sa1100_request_port(&sport->port) == 0)
552 sport->port.type = PORT_SA1100;
553 }
555 /*
556 * Verify the new serial_struct (for TIOCSSERIAL).
557 * The only change we allow are to the flags and type, and
558 * even then only between PORT_SA1100 and PORT_UNKNOWN
559 */
560 static int
561 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
562 {
563 struct sa1100_port *sport = (struct sa1100_port *)port;
564 int ret = 0;
566 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
567 ret = -EINVAL;
568 if (sport->port.irq != ser->irq)
569 ret = -EINVAL;
570 if (ser->io_type != SERIAL_IO_MEM)
571 ret = -EINVAL;
572 if (sport->port.uartclk / 16 != ser->baud_base)
573 ret = -EINVAL;
574 if ((void *)sport->port.mapbase != ser->iomem_base)
575 ret = -EINVAL;
576 if (sport->port.iobase != ser->port)
577 ret = -EINVAL;
578 if (ser->hub6 != 0)
579 ret = -EINVAL;
580 return ret;
581 }
583 static struct uart_ops sa1100_pops = {
584 .tx_empty = sa1100_tx_empty,
585 .set_mctrl = sa1100_set_mctrl,
586 .get_mctrl = sa1100_get_mctrl,
587 .stop_tx = sa1100_stop_tx,
588 .start_tx = sa1100_start_tx,
589 .stop_rx = sa1100_stop_rx,
590 .enable_ms = sa1100_enable_ms,
591 .break_ctl = sa1100_break_ctl,
592 .startup = sa1100_startup,
593 .shutdown = sa1100_shutdown,
594 .set_termios = sa1100_set_termios,
595 .type = sa1100_type,
596 .release_port = sa1100_release_port,
597 .request_port = sa1100_request_port,
598 .config_port = sa1100_config_port,
599 .verify_port = sa1100_verify_port,
600 };
602 static struct sa1100_port sa1100_ports[NR_PORTS];
604 /*
605 * Setup the SA1100 serial ports. Note that we don't include the IrDA
606 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
607 *
608 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
609 * Which serial port this ends up being depends on the machine you're
610 * running this kernel on. I'm not convinced that this is a good idea,
611 * but that's the way it traditionally works.
612 *
613 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
614 * used here.
615 */
616 static void __init sa1100_init_ports(void)
617 {
618 static int first = 1;
619 int i;
621 if (!first)
622 return;
623 first = 0;
625 for (i = 0; i < NR_PORTS; i++) {
626 sa1100_ports[i].port.uartclk = 3686400;
627 sa1100_ports[i].port.ops = &sa1100_pops;
628 sa1100_ports[i].port.fifosize = 8;
629 sa1100_ports[i].port.line = i;
630 sa1100_ports[i].port.iotype = UPIO_MEM;
631 init_timer(&sa1100_ports[i].timer);
632 sa1100_ports[i].timer.function = sa1100_timeout;
633 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
634 }
636 /*
637 * make transmit lines outputs, so that when the port
638 * is closed, the output is in the MARK state.
639 */
640 PPDR |= PPC_TXD1 | PPC_TXD3;
641 PPSR |= PPC_TXD1 | PPC_TXD3;
642 }
644 void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns)
645 {
646 if (fns->get_mctrl)
647 sa1100_pops.get_mctrl = fns->get_mctrl;
648 if (fns->set_mctrl)
649 sa1100_pops.set_mctrl = fns->set_mctrl;
651 sa1100_pops.pm = fns->pm;
652 sa1100_pops.set_wake = fns->set_wake;
653 }
655 void __init sa1100_register_uart(int idx, int port)
656 {
657 if (idx >= NR_PORTS) {
658 printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
659 return;
660 }
662 switch (port) {
663 case 1:
664 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
665 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
666 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
667 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
668 break;
670 case 2:
671 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
672 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
673 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
674 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
675 break;
677 case 3:
678 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
679 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
680 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
681 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
682 break;
684 default:
685 printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port);
686 }
687 }
690 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
691 static void sa1100_console_putchar(struct uart_port *port, int ch)
692 {
693 struct sa1100_port *sport = (struct sa1100_port *)port;
695 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
696 barrier();
697 UART_PUT_CHAR(sport, ch);
698 }
700 /*
701 * Interrupts are disabled on entering
702 */
703 static void
704 sa1100_console_write(struct console *co, const char *s, unsigned int count)
705 {
706 struct sa1100_port *sport = &sa1100_ports[co->index];
707 unsigned int old_utcr3, status;
709 /*
710 * First, save UTCR3 and then disable interrupts
711 */
712 old_utcr3 = UART_GET_UTCR3(sport);
713 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
714 UTCR3_TXE);
716 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
718 /*
719 * Finally, wait for transmitter to become empty
720 * and restore UTCR3
721 */
722 do {
723 status = UART_GET_UTSR1(sport);
724 } while (status & UTSR1_TBY);
725 UART_PUT_UTCR3(sport, old_utcr3);
726 }
728 /*
729 * If the port was already initialised (eg, by a boot loader),
730 * try to determine the current setup.
731 */
732 static void __init
733 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
734 int *parity, int *bits)
735 {
736 unsigned int utcr3;
738 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
739 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
740 /* ok, the port was enabled */
741 unsigned int utcr0, quot;
743 utcr0 = UART_GET_UTCR0(sport);
745 *parity = 'n';
746 if (utcr0 & UTCR0_PE) {
747 if (utcr0 & UTCR0_OES)
748 *parity = 'e';
749 else
750 *parity = 'o';
751 }
753 if (utcr0 & UTCR0_DSS)
754 *bits = 8;
755 else
756 *bits = 7;
758 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
759 quot &= 0xfff;
760 *baud = sport->port.uartclk / (16 * (quot + 1));
761 }
762 }
764 static int __init
765 sa1100_console_setup(struct console *co, char *options)
766 {
767 struct sa1100_port *sport;
768 int baud = 9600;
769 int bits = 8;
770 int parity = 'n';
771 int flow = 'n';
773 /*
774 * Check whether an invalid uart number has been specified, and
775 * if so, search for the first available port that does have
776 * console support.
777 */
778 if (co->index == -1 || co->index >= NR_PORTS)
779 co->index = 0;
780 sport = &sa1100_ports[co->index];
782 if (options)
783 uart_parse_options(options, &baud, &parity, &bits, &flow);
784 else
785 sa1100_console_get_options(sport, &baud, &parity, &bits);
787 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
788 }
790 static struct uart_driver sa1100_reg;
791 static struct console sa1100_console = {
792 .name = "ttySA",
793 .write = sa1100_console_write,
794 .device = uart_console_device,
795 .setup = sa1100_console_setup,
796 .flags = CON_PRINTBUFFER,
797 .index = -1,
798 .data = &sa1100_reg,
799 };
801 static int __init sa1100_rs_console_init(void)
802 {
803 sa1100_init_ports();
804 register_console(&sa1100_console);
805 return 0;
806 }
807 console_initcall(sa1100_rs_console_init);
809 #define SA1100_CONSOLE &sa1100_console
810 #else
811 #define SA1100_CONSOLE NULL
812 #endif
814 static struct uart_driver sa1100_reg = {
815 .owner = THIS_MODULE,
816 .driver_name = "ttySA",
817 .dev_name = "ttySA",
818 .major = SERIAL_SA1100_MAJOR,
819 .minor = MINOR_START,
820 .nr = NR_PORTS,
821 .cons = SA1100_CONSOLE,
822 };
824 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
825 {
826 struct sa1100_port *sport = platform_get_drvdata(dev);
828 if (sport)
829 uart_suspend_port(&sa1100_reg, &sport->port);
831 return 0;
832 }
834 static int sa1100_serial_resume(struct platform_device *dev)
835 {
836 struct sa1100_port *sport = platform_get_drvdata(dev);
838 if (sport)
839 uart_resume_port(&sa1100_reg, &sport->port);
841 return 0;
842 }
844 static int sa1100_serial_probe(struct platform_device *dev)
845 {
846 struct resource *res = dev->resource;
847 int i;
849 for (i = 0; i < dev->num_resources; i++, res++)
850 if (res->flags & IORESOURCE_MEM)
851 break;
853 if (i < dev->num_resources) {
854 for (i = 0; i < NR_PORTS; i++) {
855 if (sa1100_ports[i].port.mapbase != res->start)
856 continue;
858 sa1100_ports[i].port.dev = &dev->dev;
859 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
860 platform_set_drvdata(dev, &sa1100_ports[i]);
861 break;
862 }
863 }
865 return 0;
866 }
868 static int sa1100_serial_remove(struct platform_device *pdev)
869 {
870 struct sa1100_port *sport = platform_get_drvdata(pdev);
872 platform_set_drvdata(pdev, NULL);
874 if (sport)
875 uart_remove_one_port(&sa1100_reg, &sport->port);
877 return 0;
878 }
880 static struct platform_driver sa11x0_serial_driver = {
881 .probe = sa1100_serial_probe,
882 .remove = sa1100_serial_remove,
883 .suspend = sa1100_serial_suspend,
884 .resume = sa1100_serial_resume,
885 .driver = {
886 .name = "sa11x0-uart",
887 },
888 };
890 static int __init sa1100_serial_init(void)
891 {
892 int ret;
894 printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n");
896 sa1100_init_ports();
898 ret = uart_register_driver(&sa1100_reg);
899 if (ret == 0) {
900 ret = platform_driver_register(&sa11x0_serial_driver);
901 if (ret)
902 uart_unregister_driver(&sa1100_reg);
903 }
904 return ret;
905 }
907 static void __exit sa1100_serial_exit(void)
908 {
909 platform_driver_unregister(&sa11x0_serial_driver);
910 uart_unregister_driver(&sa1100_reg);
911 }
913 module_init(sa1100_serial_init);
914 module_exit(sa1100_serial_exit);
916 MODULE_AUTHOR("Deep Blue Solutions Ltd");
917 MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $");
918 MODULE_LICENSE("GPL");
919 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);