ia64/linux-2.6.18-xen.hg

view drivers/serial/pmac_zilog.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 #ifndef __PMAC_ZILOG_H__
2 #define __PMAC_ZILOG_H__
4 #define pmz_debug(fmt,arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg)
6 /*
7 * At most 2 ESCCs with 2 ports each
8 */
9 #define MAX_ZS_PORTS 4
11 /*
12 * We wrap our port structure around the generic uart_port.
13 */
14 #define NUM_ZSREGS 17
16 struct uart_pmac_port {
17 struct uart_port port;
18 struct uart_pmac_port *mate;
20 /* macio_dev for the escc holding this port (maybe be null on
21 * early inited port)
22 */
23 struct macio_dev *dev;
24 /* device node to this port, this points to one of 2 childs
25 * of "escc" node (ie. ch-a or ch-b)
26 */
27 struct device_node *node;
29 /* Port type as obtained from device tree (IRDA, modem, ...) */
30 int port_type;
31 u8 curregs[NUM_ZSREGS];
33 unsigned int flags;
34 #define PMACZILOG_FLAG_IS_CONS 0x00000001
35 #define PMACZILOG_FLAG_IS_KGDB 0x00000002
36 #define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
37 #define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
38 #define PMACZILOG_FLAG_REGS_HELD 0x00000010
39 #define PMACZILOG_FLAG_TX_STOPPED 0x00000020
40 #define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
41 #define PMACZILOG_FLAG_ENABLED 0x00000080
42 #define PMACZILOG_FLAG_IS_IRDA 0x00000100
43 #define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
44 #define PMACZILOG_FLAG_HAS_DMA 0x00000400
45 #define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
46 #define PMACZILOG_FLAG_IS_ASLEEP 0x00001000
47 #define PMACZILOG_FLAG_IS_OPEN 0x00002000
48 #define PMACZILOG_FLAG_IS_IRQ_ON 0x00004000
49 #define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
50 #define PMACZILOG_FLAG_BREAK 0x00010000
52 unsigned char parity_mask;
53 unsigned char prev_status;
55 volatile u8 __iomem *control_reg;
56 volatile u8 __iomem *data_reg;
58 unsigned int tx_dma_irq;
59 unsigned int rx_dma_irq;
60 volatile struct dbdma_regs __iomem *tx_dma_regs;
61 volatile struct dbdma_regs __iomem *rx_dma_regs;
63 struct termios termios_cache;
64 };
66 #define to_pmz(p) ((struct uart_pmac_port *)(p))
68 static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
69 {
70 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
71 return uap;
72 return uap->mate;
73 }
75 /*
76 * Register acessors. Note that we don't need to enforce a recovery
77 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
78 * though if we try to use this driver on older machines, we might have
79 * to add it back
80 */
81 static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
82 {
83 if (reg != 0)
84 writeb(reg, port->control_reg);
85 return readb(port->control_reg);
86 }
88 static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
89 {
90 if (reg != 0)
91 writeb(reg, port->control_reg);
92 writeb(value, port->control_reg);
93 }
95 static inline u8 read_zsdata(struct uart_pmac_port *port)
96 {
97 return readb(port->data_reg);
98 }
100 static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
101 {
102 writeb(data, port->data_reg);
103 }
105 static inline void zssync(struct uart_pmac_port *port)
106 {
107 (void)readb(port->control_reg);
108 }
110 /* Conversion routines to/from brg time constants from/to bits
111 * per second.
112 */
113 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
114 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
118 /* The Zilog register set */
120 #define FLAG 0x7e
122 /* Write Register 0 */
123 #define R0 0 /* Register selects */
124 #define R1 1
125 #define R2 2
126 #define R3 3
127 #define R4 4
128 #define R5 5
129 #define R6 6
130 #define R7 7
131 #define R8 8
132 #define R9 9
133 #define R10 10
134 #define R11 11
135 #define R12 12
136 #define R13 13
137 #define R14 14
138 #define R15 15
139 #define R7P 16
141 #define NULLCODE 0 /* Null Code */
142 #define POINT_HIGH 0x8 /* Select upper half of registers */
143 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
144 #define SEND_ABORT 0x18 /* HDLC Abort */
145 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
146 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
147 #define ERR_RES 0x30 /* Error Reset */
148 #define RES_H_IUS 0x38 /* Reset highest IUS */
150 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
151 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
152 #define RES_EOM_L 0xC0 /* Reset EOM latch */
154 /* Write Register 1 */
156 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
157 #define TxINT_ENAB 0x2 /* Tx Int Enable */
158 #define PAR_SPEC 0x4 /* Parity is special condition */
160 #define RxINT_DISAB 0 /* Rx Int Disable */
161 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
162 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
163 #define INT_ERR_Rx 0x18 /* Int on error only */
164 #define RxINT_MASK 0x18
166 #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
167 #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */
168 #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */
170 /* Write Register #2 (Interrupt Vector) */
172 /* Write Register 3 */
174 #define RxENABLE 0x1 /* Rx Enable */
175 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
176 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
177 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
178 #define ENT_HM 0x10 /* Enter Hunt Mode */
179 #define AUTO_ENAB 0x20 /* Auto Enables */
180 #define Rx5 0x0 /* Rx 5 Bits/Character */
181 #define Rx7 0x40 /* Rx 7 Bits/Character */
182 #define Rx6 0x80 /* Rx 6 Bits/Character */
183 #define Rx8 0xc0 /* Rx 8 Bits/Character */
184 #define RxN_MASK 0xc0
186 /* Write Register 4 */
188 #define PAR_ENAB 0x1 /* Parity Enable */
189 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
191 #define SYNC_ENAB 0 /* Sync Modes Enable */
192 #define SB1 0x4 /* 1 stop bit/char */
193 #define SB15 0x8 /* 1.5 stop bits/char */
194 #define SB2 0xc /* 2 stop bits/char */
195 #define SB_MASK 0xc
197 #define MONSYNC 0 /* 8 Bit Sync character */
198 #define BISYNC 0x10 /* 16 bit sync character */
199 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
200 #define EXTSYNC 0x30 /* External Sync Mode */
202 #define X1CLK 0x0 /* x1 clock mode */
203 #define X16CLK 0x40 /* x16 clock mode */
204 #define X32CLK 0x80 /* x32 clock mode */
205 #define X64CLK 0xC0 /* x64 clock mode */
206 #define XCLK_MASK 0xC0
208 /* Write Register 5 */
210 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
211 #define RTS 0x2 /* RTS */
212 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
213 #define TxENABLE 0x8 /* Tx Enable */
214 #define SND_BRK 0x10 /* Send Break */
215 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
216 #define Tx7 0x20 /* Tx 7 bits/character */
217 #define Tx6 0x40 /* Tx 6 bits/character */
218 #define Tx8 0x60 /* Tx 8 bits/character */
219 #define TxN_MASK 0x60
220 #define DTR 0x80 /* DTR */
222 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
224 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
226 /* Write Register 7' (Some enhanced feature control) */
227 #define ENEXREAD 0x40 /* Enable read of some write registers */
229 /* Write Register 8 (transmit buffer) */
231 /* Write Register 9 (Master interrupt control) */
232 #define VIS 1 /* Vector Includes Status */
233 #define NV 2 /* No Vector */
234 #define DLC 4 /* Disable Lower Chain */
235 #define MIE 8 /* Master Interrupt Enable */
236 #define STATHI 0x10 /* Status high */
237 #define NORESET 0 /* No reset on write to R9 */
238 #define CHRB 0x40 /* Reset channel B */
239 #define CHRA 0x80 /* Reset channel A */
240 #define FHWRES 0xc0 /* Force hardware reset */
242 /* Write Register 10 (misc control bits) */
243 #define BIT6 1 /* 6 bit/8bit sync */
244 #define LOOPMODE 2 /* SDLC Loop mode */
245 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
246 #define MARKIDLE 8 /* Mark/flag on idle */
247 #define GAOP 0x10 /* Go active on poll */
248 #define NRZ 0 /* NRZ mode */
249 #define NRZI 0x20 /* NRZI mode */
250 #define FM1 0x40 /* FM1 (transition = 1) */
251 #define FM0 0x60 /* FM0 (transition = 0) */
252 #define CRCPS 0x80 /* CRC Preset I/O */
254 /* Write Register 11 (Clock Mode control) */
255 #define TRxCXT 0 /* TRxC = Xtal output */
256 #define TRxCTC 1 /* TRxC = Transmit clock */
257 #define TRxCBR 2 /* TRxC = BR Generator Output */
258 #define TRxCDP 3 /* TRxC = DPLL output */
259 #define TRxCOI 4 /* TRxC O/I */
260 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
261 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
262 #define TCBR 0x10 /* Transmit clock = BR Generator output */
263 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
264 #define RCRTxCP 0 /* Receive clock = RTxC pin */
265 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
266 #define RCBR 0x40 /* Receive clock = BR Generator output */
267 #define RCDPLL 0x60 /* Receive clock = DPLL output */
268 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
270 /* Write Register 12 (lower byte of baud rate generator time constant) */
272 /* Write Register 13 (upper byte of baud rate generator time constant) */
274 /* Write Register 14 (Misc control bits) */
275 #define BRENAB 1 /* Baud rate generator enable */
276 #define BRSRC 2 /* Baud rate generator source */
277 #define DTRREQ 4 /* DTR/Request function */
278 #define AUTOECHO 8 /* Auto Echo */
279 #define LOOPBAK 0x10 /* Local loopback */
280 #define SEARCH 0x20 /* Enter search mode */
281 #define RMC 0x40 /* Reset missing clock */
282 #define DISDPLL 0x60 /* Disable DPLL */
283 #define SSBR 0x80 /* Set DPLL source = BR generator */
284 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
285 #define SFMM 0xc0 /* Set FM mode */
286 #define SNRZI 0xe0 /* Set NRZI mode */
288 /* Write Register 15 (external/status interrupt control) */
289 #define EN85C30 1 /* Enable some 85c30-enhanced registers */
290 #define ZCIE 2 /* Zero count IE */
291 #define ENSTFIFO 4 /* Enable status FIFO (SDLC) */
292 #define DCDIE 8 /* DCD IE */
293 #define SYNCIE 0x10 /* Sync/hunt IE */
294 #define CTSIE 0x20 /* CTS IE */
295 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
296 #define BRKIE 0x80 /* Break/Abort IE */
299 /* Read Register 0 */
300 #define Rx_CH_AV 0x1 /* Rx Character Available */
301 #define ZCOUNT 0x2 /* Zero count */
302 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
303 #define DCD 0x8 /* DCD */
304 #define SYNC_HUNT 0x10 /* Sync/hunt */
305 #define CTS 0x20 /* CTS */
306 #define TxEOM 0x40 /* Tx underrun */
307 #define BRK_ABRT 0x80 /* Break/Abort */
309 /* Read Register 1 */
310 #define ALL_SNT 0x1 /* All sent */
311 /* Residue Data for 8 Rx bits/char programmed */
312 #define RES3 0x8 /* 0/3 */
313 #define RES4 0x4 /* 0/4 */
314 #define RES5 0xc /* 0/5 */
315 #define RES6 0x2 /* 0/6 */
316 #define RES7 0xa /* 0/7 */
317 #define RES8 0x6 /* 0/8 */
318 #define RES18 0xe /* 1/8 */
319 #define RES28 0x0 /* 2/8 */
320 /* Special Rx Condition Interrupts */
321 #define PAR_ERR 0x10 /* Parity error */
322 #define Rx_OVR 0x20 /* Rx Overrun Error */
323 #define CRC_ERR 0x40 /* CRC/Framing Error */
324 #define END_FR 0x80 /* End of Frame (SDLC) */
326 /* Read Register 2 (channel b only) - Interrupt vector */
327 #define CHB_Tx_EMPTY 0x00
328 #define CHB_EXT_STAT 0x02
329 #define CHB_Rx_AVAIL 0x04
330 #define CHB_SPECIAL 0x06
331 #define CHA_Tx_EMPTY 0x08
332 #define CHA_EXT_STAT 0x0a
333 #define CHA_Rx_AVAIL 0x0c
334 #define CHA_SPECIAL 0x0e
335 #define STATUS_MASK 0x06
337 /* Read Register 3 (interrupt pending register) ch a only */
338 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
339 #define CHBTxIP 0x2 /* Channel B Tx IP */
340 #define CHBRxIP 0x4 /* Channel B Rx IP */
341 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
342 #define CHATxIP 0x10 /* Channel A Tx IP */
343 #define CHARxIP 0x20 /* Channel A Rx IP */
345 /* Read Register 8 (receive data register) */
347 /* Read Register 10 (misc status bits) */
348 #define ONLOOP 2 /* On loop */
349 #define LOOPSEND 0x10 /* Loop sending */
350 #define CLK2MIS 0x40 /* Two clocks missing */
351 #define CLK1MIS 0x80 /* One clock missing */
353 /* Read Register 12 (lower byte of baud rate generator constant) */
355 /* Read Register 13 (upper byte of baud rate generator constant) */
357 /* Read Register 15 (value of WR 15) */
359 /* Misc macros */
360 #define ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES))
361 #define ZS_CLEARFIFO(port) do { volatile unsigned char garbage; \
362 garbage = read_zsdata(port); \
363 garbage = read_zsdata(port); \
364 garbage = read_zsdata(port); \
365 } while(0)
367 #define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
368 #define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
369 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
370 #define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
371 #define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
372 #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
373 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
374 #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
375 #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
376 #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
377 #define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP)
378 #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
379 #define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON)
380 #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
382 #endif /* __PMAC_ZILOG_H__ */