ia64/linux-2.6.18-xen.hg

view drivers/serial/pmac_zilog.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
45 #include <linux/module.h>
46 #include <linux/tty.h>
48 #include <linux/tty_flip.h>
49 #include <linux/major.h>
50 #include <linux/string.h>
51 #include <linux/fcntl.h>
52 #include <linux/mm.h>
53 #include <linux/kernel.h>
54 #include <linux/delay.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
57 #include <linux/slab.h>
58 #include <linux/adb.h>
59 #include <linux/pmu.h>
60 #include <linux/bitops.h>
61 #include <linux/sysrq.h>
62 #include <linux/mutex.h>
63 #include <asm/sections.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66 #include <asm/prom.h>
67 #include <asm/machdep.h>
68 #include <asm/pmac_feature.h>
69 #include <asm/dbdma.h>
70 #include <asm/macio.h>
72 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
73 #define SUPPORT_SYSRQ
74 #endif
76 #include <linux/serial.h>
77 #include <linux/serial_core.h>
79 #include "pmac_zilog.h"
81 /* Not yet implemented */
82 #undef HAS_DBDMA
84 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
85 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
86 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
87 MODULE_LICENSE("GPL");
89 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
92 /*
93 * For the sake of early serial console, we can do a pre-probe
94 * (optional) of the ports at rather early boot time.
95 */
96 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
97 static int pmz_ports_count;
98 static DEFINE_MUTEX(pmz_irq_mutex);
100 static struct uart_driver pmz_uart_reg = {
101 .owner = THIS_MODULE,
102 .driver_name = "ttyS",
103 .dev_name = "ttyS",
104 .major = TTY_MAJOR,
105 };
108 /*
109 * Load all registers to reprogram the port
110 * This function must only be called when the TX is not busy. The UART
111 * port lock must be held and local interrupts disabled.
112 */
113 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
114 {
115 int i;
117 if (ZS_IS_ASLEEP(uap))
118 return;
120 /* Let pending transmits finish. */
121 for (i = 0; i < 1000; i++) {
122 unsigned char stat = read_zsreg(uap, R1);
123 if (stat & ALL_SNT)
124 break;
125 udelay(100);
126 }
128 ZS_CLEARERR(uap);
129 zssync(uap);
130 ZS_CLEARFIFO(uap);
131 zssync(uap);
132 ZS_CLEARERR(uap);
134 /* Disable all interrupts. */
135 write_zsreg(uap, R1,
136 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
138 /* Set parity, sync config, stop bits, and clock divisor. */
139 write_zsreg(uap, R4, regs[R4]);
141 /* Set misc. TX/RX control bits. */
142 write_zsreg(uap, R10, regs[R10]);
144 /* Set TX/RX controls sans the enable bits. */
145 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
148 /* now set R7 "prime" on ESCC */
149 write_zsreg(uap, R15, regs[R15] | EN85C30);
150 write_zsreg(uap, R7, regs[R7P]);
152 /* make sure we use R7 "non-prime" on ESCC */
153 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
155 /* Synchronous mode config. */
156 write_zsreg(uap, R6, regs[R6]);
157 write_zsreg(uap, R7, regs[R7]);
159 /* Disable baud generator. */
160 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
162 /* Clock mode control. */
163 write_zsreg(uap, R11, regs[R11]);
165 /* Lower and upper byte of baud rate generator divisor. */
166 write_zsreg(uap, R12, regs[R12]);
167 write_zsreg(uap, R13, regs[R13]);
169 /* Now rewrite R14, with BRENAB (if set). */
170 write_zsreg(uap, R14, regs[R14]);
172 /* Reset external status interrupts. */
173 write_zsreg(uap, R0, RES_EXT_INT);
174 write_zsreg(uap, R0, RES_EXT_INT);
176 /* Rewrite R3/R5, this time without enables masked. */
177 write_zsreg(uap, R3, regs[R3]);
178 write_zsreg(uap, R5, regs[R5]);
180 /* Rewrite R1, this time without IRQ enabled masked. */
181 write_zsreg(uap, R1, regs[R1]);
183 /* Enable interrupts */
184 write_zsreg(uap, R9, regs[R9]);
185 }
187 /*
188 * We do like sunzilog to avoid disrupting pending Tx
189 * Reprogram the Zilog channel HW registers with the copies found in the
190 * software state struct. If the transmitter is busy, we defer this update
191 * until the next TX complete interrupt. Else, we do it right now.
192 *
193 * The UART port lock must be held and local interrupts disabled.
194 */
195 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
196 {
197 if (!ZS_REGS_HELD(uap)) {
198 if (ZS_TX_ACTIVE(uap)) {
199 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
200 } else {
201 pmz_debug("pmz: maybe_update_regs: updating\n");
202 pmz_load_zsregs(uap, uap->curregs);
203 }
204 }
205 }
207 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
208 struct pt_regs *regs)
209 {
210 struct tty_struct *tty = NULL;
211 unsigned char ch, r1, drop, error, flag;
212 int loops = 0;
214 /* The interrupt can be enabled when the port isn't open, typically
215 * that happens when using one port is open and the other closed (stale
216 * interrupt) or when one port is used as a console.
217 */
218 if (!ZS_IS_OPEN(uap)) {
219 pmz_debug("pmz: draining input\n");
220 /* Port is closed, drain input data */
221 for (;;) {
222 if ((++loops) > 1000)
223 goto flood;
224 (void)read_zsreg(uap, R1);
225 write_zsreg(uap, R0, ERR_RES);
226 (void)read_zsdata(uap);
227 ch = read_zsreg(uap, R0);
228 if (!(ch & Rx_CH_AV))
229 break;
230 }
231 return NULL;
232 }
234 /* Sanity check, make sure the old bug is no longer happening */
235 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
236 WARN_ON(1);
237 (void)read_zsdata(uap);
238 return NULL;
239 }
240 tty = uap->port.info->tty;
242 while (1) {
243 error = 0;
244 drop = 0;
246 r1 = read_zsreg(uap, R1);
247 ch = read_zsdata(uap);
249 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
250 write_zsreg(uap, R0, ERR_RES);
251 zssync(uap);
252 }
254 ch &= uap->parity_mask;
255 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
256 uap->flags &= ~PMACZILOG_FLAG_BREAK;
257 }
259 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
260 #ifdef USE_CTRL_O_SYSRQ
261 /* Handle the SysRq ^O Hack */
262 if (ch == '\x0f') {
263 uap->port.sysrq = jiffies + HZ*5;
264 goto next_char;
265 }
266 #endif /* USE_CTRL_O_SYSRQ */
267 if (uap->port.sysrq) {
268 int swallow;
269 spin_unlock(&uap->port.lock);
270 swallow = uart_handle_sysrq_char(&uap->port, ch, regs);
271 spin_lock(&uap->port.lock);
272 if (swallow)
273 goto next_char;
274 }
275 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
277 /* A real serial line, record the character and status. */
278 if (drop)
279 goto next_char;
281 flag = TTY_NORMAL;
282 uap->port.icount.rx++;
284 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
285 error = 1;
286 if (r1 & BRK_ABRT) {
287 pmz_debug("pmz: got break !\n");
288 r1 &= ~(PAR_ERR | CRC_ERR);
289 uap->port.icount.brk++;
290 if (uart_handle_break(&uap->port))
291 goto next_char;
292 }
293 else if (r1 & PAR_ERR)
294 uap->port.icount.parity++;
295 else if (r1 & CRC_ERR)
296 uap->port.icount.frame++;
297 if (r1 & Rx_OVR)
298 uap->port.icount.overrun++;
299 r1 &= uap->port.read_status_mask;
300 if (r1 & BRK_ABRT)
301 flag = TTY_BREAK;
302 else if (r1 & PAR_ERR)
303 flag = TTY_PARITY;
304 else if (r1 & CRC_ERR)
305 flag = TTY_FRAME;
306 }
308 if (uap->port.ignore_status_mask == 0xff ||
309 (r1 & uap->port.ignore_status_mask) == 0) {
310 tty_insert_flip_char(tty, ch, flag);
311 }
312 if (r1 & Rx_OVR)
313 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
314 next_char:
315 /* We can get stuck in an infinite loop getting char 0 when the
316 * line is in a wrong HW state, we break that here.
317 * When that happens, I disable the receive side of the driver.
318 * Note that what I've been experiencing is a real irq loop where
319 * I'm getting flooded regardless of the actual port speed.
320 * Something stange is going on with the HW
321 */
322 if ((++loops) > 1000)
323 goto flood;
324 ch = read_zsreg(uap, R0);
325 if (!(ch & Rx_CH_AV))
326 break;
327 }
329 return tty;
330 flood:
331 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
332 write_zsreg(uap, R1, uap->curregs[R1]);
333 zssync(uap);
334 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
335 return tty;
336 }
338 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
339 {
340 unsigned char status;
342 status = read_zsreg(uap, R0);
343 write_zsreg(uap, R0, RES_EXT_INT);
344 zssync(uap);
346 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
347 if (status & SYNC_HUNT)
348 uap->port.icount.dsr++;
350 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
351 * But it does not tell us which bit has changed, we have to keep
352 * track of this ourselves.
353 * The CTS input is inverted for some reason. -- paulus
354 */
355 if ((status ^ uap->prev_status) & DCD)
356 uart_handle_dcd_change(&uap->port,
357 (status & DCD));
358 if ((status ^ uap->prev_status) & CTS)
359 uart_handle_cts_change(&uap->port,
360 !(status & CTS));
362 wake_up_interruptible(&uap->port.info->delta_msr_wait);
363 }
365 if (status & BRK_ABRT)
366 uap->flags |= PMACZILOG_FLAG_BREAK;
368 uap->prev_status = status;
369 }
371 static void pmz_transmit_chars(struct uart_pmac_port *uap)
372 {
373 struct circ_buf *xmit;
375 if (ZS_IS_ASLEEP(uap))
376 return;
377 if (ZS_IS_CONS(uap)) {
378 unsigned char status = read_zsreg(uap, R0);
380 /* TX still busy? Just wait for the next TX done interrupt.
381 *
382 * It can occur because of how we do serial console writes. It would
383 * be nice to transmit console writes just like we normally would for
384 * a TTY line. (ie. buffered and TX interrupt driven). That is not
385 * easy because console writes cannot sleep. One solution might be
386 * to poll on enough port->xmit space becomming free. -DaveM
387 */
388 if (!(status & Tx_BUF_EMP))
389 return;
390 }
392 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
394 if (ZS_REGS_HELD(uap)) {
395 pmz_load_zsregs(uap, uap->curregs);
396 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
397 }
399 if (ZS_TX_STOPPED(uap)) {
400 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
401 goto ack_tx_int;
402 }
404 if (uap->port.x_char) {
405 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
406 write_zsdata(uap, uap->port.x_char);
407 zssync(uap);
408 uap->port.icount.tx++;
409 uap->port.x_char = 0;
410 return;
411 }
413 if (uap->port.info == NULL)
414 goto ack_tx_int;
415 xmit = &uap->port.info->xmit;
416 if (uart_circ_empty(xmit)) {
417 uart_write_wakeup(&uap->port);
418 goto ack_tx_int;
419 }
420 if (uart_tx_stopped(&uap->port))
421 goto ack_tx_int;
423 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
424 write_zsdata(uap, xmit->buf[xmit->tail]);
425 zssync(uap);
427 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
428 uap->port.icount.tx++;
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&uap->port);
433 return;
435 ack_tx_int:
436 write_zsreg(uap, R0, RES_Tx_P);
437 zssync(uap);
438 }
440 /* Hrm... we register that twice, fixme later.... */
441 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
442 {
443 struct uart_pmac_port *uap = dev_id;
444 struct uart_pmac_port *uap_a;
445 struct uart_pmac_port *uap_b;
446 int rc = IRQ_NONE;
447 struct tty_struct *tty;
448 u8 r3;
450 uap_a = pmz_get_port_A(uap);
451 uap_b = uap_a->mate;
453 spin_lock(&uap_a->port.lock);
454 r3 = read_zsreg(uap_a, R3);
456 #ifdef DEBUG_HARD
457 pmz_debug("irq, r3: %x\n", r3);
458 #endif
459 /* Channel A */
460 tty = NULL;
461 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
462 write_zsreg(uap_a, R0, RES_H_IUS);
463 zssync(uap_a);
464 if (r3 & CHAEXT)
465 pmz_status_handle(uap_a, regs);
466 if (r3 & CHARxIP)
467 tty = pmz_receive_chars(uap_a, regs);
468 if (r3 & CHATxIP)
469 pmz_transmit_chars(uap_a);
470 rc = IRQ_HANDLED;
471 }
472 spin_unlock(&uap_a->port.lock);
473 if (tty != NULL)
474 tty_flip_buffer_push(tty);
476 if (uap_b->node == NULL)
477 goto out;
479 spin_lock(&uap_b->port.lock);
480 tty = NULL;
481 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
482 write_zsreg(uap_b, R0, RES_H_IUS);
483 zssync(uap_b);
484 if (r3 & CHBEXT)
485 pmz_status_handle(uap_b, regs);
486 if (r3 & CHBRxIP)
487 tty = pmz_receive_chars(uap_b, regs);
488 if (r3 & CHBTxIP)
489 pmz_transmit_chars(uap_b);
490 rc = IRQ_HANDLED;
491 }
492 spin_unlock(&uap_b->port.lock);
493 if (tty != NULL)
494 tty_flip_buffer_push(tty);
496 out:
497 #ifdef DEBUG_HARD
498 pmz_debug("irq done.\n");
499 #endif
500 return rc;
501 }
503 /*
504 * Peek the status register, lock not held by caller
505 */
506 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
507 {
508 unsigned long flags;
509 u8 status;
511 spin_lock_irqsave(&uap->port.lock, flags);
512 status = read_zsreg(uap, R0);
513 spin_unlock_irqrestore(&uap->port.lock, flags);
515 return status;
516 }
518 /*
519 * Check if transmitter is empty
520 * The port lock is not held.
521 */
522 static unsigned int pmz_tx_empty(struct uart_port *port)
523 {
524 struct uart_pmac_port *uap = to_pmz(port);
525 unsigned char status;
527 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
528 return TIOCSER_TEMT;
530 status = pmz_peek_status(to_pmz(port));
531 if (status & Tx_BUF_EMP)
532 return TIOCSER_TEMT;
533 return 0;
534 }
536 /*
537 * Set Modem Control (RTS & DTR) bits
538 * The port lock is held and interrupts are disabled.
539 * Note: Shall we really filter out RTS on external ports or
540 * should that be dealt at higher level only ?
541 */
542 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
543 {
544 struct uart_pmac_port *uap = to_pmz(port);
545 unsigned char set_bits, clear_bits;
547 /* Do nothing for irda for now... */
548 if (ZS_IS_IRDA(uap))
549 return;
550 /* We get called during boot with a port not up yet */
551 if (ZS_IS_ASLEEP(uap) ||
552 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
553 return;
555 set_bits = clear_bits = 0;
557 if (ZS_IS_INTMODEM(uap)) {
558 if (mctrl & TIOCM_RTS)
559 set_bits |= RTS;
560 else
561 clear_bits |= RTS;
562 }
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 uap->curregs[R5] |= set_bits;
570 uap->curregs[R5] &= ~clear_bits;
571 if (ZS_IS_ASLEEP(uap))
572 return;
573 write_zsreg(uap, R5, uap->curregs[R5]);
574 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
575 set_bits, clear_bits, uap->curregs[R5]);
576 zssync(uap);
577 }
579 /*
580 * Get Modem Control bits (only the input ones, the core will
581 * or that with a cached value of the control ones)
582 * The port lock is held and interrupts are disabled.
583 */
584 static unsigned int pmz_get_mctrl(struct uart_port *port)
585 {
586 struct uart_pmac_port *uap = to_pmz(port);
587 unsigned char status;
588 unsigned int ret;
590 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
591 return 0;
593 status = read_zsreg(uap, R0);
595 ret = 0;
596 if (status & DCD)
597 ret |= TIOCM_CAR;
598 if (status & SYNC_HUNT)
599 ret |= TIOCM_DSR;
600 if (!(status & CTS))
601 ret |= TIOCM_CTS;
603 return ret;
604 }
606 /*
607 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
608 * though for DMA, we will have to do a bit more.
609 * The port lock is held and interrupts are disabled.
610 */
611 static void pmz_stop_tx(struct uart_port *port)
612 {
613 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
614 }
616 /*
617 * Kick the Tx side.
618 * The port lock is held and interrupts are disabled.
619 */
620 static void pmz_start_tx(struct uart_port *port)
621 {
622 struct uart_pmac_port *uap = to_pmz(port);
623 unsigned char status;
625 pmz_debug("pmz: start_tx()\n");
627 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
628 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
630 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
631 return;
633 status = read_zsreg(uap, R0);
635 /* TX busy? Just wait for the TX done interrupt. */
636 if (!(status & Tx_BUF_EMP))
637 return;
639 /* Send the first character to jump-start the TX done
640 * IRQ sending engine.
641 */
642 if (port->x_char) {
643 write_zsdata(uap, port->x_char);
644 zssync(uap);
645 port->icount.tx++;
646 port->x_char = 0;
647 } else {
648 struct circ_buf *xmit = &port->info->xmit;
650 write_zsdata(uap, xmit->buf[xmit->tail]);
651 zssync(uap);
652 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
653 port->icount.tx++;
655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(&uap->port);
657 }
658 pmz_debug("pmz: start_tx() done.\n");
659 }
661 /*
662 * Stop Rx side, basically disable emitting of
663 * Rx interrupts on the port. We don't disable the rx
664 * side of the chip proper though
665 * The port lock is held.
666 */
667 static void pmz_stop_rx(struct uart_port *port)
668 {
669 struct uart_pmac_port *uap = to_pmz(port);
671 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
672 return;
674 pmz_debug("pmz: stop_rx()()\n");
676 /* Disable all RX interrupts. */
677 uap->curregs[R1] &= ~RxINT_MASK;
678 pmz_maybe_update_regs(uap);
680 pmz_debug("pmz: stop_rx() done.\n");
681 }
683 /*
684 * Enable modem status change interrupts
685 * The port lock is held.
686 */
687 static void pmz_enable_ms(struct uart_port *port)
688 {
689 struct uart_pmac_port *uap = to_pmz(port);
690 unsigned char new_reg;
692 if (ZS_IS_IRDA(uap) || uap->node == NULL)
693 return;
694 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
695 if (new_reg != uap->curregs[R15]) {
696 uap->curregs[R15] = new_reg;
698 if (ZS_IS_ASLEEP(uap))
699 return;
700 /* NOTE: Not subject to 'transmitter active' rule. */
701 write_zsreg(uap, R15, uap->curregs[R15]);
702 }
703 }
705 /*
706 * Control break state emission
707 * The port lock is not held.
708 */
709 static void pmz_break_ctl(struct uart_port *port, int break_state)
710 {
711 struct uart_pmac_port *uap = to_pmz(port);
712 unsigned char set_bits, clear_bits, new_reg;
713 unsigned long flags;
715 if (uap->node == NULL)
716 return;
717 set_bits = clear_bits = 0;
719 if (break_state)
720 set_bits |= SND_BRK;
721 else
722 clear_bits |= SND_BRK;
724 spin_lock_irqsave(&port->lock, flags);
726 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
727 if (new_reg != uap->curregs[R5]) {
728 uap->curregs[R5] = new_reg;
730 /* NOTE: Not subject to 'transmitter active' rule. */
731 if (ZS_IS_ASLEEP(uap))
732 return;
733 write_zsreg(uap, R5, uap->curregs[R5]);
734 }
736 spin_unlock_irqrestore(&port->lock, flags);
737 }
739 /*
740 * Turn power on or off to the SCC and associated stuff
741 * (port drivers, modem, IR port, etc.)
742 * Returns the number of milliseconds we should wait before
743 * trying to use the port.
744 */
745 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
746 {
747 int delay = 0;
748 int rc;
750 if (state) {
751 rc = pmac_call_feature(
752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
753 pmz_debug("port power on result: %d\n", rc);
754 if (ZS_IS_INTMODEM(uap)) {
755 rc = pmac_call_feature(
756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
757 delay = 2500; /* wait for 2.5s before using */
758 pmz_debug("modem power result: %d\n", rc);
759 }
760 } else {
761 /* TODO: Make that depend on a timer, don't power down
762 * immediately
763 */
764 if (ZS_IS_INTMODEM(uap)) {
765 rc = pmac_call_feature(
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
767 pmz_debug("port power off result: %d\n", rc);
768 }
769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
770 }
771 return delay;
772 }
774 /*
775 * FixZeroBug....Works around a bug in the SCC receving channel.
776 * Inspired from Darwin code, 15 Sept. 2000 -DanM
777 *
778 * The following sequence prevents a problem that is seen with O'Hare ASICs
779 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
780 * at the input to the receiver becomes 'stuck' and locks up the receiver.
781 * This problem can occur as a result of a zero bit at the receiver input
782 * coincident with any of the following events:
783 *
784 * The SCC is initialized (hardware or software).
785 * A framing error is detected.
786 * The clocking option changes from synchronous or X1 asynchronous
787 * clocking to X16, X32, or X64 asynchronous clocking.
788 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
789 *
790 * This workaround attempts to recover from the lockup condition by placing
791 * the SCC in synchronous loopback mode with a fast clock before programming
792 * any of the asynchronous modes.
793 */
794 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
795 {
796 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
797 zssync(uap);
798 udelay(10);
799 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
800 zssync(uap);
802 write_zsreg(uap, 4, X1CLK | MONSYNC);
803 write_zsreg(uap, 3, Rx8);
804 write_zsreg(uap, 5, Tx8 | RTS);
805 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
806 write_zsreg(uap, 11, RCBR | TCBR);
807 write_zsreg(uap, 12, 0);
808 write_zsreg(uap, 13, 0);
809 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
810 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
811 write_zsreg(uap, 3, Rx8 | RxENABLE);
812 write_zsreg(uap, 0, RES_EXT_INT);
813 write_zsreg(uap, 0, RES_EXT_INT);
814 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
816 /* The channel should be OK now, but it is probably receiving
817 * loopback garbage.
818 * Switch to asynchronous mode, disable the receiver,
819 * and discard everything in the receive buffer.
820 */
821 write_zsreg(uap, 9, NV);
822 write_zsreg(uap, 4, X16CLK | SB_MASK);
823 write_zsreg(uap, 3, Rx8);
825 while (read_zsreg(uap, 0) & Rx_CH_AV) {
826 (void)read_zsreg(uap, 8);
827 write_zsreg(uap, 0, RES_EXT_INT);
828 write_zsreg(uap, 0, ERR_RES);
829 }
830 }
832 /*
833 * Real startup routine, powers up the hardware and sets up
834 * the SCC. Returns a delay in ms where you need to wait before
835 * actually using the port, this is typically the internal modem
836 * powerup delay. This routine expect the lock to be taken.
837 */
838 static int __pmz_startup(struct uart_pmac_port *uap)
839 {
840 int pwr_delay = 0;
842 memset(&uap->curregs, 0, sizeof(uap->curregs));
844 /* Power up the SCC & underlying hardware (modem/irda) */
845 pwr_delay = pmz_set_scc_power(uap, 1);
847 /* Nice buggy HW ... */
848 pmz_fix_zero_bug_scc(uap);
850 /* Reset the channel */
851 uap->curregs[R9] = 0;
852 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
853 zssync(uap);
854 udelay(10);
855 write_zsreg(uap, 9, 0);
856 zssync(uap);
858 /* Clear the interrupt registers */
859 write_zsreg(uap, R1, 0);
860 write_zsreg(uap, R0, ERR_RES);
861 write_zsreg(uap, R0, ERR_RES);
862 write_zsreg(uap, R0, RES_H_IUS);
863 write_zsreg(uap, R0, RES_H_IUS);
865 /* Setup some valid baud rate */
866 uap->curregs[R4] = X16CLK | SB1;
867 uap->curregs[R3] = Rx8;
868 uap->curregs[R5] = Tx8 | RTS;
869 if (!ZS_IS_IRDA(uap))
870 uap->curregs[R5] |= DTR;
871 uap->curregs[R12] = 0;
872 uap->curregs[R13] = 0;
873 uap->curregs[R14] = BRENAB;
875 /* Clear handshaking, enable BREAK interrupts */
876 uap->curregs[R15] = BRKIE;
878 /* Master interrupt enable */
879 uap->curregs[R9] |= NV | MIE;
881 pmz_load_zsregs(uap, uap->curregs);
883 /* Enable receiver and transmitter. */
884 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
885 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
887 /* Remember status for DCD/CTS changes */
888 uap->prev_status = read_zsreg(uap, R0);
891 return pwr_delay;
892 }
894 static void pmz_irda_reset(struct uart_pmac_port *uap)
895 {
896 uap->curregs[R5] |= DTR;
897 write_zsreg(uap, R5, uap->curregs[R5]);
898 zssync(uap);
899 mdelay(110);
900 uap->curregs[R5] &= ~DTR;
901 write_zsreg(uap, R5, uap->curregs[R5]);
902 zssync(uap);
903 mdelay(10);
904 }
906 /*
907 * This is the "normal" startup routine, using the above one
908 * wrapped with the lock and doing a schedule delay
909 */
910 static int pmz_startup(struct uart_port *port)
911 {
912 struct uart_pmac_port *uap = to_pmz(port);
913 unsigned long flags;
914 int pwr_delay = 0;
916 pmz_debug("pmz: startup()\n");
918 if (ZS_IS_ASLEEP(uap))
919 return -EAGAIN;
920 if (uap->node == NULL)
921 return -ENODEV;
923 mutex_lock(&pmz_irq_mutex);
925 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
927 /* A console is never powered down. Else, power up and
928 * initialize the chip
929 */
930 if (!ZS_IS_CONS(uap)) {
931 spin_lock_irqsave(&port->lock, flags);
932 pwr_delay = __pmz_startup(uap);
933 spin_unlock_irqrestore(&port->lock, flags);
934 }
936 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
937 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, "PowerMac Zilog", uap)) {
938 dev_err(&uap->dev->ofdev.dev,
939 "Unable to register zs interrupt handler.\n");
940 pmz_set_scc_power(uap, 0);
941 mutex_unlock(&pmz_irq_mutex);
942 return -ENXIO;
943 }
945 mutex_unlock(&pmz_irq_mutex);
947 /* Right now, we deal with delay by blocking here, I'll be
948 * smarter later on
949 */
950 if (pwr_delay != 0) {
951 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
952 msleep(pwr_delay);
953 }
955 /* IrDA reset is done now */
956 if (ZS_IS_IRDA(uap))
957 pmz_irda_reset(uap);
959 /* Enable interrupts emission from the chip */
960 spin_lock_irqsave(&port->lock, flags);
961 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
962 if (!ZS_IS_EXTCLK(uap))
963 uap->curregs[R1] |= EXT_INT_ENAB;
964 write_zsreg(uap, R1, uap->curregs[R1]);
965 spin_unlock_irqrestore(&port->lock, flags);
967 pmz_debug("pmz: startup() done.\n");
969 return 0;
970 }
972 static void pmz_shutdown(struct uart_port *port)
973 {
974 struct uart_pmac_port *uap = to_pmz(port);
975 unsigned long flags;
977 pmz_debug("pmz: shutdown()\n");
979 if (uap->node == NULL)
980 return;
982 mutex_lock(&pmz_irq_mutex);
984 /* Release interrupt handler */
985 free_irq(uap->port.irq, uap);
987 spin_lock_irqsave(&port->lock, flags);
989 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
991 if (!ZS_IS_OPEN(uap->mate))
992 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
994 /* Disable interrupts */
995 if (!ZS_IS_ASLEEP(uap)) {
996 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
997 write_zsreg(uap, R1, uap->curregs[R1]);
998 zssync(uap);
999 }
1001 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1002 spin_unlock_irqrestore(&port->lock, flags);
1003 mutex_unlock(&pmz_irq_mutex);
1004 return;
1007 /* Disable receiver and transmitter. */
1008 uap->curregs[R3] &= ~RxENABLE;
1009 uap->curregs[R5] &= ~TxENABLE;
1011 /* Disable all interrupts and BRK assertion. */
1012 uap->curregs[R5] &= ~SND_BRK;
1013 pmz_maybe_update_regs(uap);
1015 /* Shut the chip down */
1016 pmz_set_scc_power(uap, 0);
1018 spin_unlock_irqrestore(&port->lock, flags);
1020 mutex_unlock(&pmz_irq_mutex);
1022 pmz_debug("pmz: shutdown() done.\n");
1025 /* Shared by TTY driver and serial console setup. The port lock is held
1026 * and local interrupts are disabled.
1027 */
1028 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1029 unsigned int iflag, unsigned long baud)
1031 int brg;
1034 /* Switch to external clocking for IrDA high clock rates. That
1035 * code could be re-used for Midi interfaces with different
1036 * multipliers
1037 */
1038 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1039 uap->curregs[R4] = X1CLK;
1040 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1041 uap->curregs[R14] = 0; /* BRG off */
1042 uap->curregs[R12] = 0;
1043 uap->curregs[R13] = 0;
1044 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1045 } else {
1046 switch (baud) {
1047 case ZS_CLOCK/16: /* 230400 */
1048 uap->curregs[R4] = X16CLK;
1049 uap->curregs[R11] = 0;
1050 uap->curregs[R14] = 0;
1051 break;
1052 case ZS_CLOCK/32: /* 115200 */
1053 uap->curregs[R4] = X32CLK;
1054 uap->curregs[R11] = 0;
1055 uap->curregs[R14] = 0;
1056 break;
1057 default:
1058 uap->curregs[R4] = X16CLK;
1059 uap->curregs[R11] = TCBR | RCBR;
1060 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1061 uap->curregs[R12] = (brg & 255);
1062 uap->curregs[R13] = ((brg >> 8) & 255);
1063 uap->curregs[R14] = BRENAB;
1065 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1068 /* Character size, stop bits, and parity. */
1069 uap->curregs[3] &= ~RxN_MASK;
1070 uap->curregs[5] &= ~TxN_MASK;
1072 switch (cflag & CSIZE) {
1073 case CS5:
1074 uap->curregs[3] |= Rx5;
1075 uap->curregs[5] |= Tx5;
1076 uap->parity_mask = 0x1f;
1077 break;
1078 case CS6:
1079 uap->curregs[3] |= Rx6;
1080 uap->curregs[5] |= Tx6;
1081 uap->parity_mask = 0x3f;
1082 break;
1083 case CS7:
1084 uap->curregs[3] |= Rx7;
1085 uap->curregs[5] |= Tx7;
1086 uap->parity_mask = 0x7f;
1087 break;
1088 case CS8:
1089 default:
1090 uap->curregs[3] |= Rx8;
1091 uap->curregs[5] |= Tx8;
1092 uap->parity_mask = 0xff;
1093 break;
1094 };
1095 uap->curregs[4] &= ~(SB_MASK);
1096 if (cflag & CSTOPB)
1097 uap->curregs[4] |= SB2;
1098 else
1099 uap->curregs[4] |= SB1;
1100 if (cflag & PARENB)
1101 uap->curregs[4] |= PAR_ENAB;
1102 else
1103 uap->curregs[4] &= ~PAR_ENAB;
1104 if (!(cflag & PARODD))
1105 uap->curregs[4] |= PAR_EVEN;
1106 else
1107 uap->curregs[4] &= ~PAR_EVEN;
1109 uap->port.read_status_mask = Rx_OVR;
1110 if (iflag & INPCK)
1111 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1112 if (iflag & (BRKINT | PARMRK))
1113 uap->port.read_status_mask |= BRK_ABRT;
1115 uap->port.ignore_status_mask = 0;
1116 if (iflag & IGNPAR)
1117 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1118 if (iflag & IGNBRK) {
1119 uap->port.ignore_status_mask |= BRK_ABRT;
1120 if (iflag & IGNPAR)
1121 uap->port.ignore_status_mask |= Rx_OVR;
1124 if ((cflag & CREAD) == 0)
1125 uap->port.ignore_status_mask = 0xff;
1129 /*
1130 * Set the irda codec on the imac to the specified baud rate.
1131 */
1132 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1134 u8 cmdbyte;
1135 int t, version;
1137 switch (*baud) {
1138 /* SIR modes */
1139 case 2400:
1140 cmdbyte = 0x53;
1141 break;
1142 case 4800:
1143 cmdbyte = 0x52;
1144 break;
1145 case 9600:
1146 cmdbyte = 0x51;
1147 break;
1148 case 19200:
1149 cmdbyte = 0x50;
1150 break;
1151 case 38400:
1152 cmdbyte = 0x4f;
1153 break;
1154 case 57600:
1155 cmdbyte = 0x4e;
1156 break;
1157 case 115200:
1158 cmdbyte = 0x4d;
1159 break;
1160 /* The FIR modes aren't really supported at this point, how
1161 * do we select the speed ? via the FCR on KeyLargo ?
1162 */
1163 case 1152000:
1164 cmdbyte = 0;
1165 break;
1166 case 4000000:
1167 cmdbyte = 0;
1168 break;
1169 default: /* 9600 */
1170 cmdbyte = 0x51;
1171 *baud = 9600;
1172 break;
1175 /* Wait for transmitter to drain */
1176 t = 10000;
1177 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1178 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1179 if (--t <= 0) {
1180 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1181 return;
1183 udelay(10);
1186 /* Drain the receiver too */
1187 t = 100;
1188 (void)read_zsdata(uap);
1189 (void)read_zsdata(uap);
1190 (void)read_zsdata(uap);
1191 mdelay(10);
1192 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1193 read_zsdata(uap);
1194 mdelay(10);
1195 if (--t <= 0) {
1196 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1197 return;
1201 /* Switch to command mode */
1202 uap->curregs[R5] |= DTR;
1203 write_zsreg(uap, R5, uap->curregs[R5]);
1204 zssync(uap);
1205 mdelay(1);
1207 /* Switch SCC to 19200 */
1208 pmz_convert_to_zs(uap, CS8, 0, 19200);
1209 pmz_load_zsregs(uap, uap->curregs);
1210 mdelay(1);
1212 /* Write get_version command byte */
1213 write_zsdata(uap, 1);
1214 t = 5000;
1215 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1216 if (--t <= 0) {
1217 dev_err(&uap->dev->ofdev.dev,
1218 "irda_setup timed out on get_version byte\n");
1219 goto out;
1221 udelay(10);
1223 version = read_zsdata(uap);
1225 if (version < 4) {
1226 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1227 version);
1228 goto out;
1231 /* Send speed mode */
1232 write_zsdata(uap, cmdbyte);
1233 t = 5000;
1234 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1235 if (--t <= 0) {
1236 dev_err(&uap->dev->ofdev.dev,
1237 "irda_setup timed out on speed mode byte\n");
1238 goto out;
1240 udelay(10);
1242 t = read_zsdata(uap);
1243 if (t != cmdbyte)
1244 dev_err(&uap->dev->ofdev.dev,
1245 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1247 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1248 *baud, version);
1250 (void)read_zsdata(uap);
1251 (void)read_zsdata(uap);
1252 (void)read_zsdata(uap);
1254 out:
1255 /* Switch back to data mode */
1256 uap->curregs[R5] &= ~DTR;
1257 write_zsreg(uap, R5, uap->curregs[R5]);
1258 zssync(uap);
1260 (void)read_zsdata(uap);
1261 (void)read_zsdata(uap);
1262 (void)read_zsdata(uap);
1266 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1267 struct termios *old)
1269 struct uart_pmac_port *uap = to_pmz(port);
1270 unsigned long baud;
1272 pmz_debug("pmz: set_termios()\n");
1274 if (ZS_IS_ASLEEP(uap))
1275 return;
1277 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1279 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1280 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1281 * about the FIR mode and high speed modes. So these are unused. For
1282 * implementing proper support for these, we should probably add some
1283 * DMA as well, at least on the Rx side, which isn't a simple thing
1284 * at this point.
1285 */
1286 if (ZS_IS_IRDA(uap)) {
1287 /* Calc baud rate */
1288 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1289 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1290 /* Cet the irda codec to the right rate */
1291 pmz_irda_setup(uap, &baud);
1292 /* Set final baud rate */
1293 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1294 pmz_load_zsregs(uap, uap->curregs);
1295 zssync(uap);
1296 } else {
1297 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1298 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1299 /* Make sure modem status interrupts are correctly configured */
1300 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1301 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1302 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1303 } else {
1304 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1305 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1308 /* Load registers to the chip */
1309 pmz_maybe_update_regs(uap);
1311 uart_update_timeout(port, termios->c_cflag, baud);
1313 pmz_debug("pmz: set_termios() done.\n");
1316 /* The port lock is not held. */
1317 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1318 struct termios *old)
1320 struct uart_pmac_port *uap = to_pmz(port);
1321 unsigned long flags;
1323 spin_lock_irqsave(&port->lock, flags);
1325 /* Disable IRQs on the port */
1326 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1327 write_zsreg(uap, R1, uap->curregs[R1]);
1329 /* Setup new port configuration */
1330 __pmz_set_termios(port, termios, old);
1332 /* Re-enable IRQs on the port */
1333 if (ZS_IS_OPEN(uap)) {
1334 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1335 if (!ZS_IS_EXTCLK(uap))
1336 uap->curregs[R1] |= EXT_INT_ENAB;
1337 write_zsreg(uap, R1, uap->curregs[R1]);
1339 spin_unlock_irqrestore(&port->lock, flags);
1342 static const char *pmz_type(struct uart_port *port)
1344 struct uart_pmac_port *uap = to_pmz(port);
1346 if (ZS_IS_IRDA(uap))
1347 return "Z85c30 ESCC - Infrared port";
1348 else if (ZS_IS_INTMODEM(uap))
1349 return "Z85c30 ESCC - Internal modem";
1350 return "Z85c30 ESCC - Serial port";
1353 /* We do not request/release mappings of the registers here, this
1354 * happens at early serial probe time.
1355 */
1356 static void pmz_release_port(struct uart_port *port)
1360 static int pmz_request_port(struct uart_port *port)
1362 return 0;
1365 /* These do not need to do anything interesting either. */
1366 static void pmz_config_port(struct uart_port *port, int flags)
1370 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1371 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1373 return -EINVAL;
1376 static struct uart_ops pmz_pops = {
1377 .tx_empty = pmz_tx_empty,
1378 .set_mctrl = pmz_set_mctrl,
1379 .get_mctrl = pmz_get_mctrl,
1380 .stop_tx = pmz_stop_tx,
1381 .start_tx = pmz_start_tx,
1382 .stop_rx = pmz_stop_rx,
1383 .enable_ms = pmz_enable_ms,
1384 .break_ctl = pmz_break_ctl,
1385 .startup = pmz_startup,
1386 .shutdown = pmz_shutdown,
1387 .set_termios = pmz_set_termios,
1388 .type = pmz_type,
1389 .release_port = pmz_release_port,
1390 .request_port = pmz_request_port,
1391 .config_port = pmz_config_port,
1392 .verify_port = pmz_verify_port,
1393 };
1395 /*
1396 * Setup one port structure after probing, HW is down at this point,
1397 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1398 * register our console before uart_add_one_port() is called
1399 */
1400 static int __init pmz_init_port(struct uart_pmac_port *uap)
1402 struct device_node *np = uap->node;
1403 char *conn;
1404 struct slot_names_prop {
1405 int count;
1406 char name[1];
1407 } *slots;
1408 int len;
1409 struct resource r_ports, r_rxdma, r_txdma;
1411 /*
1412 * Request & map chip registers
1413 */
1414 if (of_address_to_resource(np, 0, &r_ports))
1415 return -ENODEV;
1416 uap->port.mapbase = r_ports.start;
1417 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1419 uap->control_reg = uap->port.membase;
1420 uap->data_reg = uap->control_reg + 0x10;
1422 /*
1423 * Request & map DBDMA registers
1424 */
1425 #ifdef HAS_DBDMA
1426 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1427 of_address_to_resource(np, 2, &r_rxdma) == 0)
1428 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1429 #else
1430 memset(&r_txdma, 0, sizeof(struct resource));
1431 memset(&r_rxdma, 0, sizeof(struct resource));
1432 #endif
1433 if (ZS_HAS_DMA(uap)) {
1434 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1435 if (uap->tx_dma_regs == NULL) {
1436 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1437 goto no_dma;
1439 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1440 if (uap->rx_dma_regs == NULL) {
1441 iounmap(uap->tx_dma_regs);
1442 uap->tx_dma_regs = NULL;
1443 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1444 goto no_dma;
1446 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1447 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1449 no_dma:
1451 /*
1452 * Detect port type
1453 */
1454 if (device_is_compatible(np, "cobalt"))
1455 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1456 conn = get_property(np, "AAPL,connector", &len);
1457 if (conn && (strcmp(conn, "infrared") == 0))
1458 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1459 uap->port_type = PMAC_SCC_ASYNC;
1460 /* 1999 Powerbook G3 has slot-names property instead */
1461 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
1462 if (slots && slots->count > 0) {
1463 if (strcmp(slots->name, "IrDA") == 0)
1464 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1465 else if (strcmp(slots->name, "Modem") == 0)
1466 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1468 if (ZS_IS_IRDA(uap))
1469 uap->port_type = PMAC_SCC_IRDA;
1470 if (ZS_IS_INTMODEM(uap)) {
1471 struct device_node* i2c_modem = find_devices("i2c-modem");
1472 if (i2c_modem) {
1473 char* mid = get_property(i2c_modem, "modem-id", NULL);
1474 if (mid) switch(*mid) {
1475 case 0x04 :
1476 case 0x05 :
1477 case 0x07 :
1478 case 0x08 :
1479 case 0x0b :
1480 case 0x0c :
1481 uap->port_type = PMAC_SCC_I2S1;
1483 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1484 mid ? (*mid) : 0);
1485 } else {
1486 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1490 /*
1491 * Init remaining bits of "port" structure
1492 */
1493 uap->port.iotype = UPIO_MEM;
1494 uap->port.irq = irq_of_parse_and_map(np, 0);
1495 uap->port.uartclk = ZS_CLOCK;
1496 uap->port.fifosize = 1;
1497 uap->port.ops = &pmz_pops;
1498 uap->port.type = PORT_PMAC_ZILOG;
1499 uap->port.flags = 0;
1501 /* Setup some valid baud rate information in the register
1502 * shadows so we don't write crap there before baud rate is
1503 * first initialized.
1504 */
1505 pmz_convert_to_zs(uap, CS8, 0, 9600);
1507 return 0;
1510 /*
1511 * Get rid of a port on module removal
1512 */
1513 static void pmz_dispose_port(struct uart_pmac_port *uap)
1515 struct device_node *np;
1517 np = uap->node;
1518 iounmap(uap->rx_dma_regs);
1519 iounmap(uap->tx_dma_regs);
1520 iounmap(uap->control_reg);
1521 uap->node = NULL;
1522 of_node_put(np);
1523 memset(uap, 0, sizeof(struct uart_pmac_port));
1526 /*
1527 * Called upon match with an escc node in the devive-tree.
1528 */
1529 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1531 int i;
1533 /* Iterate the pmz_ports array to find a matching entry
1534 */
1535 for (i = 0; i < MAX_ZS_PORTS; i++)
1536 if (pmz_ports[i].node == mdev->ofdev.node) {
1537 struct uart_pmac_port *uap = &pmz_ports[i];
1539 uap->dev = mdev;
1540 dev_set_drvdata(&mdev->ofdev.dev, uap);
1541 if (macio_request_resources(uap->dev, "pmac_zilog"))
1542 printk(KERN_WARNING "%s: Failed to request resource"
1543 ", port still active\n",
1544 uap->node->name);
1545 else
1546 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1547 return 0;
1549 return -ENODEV;
1552 /*
1553 * That one should not be called, macio isn't really a hotswap device,
1554 * we don't expect one of those serial ports to go away...
1555 */
1556 static int pmz_detach(struct macio_dev *mdev)
1558 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1560 if (!uap)
1561 return -ENODEV;
1563 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1564 macio_release_resources(uap->dev);
1565 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1567 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1568 uap->dev = NULL;
1570 return 0;
1574 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1576 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1577 struct uart_state *state;
1578 unsigned long flags;
1580 if (uap == NULL) {
1581 printk("HRM... pmz_suspend with NULL uap\n");
1582 return 0;
1585 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1586 return 0;
1588 pmz_debug("suspend, switching to state %d\n", pm_state);
1590 state = pmz_uart_reg.state + uap->port.line;
1592 mutex_lock(&pmz_irq_mutex);
1593 mutex_lock(&state->mutex);
1595 spin_lock_irqsave(&uap->port.lock, flags);
1597 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1598 /* Disable receiver and transmitter. */
1599 uap->curregs[R3] &= ~RxENABLE;
1600 uap->curregs[R5] &= ~TxENABLE;
1602 /* Disable all interrupts and BRK assertion. */
1603 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1604 uap->curregs[R5] &= ~SND_BRK;
1605 pmz_load_zsregs(uap, uap->curregs);
1606 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1607 mb();
1610 spin_unlock_irqrestore(&uap->port.lock, flags);
1612 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1613 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1614 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1615 disable_irq(uap->port.irq);
1618 if (ZS_IS_CONS(uap))
1619 uap->port.cons->flags &= ~CON_ENABLED;
1621 /* Shut the chip down */
1622 pmz_set_scc_power(uap, 0);
1624 mutex_unlock(&state->mutex);
1625 mutex_unlock(&pmz_irq_mutex);
1627 pmz_debug("suspend, switching complete\n");
1629 mdev->ofdev.dev.power.power_state = pm_state;
1631 return 0;
1635 static int pmz_resume(struct macio_dev *mdev)
1637 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1638 struct uart_state *state;
1639 unsigned long flags;
1640 int pwr_delay = 0;
1642 if (uap == NULL)
1643 return 0;
1645 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1646 return 0;
1648 pmz_debug("resume, switching to state 0\n");
1650 state = pmz_uart_reg.state + uap->port.line;
1652 mutex_lock(&pmz_irq_mutex);
1653 mutex_lock(&state->mutex);
1655 spin_lock_irqsave(&uap->port.lock, flags);
1656 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1657 spin_unlock_irqrestore(&uap->port.lock, flags);
1658 goto bail;
1660 pwr_delay = __pmz_startup(uap);
1662 /* Take care of config that may have changed while asleep */
1663 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1665 if (ZS_IS_OPEN(uap)) {
1666 /* Enable interrupts */
1667 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1668 if (!ZS_IS_EXTCLK(uap))
1669 uap->curregs[R1] |= EXT_INT_ENAB;
1670 write_zsreg(uap, R1, uap->curregs[R1]);
1673 spin_unlock_irqrestore(&uap->port.lock, flags);
1675 if (ZS_IS_CONS(uap))
1676 uap->port.cons->flags |= CON_ENABLED;
1678 /* Re-enable IRQ on the controller */
1679 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1680 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1681 enable_irq(uap->port.irq);
1684 bail:
1685 mutex_unlock(&state->mutex);
1686 mutex_unlock(&pmz_irq_mutex);
1688 /* Right now, we deal with delay by blocking here, I'll be
1689 * smarter later on
1690 */
1691 if (pwr_delay != 0) {
1692 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1693 msleep(pwr_delay);
1696 pmz_debug("resume, switching complete\n");
1698 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1700 return 0;
1703 /*
1704 * Probe all ports in the system and build the ports array, we register
1705 * with the serial layer at this point, the macio-type probing is only
1706 * used later to "attach" to the sysfs tree so we get power management
1707 * events
1708 */
1709 static int __init pmz_probe(void)
1711 struct device_node *node_p, *node_a, *node_b, *np;
1712 int count = 0;
1713 int rc;
1715 /*
1716 * Find all escc chips in the system
1717 */
1718 node_p = of_find_node_by_name(NULL, "escc");
1719 while (node_p) {
1720 /*
1721 * First get channel A/B node pointers
1723 * TODO: Add routines with proper locking to do that...
1724 */
1725 node_a = node_b = NULL;
1726 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1727 if (strncmp(np->name, "ch-a", 4) == 0)
1728 node_a = of_node_get(np);
1729 else if (strncmp(np->name, "ch-b", 4) == 0)
1730 node_b = of_node_get(np);
1732 if (!node_a && !node_b) {
1733 of_node_put(node_a);
1734 of_node_put(node_b);
1735 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1736 (!node_a) ? 'a' : 'b', node_p->full_name);
1737 goto next;
1740 /*
1741 * Fill basic fields in the port structures
1742 */
1743 pmz_ports[count].mate = &pmz_ports[count+1];
1744 pmz_ports[count+1].mate = &pmz_ports[count];
1745 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1746 pmz_ports[count].node = node_a;
1747 pmz_ports[count+1].node = node_b;
1748 pmz_ports[count].port.line = count;
1749 pmz_ports[count+1].port.line = count+1;
1751 /*
1752 * Setup the ports for real
1753 */
1754 rc = pmz_init_port(&pmz_ports[count]);
1755 if (rc == 0 && node_b != NULL)
1756 rc = pmz_init_port(&pmz_ports[count+1]);
1757 if (rc != 0) {
1758 of_node_put(node_a);
1759 of_node_put(node_b);
1760 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1761 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1762 goto next;
1764 count += 2;
1765 next:
1766 node_p = of_find_node_by_name(node_p, "escc");
1768 pmz_ports_count = count;
1770 return 0;
1773 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1775 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1776 static int __init pmz_console_setup(struct console *co, char *options);
1778 static struct console pmz_console = {
1779 .name = "ttyS",
1780 .write = pmz_console_write,
1781 .device = uart_console_device,
1782 .setup = pmz_console_setup,
1783 .flags = CON_PRINTBUFFER,
1784 .index = -1,
1785 .data = &pmz_uart_reg,
1786 };
1788 #define PMACZILOG_CONSOLE &pmz_console
1789 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1790 #define PMACZILOG_CONSOLE (NULL)
1791 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1793 /*
1794 * Register the driver, console driver and ports with the serial
1795 * core
1796 */
1797 static int __init pmz_register(void)
1799 int i, rc;
1801 pmz_uart_reg.nr = pmz_ports_count;
1802 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1803 pmz_uart_reg.minor = 64;
1805 /*
1806 * Register this driver with the serial core
1807 */
1808 rc = uart_register_driver(&pmz_uart_reg);
1809 if (rc)
1810 return rc;
1812 /*
1813 * Register each port with the serial core
1814 */
1815 for (i = 0; i < pmz_ports_count; i++) {
1816 struct uart_pmac_port *uport = &pmz_ports[i];
1817 /* NULL node may happen on wallstreet */
1818 if (uport->node != NULL)
1819 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1820 if (rc)
1821 goto err_out;
1824 return 0;
1825 err_out:
1826 while (i-- > 0) {
1827 struct uart_pmac_port *uport = &pmz_ports[i];
1828 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1830 uart_unregister_driver(&pmz_uart_reg);
1831 return rc;
1834 static struct of_device_id pmz_match[] =
1837 .name = "ch-a",
1838 },
1840 .name = "ch-b",
1841 },
1842 {},
1843 };
1844 MODULE_DEVICE_TABLE (of, pmz_match);
1846 static struct macio_driver pmz_driver =
1848 .name = "pmac_zilog",
1849 .match_table = pmz_match,
1850 .probe = pmz_attach,
1851 .remove = pmz_detach,
1852 .suspend = pmz_suspend,
1853 .resume = pmz_resume,
1854 };
1856 static int __init init_pmz(void)
1858 int rc, i;
1859 printk(KERN_INFO "%s\n", version);
1861 /*
1862 * First, we need to do a direct OF-based probe pass. We
1863 * do that because we want serial console up before the
1864 * macio stuffs calls us back, and since that makes it
1865 * easier to pass the proper number of channels to
1866 * uart_register_driver()
1867 */
1868 if (pmz_ports_count == 0)
1869 pmz_probe();
1871 /*
1872 * Bail early if no port found
1873 */
1874 if (pmz_ports_count == 0)
1875 return -ENODEV;
1877 /*
1878 * Now we register with the serial layer
1879 */
1880 rc = pmz_register();
1881 if (rc) {
1882 printk(KERN_ERR
1883 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1884 "pmac_zilog: Did another serial driver already claim the minors?\n");
1885 /* effectively "pmz_unprobe()" */
1886 for (i=0; i < pmz_ports_count; i++)
1887 pmz_dispose_port(&pmz_ports[i]);
1888 return rc;
1891 /*
1892 * Then we register the macio driver itself
1893 */
1894 return macio_register_driver(&pmz_driver);
1897 static void __exit exit_pmz(void)
1899 int i;
1901 /* Get rid of macio-driver (detach from macio) */
1902 macio_unregister_driver(&pmz_driver);
1904 for (i = 0; i < pmz_ports_count; i++) {
1905 struct uart_pmac_port *uport = &pmz_ports[i];
1906 if (uport->node != NULL) {
1907 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1908 pmz_dispose_port(uport);
1911 /* Unregister UART driver */
1912 uart_unregister_driver(&pmz_uart_reg);
1915 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1917 static void pmz_console_putchar(struct uart_port *port, int ch)
1919 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1921 /* Wait for the transmit buffer to empty. */
1922 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1923 udelay(5);
1924 write_zsdata(uap, ch);
1927 /*
1928 * Print a string to the serial port trying not to disturb
1929 * any possible real use of the port...
1930 */
1931 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1933 struct uart_pmac_port *uap = &pmz_ports[con->index];
1934 unsigned long flags;
1936 if (ZS_IS_ASLEEP(uap))
1937 return;
1938 spin_lock_irqsave(&uap->port.lock, flags);
1940 /* Turn of interrupts and enable the transmitter. */
1941 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1942 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1944 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1946 /* Restore the values in the registers. */
1947 write_zsreg(uap, R1, uap->curregs[1]);
1948 /* Don't disable the transmitter. */
1950 spin_unlock_irqrestore(&uap->port.lock, flags);
1953 /*
1954 * Setup the serial console
1955 */
1956 static int __init pmz_console_setup(struct console *co, char *options)
1958 struct uart_pmac_port *uap;
1959 struct uart_port *port;
1960 int baud = 38400;
1961 int bits = 8;
1962 int parity = 'n';
1963 int flow = 'n';
1964 unsigned long pwr_delay;
1966 /*
1967 * XServe's default to 57600 bps
1968 */
1969 if (machine_is_compatible("RackMac1,1")
1970 || machine_is_compatible("RackMac1,2")
1971 || machine_is_compatible("MacRISC4"))
1972 baud = 57600;
1974 /*
1975 * Check whether an invalid uart number has been specified, and
1976 * if so, search for the first available port that does have
1977 * console support.
1978 */
1979 if (co->index >= pmz_ports_count)
1980 co->index = 0;
1981 uap = &pmz_ports[co->index];
1982 if (uap->node == NULL)
1983 return -ENODEV;
1984 port = &uap->port;
1986 /*
1987 * Mark port as beeing a console
1988 */
1989 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1991 /*
1992 * Temporary fix for uart layer who didn't setup the spinlock yet
1993 */
1994 spin_lock_init(&port->lock);
1996 /*
1997 * Enable the hardware
1998 */
1999 pwr_delay = __pmz_startup(uap);
2000 if (pwr_delay)
2001 mdelay(pwr_delay);
2003 if (options)
2004 uart_parse_options(options, &baud, &parity, &bits, &flow);
2006 return uart_set_options(port, co, baud, parity, bits, flow);
2009 static int __init pmz_console_init(void)
2011 /* Probe ports */
2012 pmz_probe();
2014 /* TODO: Autoprobe console based on OF */
2015 /* pmz_console.index = i; */
2016 register_console(&pmz_console);
2018 return 0;
2021 console_initcall(pmz_console_init);
2022 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2024 module_init(init_pmz);
2025 module_exit(exit_pmz);