ia64/linux-2.6.18-xen.hg

view drivers/serial/ioc4_serial.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
10 /*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15 #include <linux/errno.h>
16 #include <linux/tty.h>
17 #include <linux/serial.h>
18 #include <linux/serialP.h>
19 #include <linux/circ_buf.h>
20 #include <linux/serial_reg.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/ioc4.h>
24 #include <linux/serial_core.h>
26 /*
27 * interesting things about the ioc4
28 */
30 #define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31 #define IOC4_NUM_CARDS 8 /* max cards per partition */
33 #define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
36 (IOC4_SIO_IR_S3)
38 #define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
44 /*
45 * All IOC4 registers are 32 bits wide.
46 */
48 /*
49 * PCI Memory Space Map
50 */
51 #define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52 #define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53 #define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54 #define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55 #define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56 #define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57 #define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
59 /* Interrupt types */
60 #define IOC4_SIO_INTR_TYPE 0
61 #define IOC4_OTHER_INTR_TYPE 1
62 #define IOC4_NUM_INTR_TYPES 2
64 /* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65 #define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66 #define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67 #define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68 #define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69 #define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70 #define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71 #define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72 #define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73 #define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74 #define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75 #define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76 #define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77 #define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78 #define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79 #define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80 #define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81 #define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82 #define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83 #define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84 #define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85 #define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86 #define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87 #define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88 #define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89 #define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90 #define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91 #define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92 #define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93 #define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94 #define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95 #define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96 #define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
98 /* Per device interrupt masks */
99 #define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107 #define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115 #define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123 #define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
132 /* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
133 #define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134 #define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135 #define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136 #define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137 #define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138 #define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139 #define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
140 #define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
141 #define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
142 #define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
144 #define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
145 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
147 /* Bitmasks for IOC4_SIO_CR */
148 #define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
149 #define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
150 #define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
151 #define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
152 #define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
153 #define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
154 #define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
155 #define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
156 #define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
157 #define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
158 serial ports (ro) */
159 /* Defs for some of the generic I/O pins */
160 #define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
161 mode sel */
162 #define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
163 mode sel */
164 #define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
165 mode sel */
166 #define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
167 mode sel */
169 #define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
170 uart 0 mode select */
171 #define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
172 uart 1 mode select */
173 #define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
174 uart 2 mode select */
175 #define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
176 uart 3 mode select */
178 /* Bitmasks for serial RX status byte */
179 #define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
180 #define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
181 #define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
182 #define IOC4_RXSB_BREAK 0x08 /* Break character */
183 #define IOC4_RXSB_CTS 0x10 /* State of CTS */
184 #define IOC4_RXSB_DCD 0x20 /* State of DCD */
185 #define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
186 #define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
187 * & BREAK valid */
189 /* Bitmasks for serial TX control byte */
190 #define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
191 #define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
192 #define IOC4_TXCB_VALID 0x40 /* Byte is valid */
193 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
194 #define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
196 /* Bitmasks for IOC4_SBBR_L */
197 #define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
199 /* Bitmasks for IOC4_SSCR_<3:0> */
200 #define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
201 #define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
202 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
203 #define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
204 #define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
205 #define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
206 #define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
207 #define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
208 #define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
209 #define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
210 #define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
212 /* All producer/comsumer pointers are the same bitfield */
213 #define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
214 #define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
215 #define IOC4_PROD_CONS_PTR_OFF 3
217 /* Bitmasks for IOC4_SRCIR_<3:0> */
218 #define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
220 /* Bitmasks for IOC4_SHADOW_<3:0> */
221 #define IOC4_SHADOW_DR 0x00000001 /* Data ready */
222 #define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
223 #define IOC4_SHADOW_PE 0x00000004 /* Parity error */
224 #define IOC4_SHADOW_FE 0x00000008 /* Framing error */
225 #define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
226 #define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
227 #define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
228 #define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
229 #define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
230 #define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
231 #define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
232 #define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
233 #define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
234 #define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
235 #define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
236 #define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
237 #define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
239 /* Bitmasks for IOC4_SRTR_<3:0> */
240 #define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
241 #define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
242 #define IOC4_SRTR_CNT_VAL_SHIFT 16
243 #define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
245 /* Serial port register map used for DMA and PIO serial I/O */
246 struct ioc4_serialregs {
247 uint32_t sscr;
248 uint32_t stpir;
249 uint32_t stcir;
250 uint32_t srpir;
251 uint32_t srcir;
252 uint32_t srtr;
253 uint32_t shadow;
254 };
256 /* IOC4 UART register map */
257 struct ioc4_uartregs {
258 char i4u_lcr;
259 union {
260 char iir; /* read only */
261 char fcr; /* write only */
262 } u3;
263 union {
264 char ier; /* DLAB == 0 */
265 char dlm; /* DLAB == 1 */
266 } u2;
267 union {
268 char rbr; /* read only, DLAB == 0 */
269 char thr; /* write only, DLAB == 0 */
270 char dll; /* DLAB == 1 */
271 } u1;
272 char i4u_scr;
273 char i4u_msr;
274 char i4u_lsr;
275 char i4u_mcr;
276 };
278 /* short names */
279 #define i4u_dll u1.dll
280 #define i4u_ier u2.ier
281 #define i4u_dlm u2.dlm
282 #define i4u_fcr u3.fcr
284 /* Serial port registers used for DMA serial I/O */
285 struct ioc4_serial {
286 uint32_t sbbr01_l;
287 uint32_t sbbr01_h;
288 uint32_t sbbr23_l;
289 uint32_t sbbr23_h;
291 struct ioc4_serialregs port_0;
292 struct ioc4_serialregs port_1;
293 struct ioc4_serialregs port_2;
294 struct ioc4_serialregs port_3;
295 struct ioc4_uartregs uart_0;
296 struct ioc4_uartregs uart_1;
297 struct ioc4_uartregs uart_2;
298 struct ioc4_uartregs uart_3;
299 } ioc4_serial;
301 /* UART clock speed */
302 #define IOC4_SER_XIN_CLK_66 66666667
303 #define IOC4_SER_XIN_CLK_33 33333333
305 #define IOC4_W_IES 0
306 #define IOC4_W_IEC 1
308 typedef void ioc4_intr_func_f(void *, uint32_t);
309 typedef ioc4_intr_func_f *ioc4_intr_func_t;
311 static unsigned int Num_of_ioc4_cards;
313 /* defining this will get you LOTS of great debug info */
314 //#define DEBUG_INTERRUPTS
315 #define DPRINT_CONFIG(_x...) ;
316 //#define DPRINT_CONFIG(_x...) printk _x
318 /* number of characters left in xmit buffer before we ask for more */
319 #define WAKEUP_CHARS 256
321 /* number of characters we want to transmit to the lower level at a time */
322 #define IOC4_MAX_CHARS 256
323 #define IOC4_FIFO_CHARS 255
325 /* Device name we're using */
326 #define DEVICE_NAME_RS232 "ttyIOC"
327 #define DEVICE_NAME_RS422 "ttyAIOC"
328 #define DEVICE_MAJOR 204
329 #define DEVICE_MINOR_RS232 50
330 #define DEVICE_MINOR_RS422 84
333 /* register offsets */
334 #define IOC4_SERIAL_OFFSET 0x300
336 /* flags for next_char_state */
337 #define NCS_BREAK 0x1
338 #define NCS_PARITY 0x2
339 #define NCS_FRAMING 0x4
340 #define NCS_OVERRUN 0x8
342 /* cause we need SOME parameters ... */
343 #define MIN_BAUD_SUPPORTED 1200
344 #define MAX_BAUD_SUPPORTED 115200
346 /* protocol types supported */
347 #define PROTO_RS232 3
348 #define PROTO_RS422 7
350 /* Notification types */
351 #define N_DATA_READY 0x01
352 #define N_OUTPUT_LOWAT 0x02
353 #define N_BREAK 0x04
354 #define N_PARITY_ERROR 0x08
355 #define N_FRAMING_ERROR 0x10
356 #define N_OVERRUN_ERROR 0x20
357 #define N_DDCD 0x40
358 #define N_DCTS 0x80
360 #define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
361 N_PARITY_ERROR | N_FRAMING_ERROR | \
362 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
364 #define N_ALL_OUTPUT N_OUTPUT_LOWAT
366 #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
368 #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
369 N_PARITY_ERROR | N_FRAMING_ERROR | \
370 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
372 #define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
373 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
375 /* Some masks */
376 #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
377 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
378 #define LCR_MASK_STOP_BITS (UART_LCR_STOP)
380 #define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
381 #define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
383 /* Default to 4k buffers */
384 #ifdef IOC4_1K_BUFFERS
385 #define RING_BUF_SIZE 1024
386 #define IOC4_BUF_SIZE_BIT 0
387 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
388 #else
389 #define RING_BUF_SIZE 4096
390 #define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
391 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
392 #endif
394 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
396 /*
397 * This is the entry saved by the driver - one per card
398 */
400 #define UART_PORT_MIN 0
401 #define UART_PORT_RS232 UART_PORT_MIN
402 #define UART_PORT_RS422 1
403 #define UART_PORT_COUNT 2 /* one for each mode */
405 struct ioc4_control {
406 int ic_irq;
407 struct {
408 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
409 struct uart_port icp_uart_port[UART_PORT_COUNT];
410 /* Handy reference material */
411 struct ioc4_port *icp_port;
412 } ic_port[IOC4_NUM_SERIAL_PORTS];
413 struct ioc4_soft *ic_soft;
414 };
416 /*
417 * per-IOC4 data structure
418 */
419 #define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
420 struct ioc4_soft {
421 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
422 struct ioc4_serial __iomem *is_ioc4_serial_addr;
424 /* Each interrupt type has an entry in the array */
425 struct ioc4_intr_type {
427 /*
428 * Each in-use entry in this array contains at least
429 * one nonzero bit in sd_bits; no two entries in this
430 * array have overlapping sd_bits values.
431 */
432 struct ioc4_intr_info {
433 uint32_t sd_bits;
434 ioc4_intr_func_f *sd_intr;
435 void *sd_info;
436 } is_intr_info[MAX_IOC4_INTR_ENTS];
438 /* Number of entries active in the above array */
439 atomic_t is_num_intrs;
440 } is_intr_type[IOC4_NUM_INTR_TYPES];
442 /* is_ir_lock must be held while
443 * modifying sio_ie values, so
444 * we can be sure that sio_ie is
445 * not changing when we read it
446 * along with sio_ir.
447 */
448 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
449 };
451 /* Local port info for each IOC4 serial ports */
452 struct ioc4_port {
453 struct uart_port *ip_port; /* current active port ptr */
454 /* Ptrs for all ports */
455 struct uart_port *ip_all_ports[UART_PORT_COUNT];
456 /* Back ptrs for this port */
457 struct ioc4_control *ip_control;
458 struct pci_dev *ip_pdev;
459 struct ioc4_soft *ip_ioc4_soft;
461 /* pci mem addresses */
462 struct ioc4_misc_regs __iomem *ip_mem;
463 struct ioc4_serial __iomem *ip_serial;
464 struct ioc4_serialregs __iomem *ip_serial_regs;
465 struct ioc4_uartregs __iomem *ip_uart_regs;
467 /* Ring buffer page for this port */
468 dma_addr_t ip_dma_ringbuf;
469 /* vaddr of ring buffer */
470 struct ring_buffer *ip_cpu_ringbuf;
472 /* Rings for this port */
473 struct ring *ip_inring;
474 struct ring *ip_outring;
476 /* Hook to port specific values */
477 struct hooks *ip_hooks;
479 spinlock_t ip_lock;
481 /* Various rx/tx parameters */
482 int ip_baud;
483 int ip_tx_lowat;
484 int ip_rx_timeout;
486 /* Copy of notification bits */
487 int ip_notify;
489 /* Shadow copies of various registers so we don't need to PIO
490 * read them constantly
491 */
492 uint32_t ip_ienb; /* Enabled interrupts */
493 uint32_t ip_sscr;
494 uint32_t ip_tx_prod;
495 uint32_t ip_rx_cons;
496 int ip_pci_bus_speed;
497 unsigned char ip_flags;
498 };
500 /* tx low water mark. We need to notify the driver whenever tx is getting
501 * close to empty so it can refill the tx buffer and keep things going.
502 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
503 * have no trouble getting in more chars in time (I certainly hope so).
504 */
505 #define TX_LOWAT_LATENCY 1000
506 #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
507 #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
509 /* Flags per port */
510 #define INPUT_HIGH 0x01
511 #define DCD_ON 0x02
512 #define LOWAT_WRITTEN 0x04
513 #define READ_ABORTED 0x08
514 #define PORT_ACTIVE 0x10
515 #define PORT_INACTIVE 0 /* This is the value when "off" */
518 /* Since each port has different register offsets and bitmasks
519 * for everything, we'll store those that we need in tables so we
520 * don't have to be constantly checking the port we are dealing with.
521 */
522 struct hooks {
523 uint32_t intr_delta_dcd;
524 uint32_t intr_delta_cts;
525 uint32_t intr_tx_mt;
526 uint32_t intr_rx_timer;
527 uint32_t intr_rx_high;
528 uint32_t intr_tx_explicit;
529 uint32_t intr_dma_error;
530 uint32_t intr_clear;
531 uint32_t intr_all;
532 int rs422_select_pin;
533 };
535 static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
536 /* Values for port 0 */
537 {
538 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
539 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
540 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
541 IOC4_OTHER_IR_S0_MEMERR,
542 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
543 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
544 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
545 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
546 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
547 },
549 /* Values for port 1 */
550 {
551 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
552 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
553 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
554 IOC4_OTHER_IR_S1_MEMERR,
555 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
556 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
557 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
558 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
559 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
560 },
562 /* Values for port 2 */
563 {
564 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
565 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
566 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
567 IOC4_OTHER_IR_S2_MEMERR,
568 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
569 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
570 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
571 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
572 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
573 },
575 /* Values for port 3 */
576 {
577 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
578 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
579 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
580 IOC4_OTHER_IR_S3_MEMERR,
581 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
582 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
583 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
584 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
585 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
586 }
587 };
589 /* A ring buffer entry */
590 struct ring_entry {
591 union {
592 struct {
593 uint32_t alldata;
594 uint32_t allsc;
595 } all;
596 struct {
597 char data[4]; /* data bytes */
598 char sc[4]; /* status/control */
599 } s;
600 } u;
601 };
603 /* Test the valid bits in any of the 4 sc chars using "allsc" member */
604 #define RING_ANY_VALID \
605 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
607 #define ring_sc u.s.sc
608 #define ring_data u.s.data
609 #define ring_allsc u.all.allsc
611 /* Number of entries per ring buffer. */
612 #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
614 /* An individual ring */
615 struct ring {
616 struct ring_entry entries[ENTRIES_PER_RING];
617 };
619 /* The whole enchilada */
620 struct ring_buffer {
621 struct ring TX_0_OR_2;
622 struct ring RX_0_OR_2;
623 struct ring TX_1_OR_3;
624 struct ring RX_1_OR_3;
625 };
627 /* Get a ring from a port struct */
628 #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
630 /* Infinite loop detection.
631 */
632 #define MAXITER 10000000
634 /* Prototypes */
635 static void receive_chars(struct uart_port *);
636 static void handle_intr(void *arg, uint32_t sio_ir);
638 /*
639 * port_is_active - determines if this port is currently active
640 * @port: ptr to soft struct for this port
641 * @uart_port: uart port to test for
642 */
643 static inline int port_is_active(struct ioc4_port *port,
644 struct uart_port *uart_port)
645 {
646 if (port) {
647 if ((port->ip_flags & PORT_ACTIVE)
648 && (port->ip_port == uart_port))
649 return 1;
650 }
651 return 0;
652 }
655 /**
656 * write_ireg - write the interrupt regs
657 * @ioc4_soft: ptr to soft struct for this port
658 * @val: value to write
659 * @which: which register
660 * @type: which ireg set
661 */
662 static inline void
663 write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
664 {
665 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
666 unsigned long flags;
668 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
670 switch (type) {
671 case IOC4_SIO_INTR_TYPE:
672 switch (which) {
673 case IOC4_W_IES:
674 writel(val, &mem->sio_ies.raw);
675 break;
677 case IOC4_W_IEC:
678 writel(val, &mem->sio_iec.raw);
679 break;
680 }
681 break;
683 case IOC4_OTHER_INTR_TYPE:
684 switch (which) {
685 case IOC4_W_IES:
686 writel(val, &mem->other_ies.raw);
687 break;
689 case IOC4_W_IEC:
690 writel(val, &mem->other_iec.raw);
691 break;
692 }
693 break;
695 default:
696 break;
697 }
698 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
699 }
701 /**
702 * set_baud - Baud rate setting code
703 * @port: port to set
704 * @baud: baud rate to use
705 */
706 static int set_baud(struct ioc4_port *port, int baud)
707 {
708 int actual_baud;
709 int diff;
710 int lcr;
711 unsigned short divisor;
712 struct ioc4_uartregs __iomem *uart;
714 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
715 if (!divisor)
716 return 1;
717 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
719 diff = actual_baud - baud;
720 if (diff < 0)
721 diff = -diff;
723 /* If we're within 1%, we've found a match */
724 if (diff * 100 > actual_baud)
725 return 1;
727 uart = port->ip_uart_regs;
728 lcr = readb(&uart->i4u_lcr);
729 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
730 writeb((unsigned char)divisor, &uart->i4u_dll);
731 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
732 writeb(lcr, &uart->i4u_lcr);
733 return 0;
734 }
737 /**
738 * get_ioc4_port - given a uart port, return the control structure
739 * @port: uart port
740 * @set: set this port as current
741 */
742 static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
743 {
744 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
745 struct ioc4_control *control = idd->idd_serial_data;
746 struct ioc4_port *port;
747 int port_num, port_type;
749 if (control) {
750 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
751 port_num++ ) {
752 port = control->ic_port[port_num].icp_port;
753 if (!port)
754 continue;
755 for (port_type = UART_PORT_MIN;
756 port_type < UART_PORT_COUNT;
757 port_type++) {
758 if (the_port == port->ip_all_ports
759 [port_type]) {
760 /* set local copy */
761 if (set) {
762 port->ip_port = the_port;
763 }
764 return port;
765 }
766 }
767 }
768 }
769 return NULL;
770 }
772 /* The IOC4 hardware provides no atomic way to determine if interrupts
773 * are pending since two reads are required to do so. The handler must
774 * read the SIO_IR and the SIO_IES, and take the logical and of the
775 * two. When this value is zero, all interrupts have been serviced and
776 * the handler may return.
777 *
778 * This has the unfortunate "hole" that, if some other CPU or
779 * some other thread or some higher level interrupt manages to
780 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
781 * think we have observed SIO_IR&SIO_IE==0 when in fact this
782 * condition never really occurred.
783 *
784 * To solve this, we use a simple spinlock that must be held
785 * whenever modifying SIO_IE; holding this lock while observing
786 * both SIO_IR and SIO_IE guarantees that we do not falsely
787 * conclude that no enabled interrupts are pending.
788 */
790 static inline uint32_t
791 pending_intrs(struct ioc4_soft *soft, int type)
792 {
793 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
794 unsigned long flag;
795 uint32_t intrs = 0;
797 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
798 || (type == IOC4_OTHER_INTR_TYPE)));
800 spin_lock_irqsave(&soft->is_ir_lock, flag);
802 switch (type) {
803 case IOC4_SIO_INTR_TYPE:
804 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
805 break;
807 case IOC4_OTHER_INTR_TYPE:
808 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
810 /* Don't process any ATA interrupte */
811 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
812 break;
814 default:
815 break;
816 }
817 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
818 return intrs;
819 }
821 /**
822 * port_init - Initialize the sio and ioc4 hardware for a given port
823 * called per port from attach...
824 * @port: port to initialize
825 */
826 static int inline port_init(struct ioc4_port *port)
827 {
828 uint32_t sio_cr;
829 struct hooks *hooks = port->ip_hooks;
830 struct ioc4_uartregs __iomem *uart;
832 /* Idle the IOC4 serial interface */
833 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
835 /* Wait until any pending bus activity for this port has ceased */
836 do
837 sio_cr = readl(&port->ip_mem->sio_cr.raw);
838 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
840 /* Finish reset sequence */
841 writel(0, &port->ip_serial_regs->sscr);
843 /* Once RESET is done, reload cached tx_prod and rx_cons values
844 * and set rings to empty by making prod == cons
845 */
846 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
847 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
848 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
849 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
851 /* Disable interrupts for this 16550 */
852 uart = port->ip_uart_regs;
853 writeb(0, &uart->i4u_lcr);
854 writeb(0, &uart->i4u_ier);
856 /* Set the default baud */
857 set_baud(port, port->ip_baud);
859 /* Set line control to 8 bits no parity */
860 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
861 /* UART_LCR_STOP == 1 stop */
863 /* Enable the FIFOs */
864 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
865 /* then reset 16550 FIFOs */
866 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
867 &uart->i4u_fcr);
869 /* Clear modem control register */
870 writeb(0, &uart->i4u_mcr);
872 /* Clear deltas in modem status register */
873 readb(&uart->i4u_msr);
875 /* Only do this once per port pair */
876 if (port->ip_hooks == &hooks_array[0]
877 || port->ip_hooks == &hooks_array[2]) {
878 unsigned long ring_pci_addr;
879 uint32_t __iomem *sbbr_l;
880 uint32_t __iomem *sbbr_h;
882 if (port->ip_hooks == &hooks_array[0]) {
883 sbbr_l = &port->ip_serial->sbbr01_l;
884 sbbr_h = &port->ip_serial->sbbr01_h;
885 } else {
886 sbbr_l = &port->ip_serial->sbbr23_l;
887 sbbr_h = &port->ip_serial->sbbr23_h;
888 }
890 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
891 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
892 __FUNCTION__, ring_pci_addr));
894 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
895 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
896 }
898 /* Set the receive timeout value to 10 msec */
899 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
901 /* Set rx threshold, enable DMA */
902 /* Set high water mark at 3/4 of full ring */
903 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
904 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
906 /* Disable and clear all serial related interrupt bits */
907 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
908 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
909 port->ip_ienb &= ~hooks->intr_clear;
910 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
911 return 0;
912 }
914 /**
915 * handle_dma_error_intr - service any pending DMA error interrupts for the
916 * given port - 2nd level called via sd_intr
917 * @arg: handler arg
918 * @other_ir: ioc4regs
919 */
920 static void handle_dma_error_intr(void *arg, uint32_t other_ir)
921 {
922 struct ioc4_port *port = (struct ioc4_port *)arg;
923 struct hooks *hooks = port->ip_hooks;
924 unsigned int flags;
926 spin_lock_irqsave(&port->ip_lock, flags);
928 /* ACK the interrupt */
929 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
931 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
932 printk(KERN_ERR
933 "PCI error address is 0x%lx, "
934 "master is serial port %c %s\n",
935 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
936 << 32)
937 | readl(&port->ip_mem->pci_err_addr_l.raw))
938 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
939 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
940 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
941 (readl(&port->ip_mem->pci_err_addr_l.raw)
942 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
943 ? "RX" : "TX");
945 if (readl(&port->ip_mem->pci_err_addr_l.raw)
946 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
947 printk(KERN_ERR
948 "Multiple errors occurred\n");
949 }
950 }
951 spin_unlock_irqrestore(&port->ip_lock, flags);
953 /* Re-enable DMA error interrupts */
954 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
955 IOC4_OTHER_INTR_TYPE);
956 }
958 /**
959 * intr_connect - interrupt connect function
960 * @soft: soft struct for this card
961 * @type: interrupt type
962 * @intrbits: bit pattern to set
963 * @intr: handler function
964 * @info: handler arg
965 */
966 static void
967 intr_connect(struct ioc4_soft *soft, int type,
968 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
969 {
970 int i;
971 struct ioc4_intr_info *intr_ptr;
973 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
974 || (type == IOC4_OTHER_INTR_TYPE)));
976 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
977 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
979 /* Save off the lower level interrupt handler */
980 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
981 intr_ptr->sd_bits = intrbits;
982 intr_ptr->sd_intr = intr;
983 intr_ptr->sd_info = info;
984 }
986 /**
987 * ioc4_intr - Top level IOC4 interrupt handler.
988 * @irq: irq value
989 * @arg: handler arg
990 * @regs: registers
991 */
993 static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
994 {
995 struct ioc4_soft *soft;
996 uint32_t this_ir, this_mir;
997 int xx, num_intrs = 0;
998 int intr_type;
999 int handled = 0;
1000 struct ioc4_intr_info *intr_info;
1002 soft = arg;
1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1004 num_intrs = (int)atomic_read(
1005 &soft->is_intr_type[intr_type].is_num_intrs);
1007 this_mir = this_ir = pending_intrs(soft, intr_type);
1009 /* Farm out the interrupt to the various drivers depending on
1010 * which interrupt bits are set.
1011 */
1012 for (xx = 0; xx < num_intrs; xx++) {
1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1014 if ((this_mir = this_ir & intr_info->sd_bits)) {
1015 /* Disable owned interrupts, call handler */
1016 handled++;
1017 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1018 intr_type);
1019 intr_info->sd_intr(intr_info->sd_info, this_mir);
1020 this_ir &= ~this_mir;
1024 #ifdef DEBUG_INTERRUPTS
1026 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1027 unsigned long flag;
1029 spin_lock_irqsave(&soft->is_ir_lock, flag);
1030 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1031 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1032 __FUNCTION__, __LINE__,
1033 (void *)mem, readl(&mem->sio_ir.raw),
1034 readl(&mem->sio_ies.raw),
1035 readl(&mem->other_ir.raw),
1036 readl(&mem->other_ies.raw),
1037 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1038 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1040 #endif
1041 return handled ? IRQ_HANDLED : IRQ_NONE;
1044 /**
1045 * ioc4_attach_local - Device initialization.
1046 * Called at *_attach() time for each
1047 * IOC4 with serial ports in the system.
1048 * @idd: Master module data for this IOC4
1049 */
1050 static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1052 struct ioc4_port *port;
1053 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1054 int port_number;
1055 uint16_t ioc4_revid_min = 62;
1056 uint16_t ioc4_revid;
1057 struct pci_dev *pdev = idd->idd_pdev;
1058 struct ioc4_control* control = idd->idd_serial_data;
1059 struct ioc4_soft *soft = control->ic_soft;
1060 void __iomem *ioc4_misc = idd->idd_misc_regs;
1061 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1063 /* IOC4 firmware must be at least rev 62 */
1064 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1066 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1067 if (ioc4_revid < ioc4_revid_min) {
1068 printk(KERN_WARNING
1069 "IOC4 serial not supported on firmware rev %d, "
1070 "please upgrade to rev %d or higher\n",
1071 ioc4_revid, ioc4_revid_min);
1072 return -EPERM;
1074 BUG_ON(ioc4_misc == NULL);
1075 BUG_ON(ioc4_serial == NULL);
1077 /* Create port structures for each port */
1078 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1079 port_number++) {
1080 port = kmalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1081 if (!port) {
1082 printk(KERN_WARNING
1083 "IOC4 serial memory not available for port\n");
1084 return -ENOMEM;
1086 memset(port, 0, sizeof(struct ioc4_port));
1087 spin_lock_init(&port->ip_lock);
1089 /* we need to remember the previous ones, to point back to
1090 * them farther down - setting up the ring buffers.
1091 */
1092 ports[port_number] = port;
1094 /* Allocate buffers and jumpstart the hardware. */
1095 control->ic_port[port_number].icp_port = port;
1096 port->ip_ioc4_soft = soft;
1097 port->ip_pdev = pdev;
1098 port->ip_ienb = 0;
1099 /* Use baud rate calculations based on detected PCI
1100 * bus speed. Simply test whether the PCI clock is
1101 * running closer to 66MHz or 33MHz.
1102 */
1103 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1104 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1105 } else {
1106 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1108 port->ip_baud = 9600;
1109 port->ip_control = control;
1110 port->ip_mem = ioc4_misc;
1111 port->ip_serial = ioc4_serial;
1113 /* point to the right hook */
1114 port->ip_hooks = &hooks_array[port_number];
1116 /* Get direct hooks to the serial regs and uart regs
1117 * for this port
1118 */
1119 switch (port_number) {
1120 case 0:
1121 port->ip_serial_regs = &(port->ip_serial->port_0);
1122 port->ip_uart_regs = &(port->ip_serial->uart_0);
1123 break;
1124 case 1:
1125 port->ip_serial_regs = &(port->ip_serial->port_1);
1126 port->ip_uart_regs = &(port->ip_serial->uart_1);
1127 break;
1128 case 2:
1129 port->ip_serial_regs = &(port->ip_serial->port_2);
1130 port->ip_uart_regs = &(port->ip_serial->uart_2);
1131 break;
1132 default:
1133 case 3:
1134 port->ip_serial_regs = &(port->ip_serial->port_3);
1135 port->ip_uart_regs = &(port->ip_serial->uart_3);
1136 break;
1139 /* ring buffers are 1 to a pair of ports */
1140 if (port_number && (port_number & 1)) {
1141 /* odd use the evens buffer */
1142 port->ip_dma_ringbuf =
1143 ports[port_number - 1]->ip_dma_ringbuf;
1144 port->ip_cpu_ringbuf =
1145 ports[port_number - 1]->ip_cpu_ringbuf;
1146 port->ip_inring = RING(port, RX_1_OR_3);
1147 port->ip_outring = RING(port, TX_1_OR_3);
1149 } else {
1150 if (port->ip_dma_ringbuf == 0) {
1151 port->ip_cpu_ringbuf = pci_alloc_consistent
1152 (pdev, TOTAL_RING_BUF_SIZE,
1153 &port->ip_dma_ringbuf);
1156 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1157 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1158 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1159 "ip_dma_ringbuf 0x%p\n",
1160 __FUNCTION__,
1161 (void *)port->ip_cpu_ringbuf,
1162 (void *)port->ip_dma_ringbuf));
1163 port->ip_inring = RING(port, RX_0_OR_2);
1164 port->ip_outring = RING(port, TX_0_OR_2);
1166 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1167 __FUNCTION__,
1168 port_number, (void *)port, (void *)control));
1169 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1170 (void *)port->ip_serial_regs,
1171 (void *)port->ip_uart_regs));
1173 /* Initialize the hardware for IOC4 */
1174 port_init(port);
1176 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1177 "outring 0x%p\n",
1178 __FUNCTION__,
1179 port_number, (void *)port,
1180 (void *)port->ip_inring,
1181 (void *)port->ip_outring));
1183 /* Attach interrupt handlers */
1184 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1185 GET_SIO_IR(port_number),
1186 handle_intr, port);
1188 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1189 GET_OTHER_IR(port_number),
1190 handle_dma_error_intr, port);
1192 return 0;
1195 /**
1196 * enable_intrs - enable interrupts
1197 * @port: port to enable
1198 * @mask: mask to use
1199 */
1200 static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1202 struct hooks *hooks = port->ip_hooks;
1204 if ((port->ip_ienb & mask) != mask) {
1205 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1206 IOC4_SIO_INTR_TYPE);
1207 port->ip_ienb |= mask;
1210 if (port->ip_ienb)
1211 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1212 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1215 /**
1216 * local_open - local open a port
1217 * @port: port to open
1218 */
1219 static inline int local_open(struct ioc4_port *port)
1221 int spiniter = 0;
1223 port->ip_flags = PORT_ACTIVE;
1225 /* Pause the DMA interface if necessary */
1226 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1227 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1228 &port->ip_serial_regs->sscr);
1229 while((readl(&port->ip_serial_regs-> sscr)
1230 & IOC4_SSCR_PAUSE_STATE) == 0) {
1231 spiniter++;
1232 if (spiniter > MAXITER) {
1233 port->ip_flags = PORT_INACTIVE;
1234 return -1;
1239 /* Reset the input fifo. If the uart received chars while the port
1240 * was closed and DMA is not enabled, the uart may have a bunch of
1241 * chars hanging around in its rx fifo which will not be discarded
1242 * by rclr in the upper layer. We must get rid of them here.
1243 */
1244 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1245 &port->ip_uart_regs->i4u_fcr);
1247 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1248 /* UART_LCR_STOP == 1 stop */
1250 /* Re-enable DMA, set default threshold to intr whenever there is
1251 * data available.
1252 */
1253 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1254 port->ip_sscr |= 1; /* default threshold */
1256 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1257 * flag if it was set above
1258 */
1259 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1260 port->ip_tx_lowat = 1;
1261 return 0;
1264 /**
1265 * set_rx_timeout - Set rx timeout and threshold values.
1266 * @port: port to use
1267 * @timeout: timeout value in ticks
1268 */
1269 static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1271 int threshold;
1273 port->ip_rx_timeout = timeout;
1275 /* Timeout is in ticks. Let's figure out how many chars we
1276 * can receive at the current baud rate in that interval
1277 * and set the rx threshold to that amount. There are 4 chars
1278 * per ring entry, so we'll divide the number of chars that will
1279 * arrive in timeout by 4.
1280 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1281 */
1282 threshold = timeout * port->ip_baud / 4000;
1283 if (threshold == 0)
1284 threshold = 1; /* otherwise we'll intr all the time! */
1286 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1287 return 1;
1289 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1290 port->ip_sscr |= threshold;
1292 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1294 /* Now set the rx timeout to the given value
1295 * again timeout * IOC4_SRTR_HZ / HZ
1296 */
1297 timeout = timeout * IOC4_SRTR_HZ / 100;
1298 if (timeout > IOC4_SRTR_CNT)
1299 timeout = IOC4_SRTR_CNT;
1301 writel(timeout, &port->ip_serial_regs->srtr);
1302 return 0;
1305 /**
1306 * config_port - config the hardware
1307 * @port: port to config
1308 * @baud: baud rate for the port
1309 * @byte_size: data size
1310 * @stop_bits: number of stop bits
1311 * @parenb: parity enable ?
1312 * @parodd: odd parity ?
1313 */
1314 static inline int
1315 config_port(struct ioc4_port *port,
1316 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1318 char lcr, sizebits;
1319 int spiniter = 0;
1321 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1322 __FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));
1324 if (set_baud(port, baud))
1325 return 1;
1327 switch (byte_size) {
1328 case 5:
1329 sizebits = UART_LCR_WLEN5;
1330 break;
1331 case 6:
1332 sizebits = UART_LCR_WLEN6;
1333 break;
1334 case 7:
1335 sizebits = UART_LCR_WLEN7;
1336 break;
1337 case 8:
1338 sizebits = UART_LCR_WLEN8;
1339 break;
1340 default:
1341 return 1;
1344 /* Pause the DMA interface if necessary */
1345 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1346 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1347 &port->ip_serial_regs->sscr);
1348 while((readl(&port->ip_serial_regs->sscr)
1349 & IOC4_SSCR_PAUSE_STATE) == 0) {
1350 spiniter++;
1351 if (spiniter > MAXITER)
1352 return -1;
1356 /* Clear relevant fields in lcr */
1357 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1358 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1359 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1361 /* Set byte size in lcr */
1362 lcr |= sizebits;
1364 /* Set parity */
1365 if (parenb) {
1366 lcr |= UART_LCR_PARITY;
1367 if (!parodd)
1368 lcr |= UART_LCR_EPAR;
1371 /* Set stop bits */
1372 if (stop_bits)
1373 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1375 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1377 /* Re-enable the DMA interface if necessary */
1378 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1379 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1381 port->ip_baud = baud;
1383 /* When we get within this number of ring entries of filling the
1384 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1385 * notification when output has drained.
1386 */
1387 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1388 if (port->ip_tx_lowat == 0)
1389 port->ip_tx_lowat = 1;
1391 set_rx_timeout(port, 2);
1393 return 0;
1396 /**
1397 * do_write - Write bytes to the port. Returns the number of bytes
1398 * actually written. Called from transmit_chars
1399 * @port: port to use
1400 * @buf: the stuff to write
1401 * @len: how many bytes in 'buf'
1402 */
1403 static inline int do_write(struct ioc4_port *port, char *buf, int len)
1405 int prod_ptr, cons_ptr, total = 0;
1406 struct ring *outring;
1407 struct ring_entry *entry;
1408 struct hooks *hooks = port->ip_hooks;
1410 BUG_ON(!(len >= 0));
1412 prod_ptr = port->ip_tx_prod;
1413 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1414 outring = port->ip_outring;
1416 /* Maintain a 1-entry red-zone. The ring buffer is full when
1417 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1418 * in the body of the loop, I'll do it now.
1419 */
1420 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1422 /* Stuff the bytes into the output */
1423 while ((prod_ptr != cons_ptr) && (len > 0)) {
1424 int xx;
1426 /* Get 4 bytes (one ring entry) at a time */
1427 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1429 /* Invalidate all entries */
1430 entry->ring_allsc = 0;
1432 /* Copy in some bytes */
1433 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1434 entry->ring_data[xx] = *buf++;
1435 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1436 len--;
1437 total++;
1440 /* If we are within some small threshold of filling up the
1441 * entire ring buffer, we must place an EXPLICIT intr here
1442 * to generate a lowat interrupt in case we subsequently
1443 * really do fill up the ring and the caller goes to sleep.
1444 * No need to place more than one though.
1445 */
1446 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1447 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1448 <= port->ip_tx_lowat
1449 * (int)sizeof(struct ring_entry)) {
1450 port->ip_flags |= LOWAT_WRITTEN;
1451 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1454 /* Go on to next entry */
1455 prod_ptr += sizeof(struct ring_entry);
1456 prod_ptr &= PROD_CONS_MASK;
1459 /* If we sent something, start DMA if necessary */
1460 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1461 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1462 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1465 /* Store the new producer pointer. If tx is disabled, we stuff the
1466 * data into the ring buffer, but we don't actually start tx.
1467 */
1468 if (!uart_tx_stopped(port->ip_port)) {
1469 writel(prod_ptr, &port->ip_serial_regs->stpir);
1471 /* If we are now transmitting, enable tx_mt interrupt so we
1472 * can disable DMA if necessary when the tx finishes.
1473 */
1474 if (total > 0)
1475 enable_intrs(port, hooks->intr_tx_mt);
1477 port->ip_tx_prod = prod_ptr;
1478 return total;
1481 /**
1482 * disable_intrs - disable interrupts
1483 * @port: port to enable
1484 * @mask: mask to use
1485 */
1486 static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1488 struct hooks *hooks = port->ip_hooks;
1490 if (port->ip_ienb & mask) {
1491 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1492 IOC4_SIO_INTR_TYPE);
1493 port->ip_ienb &= ~mask;
1496 if (!port->ip_ienb)
1497 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1498 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1501 /**
1502 * set_notification - Modify event notification
1503 * @port: port to use
1504 * @mask: events mask
1505 * @set_on: set ?
1506 */
1507 static int set_notification(struct ioc4_port *port, int mask, int set_on)
1509 struct hooks *hooks = port->ip_hooks;
1510 uint32_t intrbits, sscrbits;
1512 BUG_ON(!mask);
1514 intrbits = sscrbits = 0;
1516 if (mask & N_DATA_READY)
1517 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1518 if (mask & N_OUTPUT_LOWAT)
1519 intrbits |= hooks->intr_tx_explicit;
1520 if (mask & N_DDCD) {
1521 intrbits |= hooks->intr_delta_dcd;
1522 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1524 if (mask & N_DCTS)
1525 intrbits |= hooks->intr_delta_cts;
1527 if (set_on) {
1528 enable_intrs(port, intrbits);
1529 port->ip_notify |= mask;
1530 port->ip_sscr |= sscrbits;
1531 } else {
1532 disable_intrs(port, intrbits);
1533 port->ip_notify &= ~mask;
1534 port->ip_sscr &= ~sscrbits;
1537 /* We require DMA if either DATA_READY or DDCD notification is
1538 * currently requested. If neither of these is requested and
1539 * there is currently no tx in progress, DMA may be disabled.
1540 */
1541 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1542 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1543 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1544 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1546 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1547 return 0;
1550 /**
1551 * set_mcr - set the master control reg
1552 * @the_port: port to use
1553 * @mask1: mcr mask
1554 * @mask2: shadow mask
1555 */
1556 static inline int set_mcr(struct uart_port *the_port,
1557 int mask1, int mask2)
1559 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1560 uint32_t shadow;
1561 int spiniter = 0;
1562 char mcr;
1564 if (!port)
1565 return -1;
1567 /* Pause the DMA interface if necessary */
1568 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1569 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1570 &port->ip_serial_regs->sscr);
1571 while ((readl(&port->ip_serial_regs->sscr)
1572 & IOC4_SSCR_PAUSE_STATE) == 0) {
1573 spiniter++;
1574 if (spiniter > MAXITER)
1575 return -1;
1578 shadow = readl(&port->ip_serial_regs->shadow);
1579 mcr = (shadow & 0xff000000) >> 24;
1581 /* Set new value */
1582 mcr |= mask1;
1583 shadow |= mask2;
1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1586 writel(shadow, &port->ip_serial_regs->shadow);
1588 /* Re-enable the DMA interface if necessary */
1589 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1590 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1592 return 0;
1595 /**
1596 * ioc4_set_proto - set the protocol for the port
1597 * @port: port to use
1598 * @proto: protocol to use
1599 */
1600 static int ioc4_set_proto(struct ioc4_port *port, int proto)
1602 struct hooks *hooks = port->ip_hooks;
1604 switch (proto) {
1605 case PROTO_RS232:
1606 /* Clear the appropriate GIO pin */
1607 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1608 break;
1610 case PROTO_RS422:
1611 /* Set the appropriate GIO pin */
1612 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1613 break;
1615 default:
1616 return 1;
1618 return 0;
1621 /**
1622 * transmit_chars - upper level write, called with ip_lock
1623 * @the_port: port to write
1624 */
1625 static void transmit_chars(struct uart_port *the_port)
1627 int xmit_count, tail, head;
1628 int result;
1629 char *start;
1630 struct tty_struct *tty;
1631 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1632 struct uart_info *info;
1634 if (!the_port)
1635 return;
1636 if (!port)
1637 return;
1639 info = the_port->info;
1640 tty = info->tty;
1642 if (uart_circ_empty(&info->xmit) || uart_tx_stopped(the_port)) {
1643 /* Nothing to do or hw stopped */
1644 set_notification(port, N_ALL_OUTPUT, 0);
1645 return;
1648 head = info->xmit.head;
1649 tail = info->xmit.tail;
1650 start = (char *)&info->xmit.buf[tail];
1652 /* write out all the data or until the end of the buffer */
1653 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1654 if (xmit_count > 0) {
1655 result = do_write(port, start, xmit_count);
1656 if (result > 0) {
1657 /* booking */
1658 xmit_count -= result;
1659 the_port->icount.tx += result;
1660 /* advance the pointers */
1661 tail += result;
1662 tail &= UART_XMIT_SIZE - 1;
1663 info->xmit.tail = tail;
1664 start = (char *)&info->xmit.buf[tail];
1667 if (uart_circ_chars_pending(&info->xmit) < WAKEUP_CHARS)
1668 uart_write_wakeup(the_port);
1670 if (uart_circ_empty(&info->xmit)) {
1671 set_notification(port, N_OUTPUT_LOWAT, 0);
1672 } else {
1673 set_notification(port, N_OUTPUT_LOWAT, 1);
1677 /**
1678 * ioc4_change_speed - change the speed of the port
1679 * @the_port: port to change
1680 * @new_termios: new termios settings
1681 * @old_termios: old termios settings
1682 */
1683 static void
1684 ioc4_change_speed(struct uart_port *the_port,
1685 struct termios *new_termios, struct termios *old_termios)
1687 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1688 int baud, bits;
1689 unsigned cflag;
1690 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1691 struct uart_info *info = the_port->info;
1693 cflag = new_termios->c_cflag;
1695 switch (cflag & CSIZE) {
1696 case CS5:
1697 new_data = 5;
1698 bits = 7;
1699 break;
1700 case CS6:
1701 new_data = 6;
1702 bits = 8;
1703 break;
1704 case CS7:
1705 new_data = 7;
1706 bits = 9;
1707 break;
1708 case CS8:
1709 new_data = 8;
1710 bits = 10;
1711 break;
1712 default:
1713 /* cuz we always need a default ... */
1714 new_data = 5;
1715 bits = 7;
1716 break;
1718 if (cflag & CSTOPB) {
1719 bits++;
1720 new_stop = 1;
1722 if (cflag & PARENB) {
1723 bits++;
1724 new_parity_enable = 1;
1725 if (cflag & PARODD)
1726 new_parity = 1;
1728 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1729 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1730 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__, baud));
1732 /* default is 9600 */
1733 if (!baud)
1734 baud = 9600;
1736 if (!the_port->fifosize)
1737 the_port->fifosize = IOC4_FIFO_CHARS;
1738 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1739 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1741 the_port->ignore_status_mask = N_ALL_INPUT;
1743 info->tty->low_latency = 1;
1745 if (I_IGNPAR(info->tty))
1746 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1747 | N_FRAMING_ERROR);
1748 if (I_IGNBRK(info->tty)) {
1749 the_port->ignore_status_mask &= ~N_BREAK;
1750 if (I_IGNPAR(info->tty))
1751 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1753 if (!(cflag & CREAD)) {
1754 /* ignore everything */
1755 the_port->ignore_status_mask &= ~N_DATA_READY;
1758 if (cflag & CRTSCTS) {
1759 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1761 else {
1762 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1764 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1766 /* Set the configuration and proper notification call */
1767 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1768 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1769 " notification 0x%x\n",
1770 __FUNCTION__, (void *)port, cflag, baud, new_data, new_stop,
1771 new_parity_enable, new_parity, the_port->ignore_status_mask));
1773 if ((config_port(port, baud, /* baud */
1774 new_data, /* byte size */
1775 new_stop, /* stop bits */
1776 new_parity_enable, /* set parity */
1777 new_parity)) >= 0) { /* parity 1==odd */
1778 set_notification(port, the_port->ignore_status_mask, 1);
1782 /**
1783 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1784 * @the_port: Port to operate on
1785 */
1786 static inline int ic4_startup_local(struct uart_port *the_port)
1788 struct ioc4_port *port;
1789 struct uart_info *info;
1791 if (!the_port)
1792 return -1;
1794 port = get_ioc4_port(the_port, 0);
1795 if (!port)
1796 return -1;
1798 info = the_port->info;
1800 local_open(port);
1802 /* set the protocol - mapbase has the port type */
1803 ioc4_set_proto(port, the_port->mapbase);
1805 /* set the speed of the serial port */
1806 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1808 return 0;
1811 /*
1812 * ioc4_cb_output_lowat - called when the output low water mark is hit
1813 * @the_port: port to output
1814 */
1815 static void ioc4_cb_output_lowat(struct uart_port *the_port)
1817 unsigned long pflags;
1819 /* ip_lock is set on the call here */
1820 if (the_port) {
1821 spin_lock_irqsave(&the_port->lock, pflags);
1822 transmit_chars(the_port);
1823 spin_unlock_irqrestore(&the_port->lock, pflags);
1827 /**
1828 * handle_intr - service any interrupts for the given port - 2nd level
1829 * called via sd_intr
1830 * @arg: handler arg
1831 * @sio_ir: ioc4regs
1832 */
1833 static void handle_intr(void *arg, uint32_t sio_ir)
1835 struct ioc4_port *port = (struct ioc4_port *)arg;
1836 struct hooks *hooks = port->ip_hooks;
1837 unsigned int rx_high_rd_aborted = 0;
1838 unsigned int flags;
1839 struct uart_port *the_port;
1840 int loop_counter;
1842 /* Possible race condition here: The tx_mt interrupt bit may be
1843 * cleared without the intervention of the interrupt handler,
1844 * e.g. by a write. If the top level interrupt handler reads a
1845 * tx_mt, then some other processor does a write, starting up
1846 * output, then we come in here, see the tx_mt and stop DMA, the
1847 * output started by the other processor will hang. Thus we can
1848 * only rely on tx_mt being legitimate if it is read while the
1849 * port lock is held. Therefore this bit must be ignored in the
1850 * passed in interrupt mask which was read by the top level
1851 * interrupt handler since the port lock was not held at the time
1852 * it was read. We can only rely on this bit being accurate if it
1853 * is read while the port lock is held. So we'll clear it for now,
1854 * and reload it later once we have the port lock.
1855 */
1856 sio_ir &= ~(hooks->intr_tx_mt);
1858 spin_lock_irqsave(&port->ip_lock, flags);
1860 loop_counter = MAXITER; /* to avoid hangs */
1862 do {
1863 uint32_t shadow;
1865 if ( loop_counter-- <= 0 ) {
1866 printk(KERN_WARNING "IOC4 serial: "
1867 "possible hang condition/"
1868 "port stuck on interrupt.\n");
1869 break;
1872 /* Handle a DCD change */
1873 if (sio_ir & hooks->intr_delta_dcd) {
1874 /* ACK the interrupt */
1875 writel(hooks->intr_delta_dcd,
1876 &port->ip_mem->sio_ir.raw);
1878 shadow = readl(&port->ip_serial_regs->shadow);
1880 if ((port->ip_notify & N_DDCD)
1881 && (shadow & IOC4_SHADOW_DCD)
1882 && (port->ip_port)) {
1883 the_port = port->ip_port;
1884 the_port->icount.dcd = 1;
1885 wake_up_interruptible
1886 (&the_port-> info->delta_msr_wait);
1887 } else if ((port->ip_notify & N_DDCD)
1888 && !(shadow & IOC4_SHADOW_DCD)) {
1889 /* Flag delta DCD/no DCD */
1890 port->ip_flags |= DCD_ON;
1894 /* Handle a CTS change */
1895 if (sio_ir & hooks->intr_delta_cts) {
1896 /* ACK the interrupt */
1897 writel(hooks->intr_delta_cts,
1898 &port->ip_mem->sio_ir.raw);
1900 shadow = readl(&port->ip_serial_regs->shadow);
1902 if ((port->ip_notify & N_DCTS)
1903 && (port->ip_port)) {
1904 the_port = port->ip_port;
1905 the_port->icount.cts =
1906 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1907 wake_up_interruptible
1908 (&the_port->info->delta_msr_wait);
1912 /* rx timeout interrupt. Must be some data available. Put this
1913 * before the check for rx_high since servicing this condition
1914 * may cause that condition to clear.
1915 */
1916 if (sio_ir & hooks->intr_rx_timer) {
1917 /* ACK the interrupt */
1918 writel(hooks->intr_rx_timer,
1919 &port->ip_mem->sio_ir.raw);
1921 if ((port->ip_notify & N_DATA_READY)
1922 && (port->ip_port)) {
1923 /* ip_lock is set on call here */
1924 receive_chars(port->ip_port);
1928 /* rx high interrupt. Must be after rx_timer. */
1929 else if (sio_ir & hooks->intr_rx_high) {
1930 /* Data available, notify upper layer */
1931 if ((port->ip_notify & N_DATA_READY)
1932 && port->ip_port) {
1933 /* ip_lock is set on call here */
1934 receive_chars(port->ip_port);
1937 /* We can't ACK this interrupt. If receive_chars didn't
1938 * cause the condition to clear, we'll have to disable
1939 * the interrupt until the data is drained.
1940 * If the read was aborted, don't disable the interrupt
1941 * as this may cause us to hang indefinitely. An
1942 * aborted read generally means that this interrupt
1943 * hasn't been delivered to the cpu yet anyway, even
1944 * though we see it as asserted when we read the sio_ir.
1945 */
1946 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1947 if ((port->ip_flags & READ_ABORTED) == 0) {
1948 port->ip_ienb &= ~hooks->intr_rx_high;
1949 port->ip_flags |= INPUT_HIGH;
1950 } else {
1951 rx_high_rd_aborted++;
1956 /* We got a low water interrupt: notify upper layer to
1957 * send more data. Must come before tx_mt since servicing
1958 * this condition may cause that condition to clear.
1959 */
1960 if (sio_ir & hooks->intr_tx_explicit) {
1961 port->ip_flags &= ~LOWAT_WRITTEN;
1963 /* ACK the interrupt */
1964 writel(hooks->intr_tx_explicit,
1965 &port->ip_mem->sio_ir.raw);
1967 if (port->ip_notify & N_OUTPUT_LOWAT)
1968 ioc4_cb_output_lowat(port->ip_port);
1971 /* Handle tx_mt. Must come after tx_explicit. */
1972 else if (sio_ir & hooks->intr_tx_mt) {
1973 /* If we are expecting a lowat notification
1974 * and we get to this point it probably means that for
1975 * some reason the tx_explicit didn't work as expected
1976 * (that can legitimately happen if the output buffer is
1977 * filled up in just the right way).
1978 * So send the notification now.
1979 */
1980 if (port->ip_notify & N_OUTPUT_LOWAT) {
1981 ioc4_cb_output_lowat(port->ip_port);
1983 /* We need to reload the sio_ir since the lowat
1984 * call may have caused another write to occur,
1985 * clearing the tx_mt condition.
1986 */
1987 sio_ir = PENDING(port);
1990 /* If the tx_mt condition still persists even after the
1991 * lowat call, we've got some work to do.
1992 */
1993 if (sio_ir & hooks->intr_tx_mt) {
1995 /* If we are not currently expecting DMA input,
1996 * and the transmitter has just gone idle,
1997 * there is no longer any reason for DMA, so
1998 * disable it.
1999 */
2000 if (!(port->ip_notify
2001 & (N_DATA_READY | N_DDCD))) {
2002 BUG_ON(!(port->ip_sscr
2003 & IOC4_SSCR_DMA_EN));
2004 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2005 writel(port->ip_sscr,
2006 &port->ip_serial_regs->sscr);
2009 /* Prevent infinite tx_mt interrupt */
2010 port->ip_ienb &= ~hooks->intr_tx_mt;
2013 sio_ir = PENDING(port);
2015 /* if the read was aborted and only hooks->intr_rx_high,
2016 * clear hooks->intr_rx_high, so we do not loop forever.
2017 */
2019 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2020 sio_ir &= ~hooks->intr_rx_high;
2022 } while (sio_ir & hooks->intr_all);
2024 spin_unlock_irqrestore(&port->ip_lock, flags);
2026 /* Re-enable interrupts before returning from interrupt handler.
2027 * Getting interrupted here is okay. It'll just v() our semaphore, and
2028 * we'll come through the loop again.
2029 */
2031 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2032 IOC4_SIO_INTR_TYPE);
2035 /*
2036 * ioc4_cb_post_ncs - called for some basic errors
2037 * @port: port to use
2038 * @ncs: event
2039 */
2040 static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2042 struct uart_icount *icount;
2044 icount = &the_port->icount;
2046 if (ncs & NCS_BREAK)
2047 icount->brk++;
2048 if (ncs & NCS_FRAMING)
2049 icount->frame++;
2050 if (ncs & NCS_OVERRUN)
2051 icount->overrun++;
2052 if (ncs & NCS_PARITY)
2053 icount->parity++;
2056 /**
2057 * do_read - Read in bytes from the port. Return the number of bytes
2058 * actually read.
2059 * @the_port: port to use
2060 * @buf: place to put the stuff we read
2061 * @len: how big 'buf' is
2062 */
2064 static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2065 int len)
2067 int prod_ptr, cons_ptr, total;
2068 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2069 struct ring *inring;
2070 struct ring_entry *entry;
2071 struct hooks *hooks = port->ip_hooks;
2072 int byte_num;
2073 char *sc;
2074 int loop_counter;
2076 BUG_ON(!(len >= 0));
2077 BUG_ON(!port);
2079 /* There is a nasty timing issue in the IOC4. When the rx_timer
2080 * expires or the rx_high condition arises, we take an interrupt.
2081 * At some point while servicing the interrupt, we read bytes from
2082 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2083 * not started until the first byte is received *after* it is armed,
2084 * and any bytes pending in the rx construction buffers are not drained
2085 * to memory until either there are 4 bytes available or the rx_timer
2086 * expires. This leads to a potential situation where data is left
2087 * in the construction buffers forever - 1 to 3 bytes were received
2088 * after the interrupt was generated but before the rx_timer was
2089 * re-armed. At that point as long as no subsequent bytes are received
2090 * the timer will never be started and the bytes will remain in the
2091 * construction buffer forever. The solution is to execute a DRAIN
2092 * command after rearming the timer. This way any bytes received before
2093 * the DRAIN will be drained to memory, and any bytes received after
2094 * the DRAIN will start the TIMER and be drained when it expires.
2095 * Luckily, this only needs to be done when the DMA buffer is empty
2096 * since there is no requirement that this function return all
2097 * available data as long as it returns some.
2098 */
2099 /* Re-arm the timer */
2100 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2102 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2103 cons_ptr = port->ip_rx_cons;
2105 if (prod_ptr == cons_ptr) {
2106 int reset_dma = 0;
2108 /* Input buffer appears empty, do a flush. */
2110 /* DMA must be enabled for this to work. */
2111 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2112 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2113 reset_dma = 1;
2116 /* Potential race condition: we must reload the srpir after
2117 * issuing the drain command, otherwise we could think the rx
2118 * buffer is empty, then take a very long interrupt, and when
2119 * we come back it's full and we wait forever for the drain to
2120 * complete.
2121 */
2122 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2123 &port->ip_serial_regs->sscr);
2124 prod_ptr = readl(&port->ip_serial_regs->srpir)
2125 & PROD_CONS_MASK;
2127 /* We must not wait for the DRAIN to complete unless there are
2128 * at least 8 bytes (2 ring entries) available to receive the
2129 * data otherwise the DRAIN will never complete and we'll
2130 * deadlock here.
2131 * In fact, to make things easier, I'll just ignore the flush if
2132 * there is any data at all now available.
2133 */
2134 if (prod_ptr == cons_ptr) {
2135 loop_counter = 0;
2136 while (readl(&port->ip_serial_regs->sscr) &
2137 IOC4_SSCR_RX_DRAIN) {
2138 loop_counter++;
2139 if (loop_counter > MAXITER)
2140 return -1;
2143 /* SIGH. We have to reload the prod_ptr *again* since
2144 * the drain may have caused it to change
2145 */
2146 prod_ptr = readl(&port->ip_serial_regs->srpir)
2147 & PROD_CONS_MASK;
2149 if (reset_dma) {
2150 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2151 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2154 inring = port->ip_inring;
2155 port->ip_flags &= ~READ_ABORTED;
2157 total = 0;
2158 loop_counter = 0xfffff; /* to avoid hangs */
2160 /* Grab bytes from the hardware */
2161 while ((prod_ptr != cons_ptr) && (len > 0)) {
2162 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2164 if ( loop_counter-- <= 0 ) {
2165 printk(KERN_WARNING "IOC4 serial: "
2166 "possible hang condition/"
2167 "port stuck on read.\n");
2168 break;
2171 /* According to the producer pointer, this ring entry
2172 * must contain some data. But if the PIO happened faster
2173 * than the DMA, the data may not be available yet, so let's
2174 * wait until it arrives.
2175 */
2176 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2177 /* Indicate the read is aborted so we don't disable
2178 * the interrupt thinking that the consumer is
2179 * congested.
2180 */
2181 port->ip_flags |= READ_ABORTED;
2182 len = 0;
2183 break;
2186 /* Load the bytes/status out of the ring entry */
2187 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2188 sc = &(entry->ring_sc[byte_num]);
2190 /* Check for change in modem state or overrun */
2191 if ((*sc & IOC4_RXSB_MODEM_VALID)
2192 && (port->ip_notify & N_DDCD)) {
2193 /* Notify upper layer if DCD dropped */
2195 if ((port->ip_flags & DCD_ON)
2196 && !(*sc & IOC4_RXSB_DCD)) {
2198 /* If we have already copied some data,
2199 * return it. We'll pick up the carrier
2200 * drop on the next pass. That way we
2201 * don't throw away the data that has
2202 * already been copied back to
2203 * the caller's buffer.
2204 */
2205 if (total > 0) {
2206 len = 0;
2207 break;
2209 port->ip_flags &= ~DCD_ON;
2211 /* Turn off this notification so the
2212 * carrier drop protocol won't see it
2213 * again when it does a read.
2214 */
2215 *sc &= ~IOC4_RXSB_MODEM_VALID;
2217 /* To keep things consistent, we need
2218 * to update the consumer pointer so
2219 * the next reader won't come in and
2220 * try to read the same ring entries
2221 * again. This must be done here before
2222 * the dcd change.
2223 */
2225 if ((entry->ring_allsc & RING_ANY_VALID)
2226 == 0) {
2227 cons_ptr += (int)sizeof
2228 (struct ring_entry);
2229 cons_ptr &= PROD_CONS_MASK;
2231 writel(cons_ptr,
2232 &port->ip_serial_regs->srcir);
2233 port->ip_rx_cons = cons_ptr;
2235 /* Notify upper layer of carrier drop */
2236 if ((port->ip_notify & N_DDCD)
2237 && port->ip_port) {
2238 the_port->icount.dcd = 0;
2239 wake_up_interruptible
2240 (&the_port->info->
2241 delta_msr_wait);
2244 /* If we had any data to return, we
2245 * would have returned it above.
2246 */
2247 return 0;
2250 if (*sc & IOC4_RXSB_MODEM_VALID) {
2251 /* Notify that an input overrun occurred */
2252 if ((*sc & IOC4_RXSB_OVERRUN)
2253 && (port->ip_notify & N_OVERRUN_ERROR)) {
2254 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2256 /* Don't look at this byte again */
2257 *sc &= ~IOC4_RXSB_MODEM_VALID;
2260 /* Check for valid data or RX errors */
2261 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2262 ((*sc & (IOC4_RXSB_PAR_ERR
2263 | IOC4_RXSB_FRAME_ERR
2264 | IOC4_RXSB_BREAK))
2265 && (port->ip_notify & (N_PARITY_ERROR
2266 | N_FRAMING_ERROR
2267 | N_BREAK)))) {
2268 /* There is an error condition on the next byte.
2269 * If we have already transferred some bytes,
2270 * we'll stop here. Otherwise if this is the
2271 * first byte to be read, we'll just transfer
2272 * it alone after notifying the
2273 * upper layer of its status.
2274 */
2275 if (total > 0) {
2276 len = 0;
2277 break;
2278 } else {
2279 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2280 (port->ip_notify & N_PARITY_ERROR)) {
2281 ioc4_cb_post_ncs(the_port,
2282 NCS_PARITY);
2284 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2285 (port->ip_notify & N_FRAMING_ERROR)){
2286 ioc4_cb_post_ncs(the_port,
2287 NCS_FRAMING);
2289 if ((*sc & IOC4_RXSB_BREAK)
2290 && (port->ip_notify & N_BREAK)) {
2291 ioc4_cb_post_ncs
2292 (the_port,
2293 NCS_BREAK);
2295 len = 1;
2298 if (*sc & IOC4_RXSB_DATA_VALID) {
2299 *sc &= ~IOC4_RXSB_DATA_VALID;
2300 *buf = entry->ring_data[byte_num];
2301 buf++;
2302 len--;
2303 total++;
2307 /* If we used up this entry entirely, go on to the next one,
2308 * otherwise we must have run out of buffer space, so
2309 * leave the consumer pointer here for the next read in case
2310 * there are still unread bytes in this entry.
2311 */
2312 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2313 cons_ptr += (int)sizeof(struct ring_entry);
2314 cons_ptr &= PROD_CONS_MASK;
2318 /* Update consumer pointer and re-arm rx timer interrupt */
2319 writel(cons_ptr, &port->ip_serial_regs->srcir);
2320 port->ip_rx_cons = cons_ptr;
2322 /* If we have now dipped below the rx high water mark and we have
2323 * rx_high interrupt turned off, we can now turn it back on again.
2324 */
2325 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2326 & PROD_CONS_MASK) < ((port->ip_sscr &
2327 IOC4_SSCR_RX_THRESHOLD)
2328 << IOC4_PROD_CONS_PTR_OFF))) {
2329 port->ip_flags &= ~INPUT_HIGH;
2330 enable_intrs(port, hooks->intr_rx_high);
2332 return total;
2335 /**
2336 * receive_chars - upper level read. Called with ip_lock.
2337 * @the_port: port to read from
2338 */
2339 static void receive_chars(struct uart_port *the_port)
2341 struct tty_struct *tty;
2342 unsigned char ch[IOC4_MAX_CHARS];
2343 int read_count, request_count = IOC4_MAX_CHARS;
2344 struct uart_icount *icount;
2345 struct uart_info *info = the_port->info;
2346 unsigned long pflags;
2348 /* Make sure all the pointers are "good" ones */
2349 if (!info)
2350 return;
2351 if (!info->tty)
2352 return;
2354 spin_lock_irqsave(&the_port->lock, pflags);
2355 tty = info->tty;
2357 request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS);
2359 if (request_count > 0) {
2360 icount = &the_port->icount;
2361 read_count = do_read(the_port, ch, request_count);
2362 if (read_count > 0) {
2363 tty_insert_flip_string(tty, ch, read_count);
2364 icount->rx += read_count;
2368 spin_unlock_irqrestore(&the_port->lock, pflags);
2370 tty_flip_buffer_push(tty);
2373 /**
2374 * ic4_type - What type of console are we?
2375 * @port: Port to operate with (we ignore since we only have one port)
2377 */
2378 static const char *ic4_type(struct uart_port *the_port)
2380 if (the_port->mapbase == PROTO_RS232)
2381 return "SGI IOC4 Serial [rs232]";
2382 else
2383 return "SGI IOC4 Serial [rs422]";
2386 /**
2387 * ic4_tx_empty - Is the transmitter empty?
2388 * @port: Port to operate on
2390 */
2391 static unsigned int ic4_tx_empty(struct uart_port *the_port)
2393 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2394 unsigned int ret = 0;
2396 if (port_is_active(port, the_port)) {
2397 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2398 ret = TIOCSER_TEMT;
2400 return ret;
2403 /**
2404 * ic4_stop_tx - stop the transmitter
2405 * @port: Port to operate on
2407 */
2408 static void ic4_stop_tx(struct uart_port *the_port)
2410 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2412 if (port_is_active(port, the_port))
2413 set_notification(port, N_OUTPUT_LOWAT, 0);
2416 /**
2417 * null_void_function -
2418 * @port: Port to operate on
2420 */
2421 static void null_void_function(struct uart_port *the_port)
2425 /**
2426 * ic4_shutdown - shut down the port - free irq and disable
2427 * @port: Port to shut down
2429 */
2430 static void ic4_shutdown(struct uart_port *the_port)
2432 unsigned long port_flags;
2433 struct ioc4_port *port;
2434 struct uart_info *info;
2436 port = get_ioc4_port(the_port, 0);
2437 if (!port)
2438 return;
2440 info = the_port->info;
2441 port->ip_port = NULL;
2443 wake_up_interruptible(&info->delta_msr_wait);
2445 if (info->tty)
2446 set_bit(TTY_IO_ERROR, &info->tty->flags);
2448 spin_lock_irqsave(&the_port->lock, port_flags);
2449 set_notification(port, N_ALL, 0);
2450 port->ip_flags = PORT_INACTIVE;
2451 spin_unlock_irqrestore(&the_port->lock, port_flags);
2454 /**
2455 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2456 * @port: Port to operate on
2457 * @mctrl: Lines to set/unset
2459 */
2460 static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2462 unsigned char mcr = 0;
2463 struct ioc4_port *port;
2465 port = get_ioc4_port(the_port, 0);
2466 if (!port_is_active(port, the_port))
2467 return;
2469 if (mctrl & TIOCM_RTS)
2470 mcr |= UART_MCR_RTS;
2471 if (mctrl & TIOCM_DTR)
2472 mcr |= UART_MCR_DTR;
2473 if (mctrl & TIOCM_OUT1)
2474 mcr |= UART_MCR_OUT1;
2475 if (mctrl & TIOCM_OUT2)
2476 mcr |= UART_MCR_OUT2;
2477 if (mctrl & TIOCM_LOOP)
2478 mcr |= UART_MCR_LOOP;
2480 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2483 /**
2484 * ic4_get_mctrl - get control line info
2485 * @port: port to operate on
2487 */
2488 static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2490 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2491 uint32_t shadow;
2492 unsigned int ret = 0;
2494 if (!port_is_active(port, the_port))
2495 return 0;
2497 shadow = readl(&port->ip_serial_regs->shadow);
2498 if (shadow & IOC4_SHADOW_DCD)
2499 ret |= TIOCM_CAR;
2500 if (shadow & IOC4_SHADOW_DR)
2501 ret |= TIOCM_DSR;
2502 if (shadow & IOC4_SHADOW_CTS)
2503 ret |= TIOCM_CTS;
2504 return ret;
2507 /**
2508 * ic4_start_tx - Start transmitter, flush any output
2509 * @port: Port to operate on
2511 */
2512 static void ic4_start_tx(struct uart_port *the_port)
2514 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2516 if (port_is_active(port, the_port)) {
2517 set_notification(port, N_OUTPUT_LOWAT, 1);
2518 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2522 /**
2523 * ic4_break_ctl - handle breaks
2524 * @port: Port to operate on
2525 * @break_state: Break state
2527 */
2528 static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2532 /**
2533 * ic4_startup - Start up the serial port
2534 * @port: Port to operate on
2536 */
2537 static int ic4_startup(struct uart_port *the_port)
2539 int retval;
2540 struct ioc4_port *port;
2541 struct ioc4_control *control;
2542 struct uart_info *info;
2543 unsigned long port_flags;
2545 if (!the_port)
2546 return -ENODEV;
2547 port = get_ioc4_port(the_port, 1);
2548 if (!port)
2549 return -ENODEV;
2550 info = the_port->info;
2552 control = port->ip_control;
2553 if (!control) {
2554 port->ip_port = NULL;
2555 return -ENODEV;
2558 /* Start up the serial port */
2559 spin_lock_irqsave(&the_port->lock, port_flags);
2560 retval = ic4_startup_local(the_port);
2561 spin_unlock_irqrestore(&the_port->lock, port_flags);
2562 return retval;
2565 /**
2566 * ic4_set_termios - set termios stuff
2567 * @port: port to operate on
2568 * @termios: New settings
2569 * @termios: Old
2571 */
2572 static void
2573 ic4_set_termios(struct uart_port *the_port,
2574 struct termios *termios, struct termios *old_termios)
2576 unsigned long port_flags;
2578 spin_lock_irqsave(&the_port->lock, port_flags);
2579 ioc4_change_speed(the_port, termios, old_termios);
2580 spin_unlock_irqrestore(&the_port->lock, port_flags);
2583 /**
2584 * ic4_request_port - allocate resources for port - no op....
2585 * @port: port to operate on
2587 */
2588 static int ic4_request_port(struct uart_port *port)
2590 return 0;
2593 /* Associate the uart functions above - given to serial core */
2595 static struct uart_ops ioc4_ops = {
2596 .tx_empty = ic4_tx_empty,
2597 .set_mctrl = ic4_set_mctrl,
2598 .get_mctrl = ic4_get_mctrl,
2599 .stop_tx = ic4_stop_tx,
2600 .start_tx = ic4_start_tx,
2601 .stop_rx = null_void_function,
2602 .enable_ms = null_void_function,
2603 .break_ctl = ic4_break_ctl,
2604 .startup = ic4_startup,
2605 .shutdown = ic4_shutdown,
2606 .set_termios = ic4_set_termios,
2607 .type = ic4_type,
2608 .release_port = null_void_function,
2609 .request_port = ic4_request_port,
2610 };
2612 /*
2613 * Boot-time initialization code
2614 */
2616 static struct uart_driver ioc4_uart_rs232 = {
2617 .owner = THIS_MODULE,
2618 .driver_name = "ioc4_serial_rs232",
2619 .dev_name = DEVICE_NAME_RS232,
2620 .major = DEVICE_MAJOR,
2621 .minor = DEVICE_MINOR_RS232,
2622 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2623 };
2625 static struct uart_driver ioc4_uart_rs422 = {
2626 .owner = THIS_MODULE,
2627 .driver_name = "ioc4_serial_rs422",
2628 .dev_name = DEVICE_NAME_RS422,
2629 .major = DEVICE_MAJOR,
2630 .minor = DEVICE_MINOR_RS422,
2631 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2632 };
2635 /**
2636 * ioc4_serial_remove_one - detach function
2638 * @idd: IOC4 master module data for this IOC4
2639 */
2641 static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2643 int port_num, port_type;
2644 struct ioc4_control *control;
2645 struct uart_port *the_port;
2646 struct ioc4_port *port;
2647 struct ioc4_soft *soft;
2649 /* If serial driver did not attach, don't try to detach */
2650 control = idd->idd_serial_data;
2651 if (!control)
2652 return 0;
2654 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2655 for (port_type = UART_PORT_MIN;
2656 port_type < UART_PORT_COUNT;
2657 port_type++) {
2658 the_port = &control->ic_port[port_num].icp_uart_port
2659 [port_type];
2660 if (the_port) {
2661 switch (port_type) {
2662 case UART_PORT_RS422:
2663 uart_remove_one_port(&ioc4_uart_rs422,
2664 the_port);
2665 break;
2666 default:
2667 case UART_PORT_RS232:
2668 uart_remove_one_port(&ioc4_uart_rs232,
2669 the_port);
2670 break;
2674 port = control->ic_port[port_num].icp_port;
2675 /* we allocate in pairs */
2676 if (!(port_num & 1) && port) {
2677 pci_free_consistent(port->ip_pdev,
2678 TOTAL_RING_BUF_SIZE,
2679 port->ip_cpu_ringbuf,
2680 port->ip_dma_ringbuf);
2681 kfree(port);
2684 soft = control->ic_soft;
2685 if (soft) {
2686 free_irq(control->ic_irq, soft);
2687 if (soft->is_ioc4_serial_addr) {
2688 release_region((unsigned long)
2689 soft->is_ioc4_serial_addr,
2690 sizeof(struct ioc4_serial));
2692 kfree(soft);
2694 kfree(control);
2695 idd->idd_serial_data = NULL;
2697 return 0;
2701 /**
2702 * ioc4_serial_core_attach_rs232 - register with serial core
2703 * This is done during pci probing
2704 * @pdev: handle for this card
2705 */
2706 static inline int
2707 ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2709 struct ioc4_port *port;
2710 struct uart_port *the_port;
2711 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2712 struct ioc4_control *control = idd->idd_serial_data;
2713 int port_num;
2714 int port_type_idx;
2715 struct uart_driver *u_driver;
2718 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2719 __FUNCTION__, pdev, (void *)control));
2721 if (!control)
2722 return -ENODEV;
2724 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2725 : UART_PORT_RS422;
2727 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2728 : &ioc4_uart_rs422;
2730 /* once around for each port on this card */
2731 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2732 the_port = &control->ic_port[port_num].icp_uart_port
2733 [port_type_idx];
2734 port = control->ic_port[port_num].icp_port;
2735 port->ip_all_ports[port_type_idx] = the_port;
2737 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2738 __FUNCTION__, (void *)the_port,
2739 (void *)port,
2740 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2742 /* membase, iobase and mapbase just need to be non-0 */
2743 the_port->membase = (unsigned char __iomem *)1;
2744 the_port->iobase = (pdev->bus->number << 16) | port_num;
2745 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2746 the_port->mapbase = port_type;
2747 the_port->type = PORT_16550A;
2748 the_port->fifosize = IOC4_FIFO_CHARS;
2749 the_port->ops = &ioc4_ops;
2750 the_port->irq = control->ic_irq;
2751 the_port->dev = &pdev->dev;
2752 spin_lock_init(&the_port->lock);
2753 if (uart_add_one_port(u_driver, the_port) < 0) {
2754 printk(KERN_WARNING
2755 "%s: unable to add port %d bus %d\n",
2756 __FUNCTION__, the_port->line, pdev->bus->number);
2757 } else {
2758 DPRINT_CONFIG(
2759 ("IOC4 serial port %d irq = %d, bus %d\n",
2760 the_port->line, the_port->irq, pdev->bus->number));
2763 return 0;
2766 /**
2767 * ioc4_serial_attach_one - register attach function
2768 * called per card found from IOC4 master module.
2769 * @idd: Master module data for this IOC4
2770 */
2771 int
2772 ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2774 unsigned long tmp_addr1;
2775 struct ioc4_serial __iomem *serial;
2776 struct ioc4_soft *soft;
2777 struct ioc4_control *control;
2778 int ret = 0;
2781 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
2782 idd->idd_pci_id));
2784 /* PCI-RT does not bring out serial connections.
2785 * Do not attach to this particular IOC4.
2786 */
2787 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2788 return 0;
2790 /* request serial registers */
2791 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2793 if (!request_region(tmp_addr1, sizeof(struct ioc4_serial),
2794 "sioc4_uart")) {
2795 printk(KERN_WARNING
2796 "ioc4 (%p): unable to get request region for "
2797 "uart space\n", (void *)idd->idd_pdev);
2798 ret = -ENODEV;
2799 goto out1;
2801 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2802 if (!serial) {
2803 printk(KERN_WARNING
2804 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2805 (void *)idd->idd_pdev);
2806 ret = -ENODEV;
2807 goto out2;
2809 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2810 __FUNCTION__, (void *)idd->idd_misc_regs,
2811 (void *)serial));
2813 /* Get memory for the new card */
2814 control = kmalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2816 if (!control) {
2817 printk(KERN_WARNING "ioc4_attach_one"
2818 ": unable to get memory for the IOC4\n");
2819 ret = -ENOMEM;
2820 goto out2;
2822 memset(control, 0, sizeof(struct ioc4_control));
2823 idd->idd_serial_data = control;
2825 /* Allocate the soft structure */
2826 soft = kmalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2827 if (!soft) {
2828 printk(KERN_WARNING
2829 "ioc4 (%p): unable to get memory for the soft struct\n",
2830 (void *)idd->idd_pdev);
2831 ret = -ENOMEM;
2832 goto out3;
2834 memset(soft, 0, sizeof(struct ioc4_soft));
2836 spin_lock_init(&soft->is_ir_lock);
2837 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2838 soft->is_ioc4_serial_addr = serial;
2840 /* Init the IOC4 */
2841 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2842 &idd->idd_misc_regs->sio_cr.raw);
2844 /* Enable serial port mode select generic PIO pins as outputs */
2845 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2846 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2847 &idd->idd_misc_regs->gpcr_s.raw);
2849 /* Clear and disable all serial interrupts */
2850 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2851 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2852 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2853 IOC4_OTHER_INTR_TYPE);
2854 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2855 control->ic_soft = soft;
2857 /* Hook up interrupt handler */
2858 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2859 "sgi-ioc4serial", soft)) {
2860 control->ic_irq = idd->idd_pdev->irq;
2861 } else {
2862 printk(KERN_WARNING
2863 "%s : request_irq fails for IRQ 0x%x\n ",
2864 __FUNCTION__, idd->idd_pdev->irq);
2866 ret = ioc4_attach_local(idd);
2867 if (ret)
2868 goto out4;
2870 /* register port with the serial core - 1 rs232, 1 rs422 */
2872 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2873 goto out4;
2875 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2876 goto out5;
2878 Num_of_ioc4_cards++;
2880 return ret;
2882 /* error exits that give back resources */
2883 out5:
2884 ioc4_serial_remove_one(idd);
2885 out4:
2886 kfree(soft);
2887 out3:
2888 kfree(control);
2889 out2:
2890 release_region(tmp_addr1, sizeof(struct ioc4_serial));
2891 out1:
2893 return ret;
2897 static struct ioc4_submodule ioc4_serial_submodule = {
2898 .is_name = "IOC4_serial",
2899 .is_owner = THIS_MODULE,
2900 .is_probe = ioc4_serial_attach_one,
2901 .is_remove = ioc4_serial_remove_one,
2902 };
2904 /**
2905 * ioc4_serial_init - module init
2906 */
2907 int ioc4_serial_init(void)
2909 int ret;
2911 /* register with serial core */
2912 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2913 printk(KERN_WARNING
2914 "%s: Couldn't register rs232 IOC4 serial driver\n",
2915 __FUNCTION__);
2916 return ret;
2918 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2919 printk(KERN_WARNING
2920 "%s: Couldn't register rs422 IOC4 serial driver\n",
2921 __FUNCTION__);
2922 return ret;
2925 /* register with IOC4 main module */
2926 return ioc4_register_submodule(&ioc4_serial_submodule);
2929 static void __devexit ioc4_serial_exit(void)
2931 ioc4_unregister_submodule(&ioc4_serial_submodule);
2932 uart_unregister_driver(&ioc4_uart_rs232);
2933 uart_unregister_driver(&ioc4_uart_rs422);
2936 module_init(ioc4_serial_init);
2937 module_exit(ioc4_serial_exit);
2939 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2940 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2941 MODULE_LICENSE("GPL");