ia64/linux-2.6.18-xen.hg

view drivers/serial/8250_au1x00.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * Serial Device Initialisation for Au1x00
3 *
4 * (C) Copyright Embedded Alley Solutions, Inc 2005
5 * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/module.h>
18 #include <linux/serial_core.h>
19 #include <linux/signal.h>
20 #include <linux/slab.h>
21 #include <linux/types.h>
23 #include <linux/serial_8250.h>
25 #include <asm/mach-au1x00/au1000.h>
27 #include "8250.h"
29 #define PORT(_base, _irq) \
30 { \
31 .iobase = _base, \
32 .membase = (void __iomem *)_base,\
33 .mapbase = CPHYSADDR(_base), \
34 .irq = _irq, \
35 .uartclk = 0, /* filled */ \
36 .regshift = 2, \
37 .iotype = UPIO_AU, \
38 .flags = UPF_SKIP_TEST \
39 }
41 static struct plat_serial8250_port au1x00_data[] = {
42 #if defined(CONFIG_SOC_AU1000)
43 PORT(UART0_ADDR, AU1000_UART0_INT),
44 PORT(UART1_ADDR, AU1000_UART1_INT),
45 PORT(UART2_ADDR, AU1000_UART2_INT),
46 PORT(UART3_ADDR, AU1000_UART3_INT),
47 #elif defined(CONFIG_SOC_AU1500)
48 PORT(UART0_ADDR, AU1500_UART0_INT),
49 PORT(UART3_ADDR, AU1500_UART3_INT),
50 #elif defined(CONFIG_SOC_AU1100)
51 PORT(UART0_ADDR, AU1100_UART0_INT),
52 PORT(UART1_ADDR, AU1100_UART1_INT),
53 /* The internal UART2 does not exist on the AU1100 processor. */
54 PORT(UART3_ADDR, AU1100_UART3_INT),
55 #elif defined(CONFIG_SOC_AU1550)
56 PORT(UART0_ADDR, AU1550_UART0_INT),
57 PORT(UART1_ADDR, AU1550_UART1_INT),
58 PORT(UART3_ADDR, AU1550_UART3_INT),
59 #elif defined(CONFIG_SOC_AU1200)
60 PORT(UART0_ADDR, AU1200_UART0_INT),
61 PORT(UART1_ADDR, AU1200_UART1_INT),
62 #endif
63 { },
64 };
66 static struct platform_device au1x00_device = {
67 .name = "serial8250",
68 .id = PLAT8250_DEV_AU1X00,
69 .dev = {
70 .platform_data = au1x00_data,
71 },
72 };
74 static int __init au1x00_init(void)
75 {
76 int i;
77 unsigned int uartclk;
79 /* get uart clock */
80 uartclk = get_au1x00_uart_baud_base() * 16;
82 /* fill up uartclk */
83 for (i = 0; au1x00_data[i].flags ; i++)
84 au1x00_data[i].uartclk = uartclk;
86 return platform_device_register(&au1x00_device);
87 }
89 /* XXX: Yes, I know this doesn't yet work. */
90 static void __exit au1x00_exit(void)
91 {
92 platform_device_unregister(&au1x00_device);
93 }
95 module_init(au1x00_init);
96 module_exit(au1x00_exit);
98 MODULE_AUTHOR("Pantelis Antoniou <pantelis@embeddedalley.com>");
99 MODULE_DESCRIPTION("8250 serial probe module for Au1x000 cards");
100 MODULE_LICENSE("GPL");