ia64/linux-2.6.18-xen.hg

view drivers/ieee1394/ieee1394.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * Generic IEEE 1394 definitions
3 */
5 #ifndef _IEEE1394_IEEE1394_H
6 #define _IEEE1394_IEEE1394_H
8 #define TCODE_WRITEQ 0x0
9 #define TCODE_WRITEB 0x1
10 #define TCODE_WRITE_RESPONSE 0x2
11 #define TCODE_READQ 0x4
12 #define TCODE_READB 0x5
13 #define TCODE_READQ_RESPONSE 0x6
14 #define TCODE_READB_RESPONSE 0x7
15 #define TCODE_CYCLE_START 0x8
16 #define TCODE_LOCK_REQUEST 0x9
17 #define TCODE_ISO_DATA 0xa
18 #define TCODE_STREAM_DATA 0xa
19 #define TCODE_LOCK_RESPONSE 0xb
21 #define RCODE_COMPLETE 0x0
22 #define RCODE_CONFLICT_ERROR 0x4
23 #define RCODE_DATA_ERROR 0x5
24 #define RCODE_TYPE_ERROR 0x6
25 #define RCODE_ADDRESS_ERROR 0x7
27 #define EXTCODE_MASK_SWAP 0x1
28 #define EXTCODE_COMPARE_SWAP 0x2
29 #define EXTCODE_FETCH_ADD 0x3
30 #define EXTCODE_LITTLE_ADD 0x4
31 #define EXTCODE_BOUNDED_ADD 0x5
32 #define EXTCODE_WRAP_ADD 0x6
34 #define ACK_COMPLETE 0x1
35 #define ACK_PENDING 0x2
36 #define ACK_BUSY_X 0x4
37 #define ACK_BUSY_A 0x5
38 #define ACK_BUSY_B 0x6
39 #define ACK_TARDY 0xb
40 #define ACK_CONFLICT_ERROR 0xc
41 #define ACK_DATA_ERROR 0xd
42 #define ACK_TYPE_ERROR 0xe
43 #define ACK_ADDRESS_ERROR 0xf
45 /* Non-standard "ACK codes" for internal use */
46 #define ACKX_NONE (-1)
47 #define ACKX_SEND_ERROR (-2)
48 #define ACKX_ABORTED (-3)
49 #define ACKX_TIMEOUT (-4)
52 #define IEEE1394_SPEED_100 0x00
53 #define IEEE1394_SPEED_200 0x01
54 #define IEEE1394_SPEED_400 0x02
55 #define IEEE1394_SPEED_800 0x03
56 #define IEEE1394_SPEED_1600 0x04
57 #define IEEE1394_SPEED_3200 0x05
58 /* The current highest tested speed supported by the subsystem */
59 #define IEEE1394_SPEED_MAX IEEE1394_SPEED_800
61 /* Maps speed values above to a string representation */
62 extern const char *hpsb_speedto_str[];
65 /* 1394a cable PHY packets */
66 #define SELFID_PWRCL_NO_POWER 0x0
67 #define SELFID_PWRCL_PROVIDE_15W 0x1
68 #define SELFID_PWRCL_PROVIDE_30W 0x2
69 #define SELFID_PWRCL_PROVIDE_45W 0x3
70 #define SELFID_PWRCL_USE_1W 0x4
71 #define SELFID_PWRCL_USE_3W 0x5
72 #define SELFID_PWRCL_USE_6W 0x6
73 #define SELFID_PWRCL_USE_10W 0x7
75 #define SELFID_PORT_CHILD 0x3
76 #define SELFID_PORT_PARENT 0x2
77 #define SELFID_PORT_NCONN 0x1
78 #define SELFID_PORT_NONE 0x0
80 #define PHYPACKET_LINKON 0x40000000
81 #define PHYPACKET_PHYCONFIG_R 0x00800000
82 #define PHYPACKET_PHYCONFIG_T 0x00400000
83 #define EXTPHYPACKET_TYPE_PING 0x00000000
84 #define EXTPHYPACKET_TYPE_REMOTEACCESS_BASE 0x00040000
85 #define EXTPHYPACKET_TYPE_REMOTEACCESS_PAGED 0x00140000
86 #define EXTPHYPACKET_TYPE_REMOTEREPLY_BASE 0x000C0000
87 #define EXTPHYPACKET_TYPE_REMOTEREPLY_PAGED 0x001C0000
88 #define EXTPHYPACKET_TYPE_REMOTECOMMAND 0x00200000
89 #define EXTPHYPACKET_TYPE_REMOTECONFIRMATION 0x00280000
90 #define EXTPHYPACKET_TYPE_RESUME 0x003C0000
92 #define EXTPHYPACKET_TYPEMASK 0xC0FC0000
94 #define PHYPACKET_PORT_SHIFT 24
95 #define PHYPACKET_GAPCOUNT_SHIFT 16
97 /* 1394a PHY register map bitmasks */
98 #define PHY_00_PHYSICAL_ID 0xFC
99 #define PHY_00_R 0x02 /* Root */
100 #define PHY_00_PS 0x01 /* Power Status*/
101 #define PHY_01_RHB 0x80 /* Root Hold-Off */
102 #define PHY_01_IBR 0x80 /* Initiate Bus Reset */
103 #define PHY_01_GAP_COUNT 0x3F
104 #define PHY_02_EXTENDED 0xE0 /* 0x7 for 1394a-compliant PHY */
105 #define PHY_02_TOTAL_PORTS 0x1F
106 #define PHY_03_MAX_SPEED 0xE0
107 #define PHY_03_DELAY 0x0F
108 #define PHY_04_LCTRL 0x80 /* Link Active Report Control */
109 #define PHY_04_CONTENDER 0x40
110 #define PHY_04_JITTER 0x38
111 #define PHY_04_PWR_CLASS 0x07 /* Power Class */
112 #define PHY_05_WATCHDOG 0x80
113 #define PHY_05_ISBR 0x40 /* Initiate Short Bus Reset */
114 #define PHY_05_LOOP 0x20 /* Loop Detect */
115 #define PHY_05_PWR_FAIL 0x10 /* Cable Power Failure Detect */
116 #define PHY_05_TIMEOUT 0x08 /* Arbitration State Machine Timeout */
117 #define PHY_05_PORT_EVENT 0x04 /* Port Event Detect */
118 #define PHY_05_ENAB_ACCEL 0x02 /* Enable Arbitration Acceleration */
119 #define PHY_05_ENAB_MULTI 0x01 /* Ena. Multispeed Packet Concatenation */
121 #include <asm/byteorder.h>
123 #ifdef __BIG_ENDIAN_BITFIELD
125 struct selfid {
126 u32 packet_identifier:2; /* always binary 10 */
127 u32 phy_id:6;
128 /* byte */
129 u32 extended:1; /* if true is struct ext_selfid */
130 u32 link_active:1;
131 u32 gap_count:6;
132 /* byte */
133 u32 speed:2;
134 u32 phy_delay:2;
135 u32 contender:1;
136 u32 power_class:3;
137 /* byte */
138 u32 port0:2;
139 u32 port1:2;
140 u32 port2:2;
141 u32 initiated_reset:1;
142 u32 more_packets:1;
143 } __attribute__((packed));
145 struct ext_selfid {
146 u32 packet_identifier:2; /* always binary 10 */
147 u32 phy_id:6;
148 /* byte */
149 u32 extended:1; /* if false is struct selfid */
150 u32 seq_nr:3;
151 u32 reserved:2;
152 u32 porta:2;
153 /* byte */
154 u32 portb:2;
155 u32 portc:2;
156 u32 portd:2;
157 u32 porte:2;
158 /* byte */
159 u32 portf:2;
160 u32 portg:2;
161 u32 porth:2;
162 u32 reserved2:1;
163 u32 more_packets:1;
164 } __attribute__((packed));
166 #elif defined __LITTLE_ENDIAN_BITFIELD /* __BIG_ENDIAN_BITFIELD */
168 /*
169 * Note: these mean to be bit fields of a big endian SelfID as seen on a little
170 * endian machine. Without swapping.
171 */
173 struct selfid {
174 u32 phy_id:6;
175 u32 packet_identifier:2; /* always binary 10 */
176 /* byte */
177 u32 gap_count:6;
178 u32 link_active:1;
179 u32 extended:1; /* if true is struct ext_selfid */
180 /* byte */
181 u32 power_class:3;
182 u32 contender:1;
183 u32 phy_delay:2;
184 u32 speed:2;
185 /* byte */
186 u32 more_packets:1;
187 u32 initiated_reset:1;
188 u32 port2:2;
189 u32 port1:2;
190 u32 port0:2;
191 } __attribute__((packed));
193 struct ext_selfid {
194 u32 phy_id:6;
195 u32 packet_identifier:2; /* always binary 10 */
196 /* byte */
197 u32 porta:2;
198 u32 reserved:2;
199 u32 seq_nr:3;
200 u32 extended:1; /* if false is struct selfid */
201 /* byte */
202 u32 porte:2;
203 u32 portd:2;
204 u32 portc:2;
205 u32 portb:2;
206 /* byte */
207 u32 more_packets:1;
208 u32 reserved2:1;
209 u32 porth:2;
210 u32 portg:2;
211 u32 portf:2;
212 } __attribute__((packed));
214 #else
215 #error What? PDP endian?
216 #endif /* __BIG_ENDIAN_BITFIELD */
219 #endif /* _IEEE1394_IEEE1394_H */