ia64/linux-2.6.18-xen.hg

view drivers/ide/ide-dma.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000
3 *
4 * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 */
8 /*
9 * Special Thanks to Mark for his Six years of work.
10 *
11 * Copyright (c) 1995-1998 Mark Lord
12 * May be copied or modified under the terms of the GNU General Public License
13 */
15 /*
16 * This module provides support for the bus-master IDE DMA functions
17 * of various PCI chipsets, including the Intel PIIX (i82371FB for
18 * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and
19 * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset)
20 * ("PIIX" stands for "PCI ISA IDE Xcellerator").
21 *
22 * Pretty much the same code works for other IDE PCI bus-mastering chipsets.
23 *
24 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
25 *
26 * By default, DMA support is prepared for use, but is currently enabled only
27 * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single),
28 * or which are recognized as "good" (see table below). Drives with only mode0
29 * or mode1 (multi/single) DMA should also work with this chipset/driver
30 * (eg. MC2112A) but are not enabled by default.
31 *
32 * Use "hdparm -i" to view modes supported by a given drive.
33 *
34 * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling
35 * DMA support, but must be (re-)compiled against this kernel version or later.
36 *
37 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
38 * If problems arise, ide.c will disable DMA operation after a few retries.
39 * This error recovery mechanism works and has been extremely well exercised.
40 *
41 * IDE drives, depending on their vintage, may support several different modes
42 * of DMA operation. The boot-time modes are indicated with a "*" in
43 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
44 * the "hdparm -X" feature. There is seldom a need to do this, as drives
45 * normally power-up with their "best" PIO/DMA modes enabled.
46 *
47 * Testing has been done with a rather extensive number of drives,
48 * with Quantum & Western Digital models generally outperforming the pack,
49 * and Fujitsu & Conner (and some Seagate which are really Conner) drives
50 * showing more lackluster throughput.
51 *
52 * Keep an eye on /var/adm/messages for "DMA disabled" messages.
53 *
54 * Some people have reported trouble with Intel Zappa motherboards.
55 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
56 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
57 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
58 *
59 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
60 * fixing the problem with the BIOS on some Acer motherboards.
61 *
62 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
63 * "TX" chipset compatibility and for providing patches for the "TX" chipset.
64 *
65 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
66 * at generic DMA -- his patches were referred to when preparing this code.
67 *
68 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
69 * for supplying a Promise UDMA board & WD UDMA drive for this work!
70 *
71 * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports.
72 *
73 * ATA-66/100 and recovery functions, I forgot the rest......
74 *
75 */
77 #include <linux/module.h>
78 #include <linux/types.h>
79 #include <linux/kernel.h>
80 #include <linux/timer.h>
81 #include <linux/mm.h>
82 #include <linux/interrupt.h>
83 #include <linux/pci.h>
84 #include <linux/init.h>
85 #include <linux/ide.h>
86 #include <linux/delay.h>
87 #include <linux/scatterlist.h>
89 #include <asm/io.h>
90 #include <asm/irq.h>
92 static const struct drive_list_entry drive_whitelist [] = {
94 { "Micropolis 2112A" , "ALL" },
95 { "CONNER CTMA 4000" , "ALL" },
96 { "CONNER CTT8000-A" , "ALL" },
97 { "ST34342A" , "ALL" },
98 { NULL , NULL }
99 };
101 static const struct drive_list_entry drive_blacklist [] = {
103 { "WDC AC11000H" , "ALL" },
104 { "WDC AC22100H" , "ALL" },
105 { "WDC AC32500H" , "ALL" },
106 { "WDC AC33100H" , "ALL" },
107 { "WDC AC31600H" , "ALL" },
108 { "WDC AC32100H" , "24.09P07" },
109 { "WDC AC23200L" , "21.10N21" },
110 { "Compaq CRD-8241B" , "ALL" },
111 { "CRD-8400B" , "ALL" },
112 { "CRD-8480B", "ALL" },
113 { "CRD-8482B", "ALL" },
114 { "CRD-84" , "ALL" },
115 { "SanDisk SDP3B" , "ALL" },
116 { "SanDisk SDP3B-64" , "ALL" },
117 { "SANYO CD-ROM CRD" , "ALL" },
118 { "HITACHI CDR-8" , "ALL" },
119 { "HITACHI CDR-8335" , "ALL" },
120 { "HITACHI CDR-8435" , "ALL" },
121 { "Toshiba CD-ROM XM-6202B" , "ALL" },
122 { "CD-532E-A" , "ALL" },
123 { "E-IDE CD-ROM CR-840", "ALL" },
124 { "CD-ROM Drive/F5A", "ALL" },
125 { "WPI CDD-820", "ALL" },
126 { "SAMSUNG CD-ROM SC-148C", "ALL" },
127 { "SAMSUNG CD-ROM SC", "ALL" },
128 { "SanDisk SDP3B-64" , "ALL" },
129 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
130 { "_NEC DV5800A", "ALL" },
131 { NULL , NULL }
133 };
135 /**
136 * ide_in_drive_list - look for drive in black/white list
137 * @id: drive identifier
138 * @drive_table: list to inspect
139 *
140 * Look for a drive in the blacklist and the whitelist tables
141 * Returns 1 if the drive is found in the table.
142 */
144 int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
145 {
146 for ( ; drive_table->id_model ; drive_table++)
147 if ((!strcmp(drive_table->id_model, id->model)) &&
148 ((strstr(drive_table->id_firmware, id->fw_rev)) ||
149 (!strcmp(drive_table->id_firmware, "ALL"))))
150 return 1;
151 return 0;
152 }
154 EXPORT_SYMBOL_GPL(ide_in_drive_list);
156 /**
157 * ide_dma_intr - IDE DMA interrupt handler
158 * @drive: the drive the interrupt is for
159 *
160 * Handle an interrupt completing a read/write DMA transfer on an
161 * IDE device
162 */
164 ide_startstop_t ide_dma_intr (ide_drive_t *drive)
165 {
166 u8 stat = 0, dma_stat = 0;
168 dma_stat = HWIF(drive)->ide_dma_end(drive);
169 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
170 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
171 if (!dma_stat) {
172 struct request *rq = HWGROUP(drive)->rq;
174 if (rq->rq_disk) {
175 ide_driver_t *drv;
177 drv = *(ide_driver_t **)rq->rq_disk->private_data;
178 drv->end_request(drive, 1, rq->nr_sectors);
179 } else
180 ide_end_request(drive, 1, rq->nr_sectors);
181 return ide_stopped;
182 }
183 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
184 drive->name, dma_stat);
185 }
186 return ide_error(drive, "dma_intr", stat);
187 }
189 EXPORT_SYMBOL_GPL(ide_dma_intr);
191 #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
192 /**
193 * ide_build_sglist - map IDE scatter gather for DMA I/O
194 * @drive: the drive to build the DMA table for
195 * @rq: the request holding the sg list
196 *
197 * Perform the PCI mapping magic necessary to access the source or
198 * target buffers of a request via PCI DMA. The lower layers of the
199 * kernel provide the necessary cache management so that we can
200 * operate in a portable fashion
201 */
203 int ide_build_sglist(ide_drive_t *drive, struct request *rq)
204 {
205 ide_hwif_t *hwif = HWIF(drive);
206 struct scatterlist *sg = hwif->sg_table;
208 BUG_ON((rq->flags & REQ_DRIVE_TASKFILE) && rq->nr_sectors > 256);
210 ide_map_sg(drive, rq);
212 if (rq_data_dir(rq) == READ)
213 hwif->sg_dma_direction = PCI_DMA_FROMDEVICE;
214 else
215 hwif->sg_dma_direction = PCI_DMA_TODEVICE;
217 return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
218 }
220 EXPORT_SYMBOL_GPL(ide_build_sglist);
222 /**
223 * ide_build_dmatable - build IDE DMA table
224 *
225 * ide_build_dmatable() prepares a dma request. We map the command
226 * to get the pci bus addresses of the buffers and then build up
227 * the PRD table that the IDE layer wants to be fed. The code
228 * knows about the 64K wrap bug in the CS5530.
229 *
230 * Returns the number of built PRD entries if all went okay,
231 * returns 0 otherwise.
232 *
233 * May also be invoked from trm290.c
234 */
236 int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
237 {
238 ide_hwif_t *hwif = HWIF(drive);
239 unsigned int *table = hwif->dmatable_cpu;
240 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
241 unsigned int count = 0;
242 int i;
243 struct scatterlist *sg;
245 hwif->sg_nents = i = ide_build_sglist(drive, rq);
247 if (!i)
248 return 0;
250 sg = hwif->sg_table;
251 while (i) {
252 u32 cur_addr;
253 u32 cur_len;
255 cur_addr = sg_dma_address(sg);
256 cur_len = sg_dma_len(sg);
258 /*
259 * Fill in the dma table, without crossing any 64kB boundaries.
260 * Most hardware requires 16-bit alignment of all blocks,
261 * but the trm290 requires 32-bit alignment.
262 */
264 while (cur_len) {
265 if (count++ >= PRD_ENTRIES) {
266 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
267 goto use_pio_instead;
268 } else {
269 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
271 if (bcount > cur_len)
272 bcount = cur_len;
273 *table++ = cpu_to_le32(cur_addr);
274 xcount = bcount & 0xffff;
275 if (is_trm290)
276 xcount = ((xcount >> 2) - 1) << 16;
277 if (xcount == 0x0000) {
278 /*
279 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
280 * but at least one (e.g. CS5530) misinterprets it as zero (!).
281 * So here we break the 64KB entry into two 32KB entries instead.
282 */
283 if (count++ >= PRD_ENTRIES) {
284 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
285 goto use_pio_instead;
286 }
287 *table++ = cpu_to_le32(0x8000);
288 *table++ = cpu_to_le32(cur_addr + 0x8000);
289 xcount = 0x8000;
290 }
291 *table++ = cpu_to_le32(xcount);
292 cur_addr += bcount;
293 cur_len -= bcount;
294 }
295 }
297 sg++;
298 i--;
299 }
301 if (count) {
302 if (!is_trm290)
303 *--table |= cpu_to_le32(0x80000000);
304 return count;
305 }
306 printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
307 use_pio_instead:
308 pci_unmap_sg(hwif->pci_dev,
309 hwif->sg_table,
310 hwif->sg_nents,
311 hwif->sg_dma_direction);
312 return 0; /* revert to PIO for this request */
313 }
315 EXPORT_SYMBOL_GPL(ide_build_dmatable);
317 /**
318 * ide_destroy_dmatable - clean up DMA mapping
319 * @drive: The drive to unmap
320 *
321 * Teardown mappings after DMA has completed. This must be called
322 * after the completion of each use of ide_build_dmatable and before
323 * the next use of ide_build_dmatable. Failure to do so will cause
324 * an oops as only one mapping can be live for each target at a given
325 * time.
326 */
328 void ide_destroy_dmatable (ide_drive_t *drive)
329 {
330 struct pci_dev *dev = HWIF(drive)->pci_dev;
331 struct scatterlist *sg = HWIF(drive)->sg_table;
332 int nents = HWIF(drive)->sg_nents;
334 pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction);
335 }
337 EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
339 /**
340 * config_drive_for_dma - attempt to activate IDE DMA
341 * @drive: the drive to place in DMA mode
342 *
343 * If the drive supports at least mode 2 DMA or UDMA of any kind
344 * then attempt to place it into DMA mode. Drives that are known to
345 * support DMA but predate the DMA properties or that are known
346 * to have DMA handling bugs are also set up appropriately based
347 * on the good/bad drive lists.
348 */
350 static int config_drive_for_dma (ide_drive_t *drive)
351 {
352 struct hd_driveid *id = drive->id;
353 ide_hwif_t *hwif = HWIF(drive);
355 if ((id->capability & 1) && hwif->autodma) {
356 /*
357 * Enable DMA on any drive that has
358 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
359 */
360 if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
361 return hwif->ide_dma_on(drive);
362 /*
363 * Enable DMA on any drive that has mode2 DMA
364 * (multi or single) enabled
365 */
366 if (id->field_valid & 2) /* regular DMA */
367 if ((id->dma_mword & 0x404) == 0x404 ||
368 (id->dma_1word & 0x404) == 0x404)
369 return hwif->ide_dma_on(drive);
371 /* Consult the list of known "good" drives */
372 if (__ide_dma_good_drive(drive))
373 return hwif->ide_dma_on(drive);
374 }
375 // if (hwif->tuneproc != NULL) hwif->tuneproc(drive, 255);
376 return hwif->ide_dma_off_quietly(drive);
377 }
379 /**
380 * dma_timer_expiry - handle a DMA timeout
381 * @drive: Drive that timed out
382 *
383 * An IDE DMA transfer timed out. In the event of an error we ask
384 * the driver to resolve the problem, if a DMA transfer is still
385 * in progress we continue to wait (arguably we need to add a
386 * secondary 'I don't care what the drive thinks' timeout here)
387 * Finally if we have an interrupt we let it complete the I/O.
388 * But only one time - we clear expiry and if it's still not
389 * completed after WAIT_CMD, we error and retry in PIO.
390 * This can occur if an interrupt is lost or due to hang or bugs.
391 */
393 static int dma_timer_expiry (ide_drive_t *drive)
394 {
395 ide_hwif_t *hwif = HWIF(drive);
396 u8 dma_stat = hwif->INB(hwif->dma_status);
398 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
399 drive->name, dma_stat);
401 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
402 return WAIT_CMD;
404 HWGROUP(drive)->expiry = NULL; /* one free ride for now */
406 /* 1 dmaing, 2 error, 4 intr */
407 if (dma_stat & 2) /* ERROR */
408 return -1;
410 if (dma_stat & 1) /* DMAing */
411 return WAIT_CMD;
413 if (dma_stat & 4) /* Got an Interrupt */
414 return WAIT_CMD;
416 return 0; /* Status is unknown -- reset the bus */
417 }
419 /**
420 * __ide_dma_host_off - Generic DMA kill
421 * @drive: drive to control
422 *
423 * Perform the generic IDE controller DMA off operation. This
424 * works for most IDE bus mastering controllers
425 */
427 int __ide_dma_host_off (ide_drive_t *drive)
428 {
429 ide_hwif_t *hwif = HWIF(drive);
430 u8 unit = (drive->select.b.unit & 0x01);
431 u8 dma_stat = hwif->INB(hwif->dma_status);
433 hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status);
434 return 0;
435 }
437 EXPORT_SYMBOL(__ide_dma_host_off);
439 /**
440 * __ide_dma_host_off_quietly - Generic DMA kill
441 * @drive: drive to control
442 *
443 * Turn off the current DMA on this IDE controller.
444 */
446 int __ide_dma_off_quietly (ide_drive_t *drive)
447 {
448 drive->using_dma = 0;
449 ide_toggle_bounce(drive, 0);
451 if (HWIF(drive)->ide_dma_host_off(drive))
452 return 1;
454 return 0;
455 }
457 EXPORT_SYMBOL(__ide_dma_off_quietly);
458 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
460 /**
461 * __ide_dma_off - disable DMA on a device
462 * @drive: drive to disable DMA on
463 *
464 * Disable IDE DMA for a device on this IDE controller.
465 * Inform the user that DMA has been disabled.
466 */
468 int __ide_dma_off (ide_drive_t *drive)
469 {
470 printk(KERN_INFO "%s: DMA disabled\n", drive->name);
471 return HWIF(drive)->ide_dma_off_quietly(drive);
472 }
474 EXPORT_SYMBOL(__ide_dma_off);
476 #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
477 /**
478 * __ide_dma_host_on - Enable DMA on a host
479 * @drive: drive to enable for DMA
480 *
481 * Enable DMA on an IDE controller following generic bus mastering
482 * IDE controller behaviour
483 */
485 int __ide_dma_host_on (ide_drive_t *drive)
486 {
487 if (drive->using_dma) {
488 ide_hwif_t *hwif = HWIF(drive);
489 u8 unit = (drive->select.b.unit & 0x01);
490 u8 dma_stat = hwif->INB(hwif->dma_status);
492 hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status);
493 return 0;
494 }
495 return 1;
496 }
498 EXPORT_SYMBOL(__ide_dma_host_on);
500 /**
501 * __ide_dma_on - Enable DMA on a device
502 * @drive: drive to enable DMA on
503 *
504 * Enable IDE DMA for a device on this IDE controller.
505 */
507 int __ide_dma_on (ide_drive_t *drive)
508 {
509 /* consult the list of known "bad" drives */
510 if (__ide_dma_bad_drive(drive))
511 return 1;
513 drive->using_dma = 1;
514 ide_toggle_bounce(drive, 1);
516 if (HWIF(drive)->ide_dma_host_on(drive))
517 return 1;
519 return 0;
520 }
522 EXPORT_SYMBOL(__ide_dma_on);
524 /**
525 * __ide_dma_check - check DMA setup
526 * @drive: drive to check
527 *
528 * Don't use - due for extermination
529 */
531 int __ide_dma_check (ide_drive_t *drive)
532 {
533 return config_drive_for_dma(drive);
534 }
536 EXPORT_SYMBOL(__ide_dma_check);
538 /**
539 * ide_dma_setup - begin a DMA phase
540 * @drive: target device
541 *
542 * Build an IDE DMA PRD (IDE speak for scatter gather table)
543 * and then set up the DMA transfer registers for a device
544 * that follows generic IDE PCI DMA behaviour. Controllers can
545 * override this function if they need to
546 *
547 * Returns 0 on success. If a PIO fallback is required then 1
548 * is returned.
549 */
551 int ide_dma_setup(ide_drive_t *drive)
552 {
553 ide_hwif_t *hwif = drive->hwif;
554 struct request *rq = HWGROUP(drive)->rq;
555 unsigned int reading;
556 u8 dma_stat;
558 if (rq_data_dir(rq))
559 reading = 0;
560 else
561 reading = 1 << 3;
563 /* fall back to pio! */
564 if (!ide_build_dmatable(drive, rq)) {
565 ide_map_sg(drive, rq);
566 return 1;
567 }
569 /* PRD table */
570 hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable);
572 /* specify r/w */
573 hwif->OUTB(reading, hwif->dma_command);
575 /* read dma_status for INTR & ERROR flags */
576 dma_stat = hwif->INB(hwif->dma_status);
578 /* clear INTR & ERROR flags */
579 hwif->OUTB(dma_stat|6, hwif->dma_status);
580 drive->waiting_for_dma = 1;
581 return 0;
582 }
584 EXPORT_SYMBOL_GPL(ide_dma_setup);
586 static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
587 {
588 /* issue cmd to drive */
589 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
590 }
592 void ide_dma_start(ide_drive_t *drive)
593 {
594 ide_hwif_t *hwif = HWIF(drive);
595 u8 dma_cmd = hwif->INB(hwif->dma_command);
597 /* Note that this is done *after* the cmd has
598 * been issued to the drive, as per the BM-IDE spec.
599 * The Promise Ultra33 doesn't work correctly when
600 * we do this part before issuing the drive cmd.
601 */
602 /* start DMA */
603 hwif->OUTB(dma_cmd|1, hwif->dma_command);
604 hwif->dma = 1;
605 wmb();
606 }
608 EXPORT_SYMBOL_GPL(ide_dma_start);
610 /* returns 1 on error, 0 otherwise */
611 int __ide_dma_end (ide_drive_t *drive)
612 {
613 ide_hwif_t *hwif = HWIF(drive);
614 u8 dma_stat = 0, dma_cmd = 0;
616 drive->waiting_for_dma = 0;
617 /* get dma_command mode */
618 dma_cmd = hwif->INB(hwif->dma_command);
619 /* stop DMA */
620 hwif->OUTB(dma_cmd&~1, hwif->dma_command);
621 /* get DMA status */
622 dma_stat = hwif->INB(hwif->dma_status);
623 /* clear the INTR & ERROR bits */
624 hwif->OUTB(dma_stat|6, hwif->dma_status);
625 /* purge DMA mappings */
626 ide_destroy_dmatable(drive);
627 /* verify good DMA status */
628 hwif->dma = 0;
629 wmb();
630 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
631 }
633 EXPORT_SYMBOL(__ide_dma_end);
635 /* returns 1 if dma irq issued, 0 otherwise */
636 static int __ide_dma_test_irq(ide_drive_t *drive)
637 {
638 ide_hwif_t *hwif = HWIF(drive);
639 u8 dma_stat = hwif->INB(hwif->dma_status);
641 #if 0 /* do not set unless you know what you are doing */
642 if (dma_stat & 4) {
643 u8 stat = hwif->INB(IDE_STATUS_REG);
644 hwif->OUTB(hwif->dma_status, dma_stat & 0xE4);
645 }
646 #endif
647 /* return 1 if INTR asserted */
648 if ((dma_stat & 4) == 4)
649 return 1;
650 if (!drive->waiting_for_dma)
651 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
652 drive->name, __FUNCTION__);
653 return 0;
654 }
655 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
657 int __ide_dma_bad_drive (ide_drive_t *drive)
658 {
659 struct hd_driveid *id = drive->id;
661 int blacklist = ide_in_drive_list(id, drive_blacklist);
662 if (blacklist) {
663 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
664 drive->name, id->model);
665 return blacklist;
666 }
667 return 0;
668 }
670 EXPORT_SYMBOL(__ide_dma_bad_drive);
672 int __ide_dma_good_drive (ide_drive_t *drive)
673 {
674 struct hd_driveid *id = drive->id;
675 return ide_in_drive_list(id, drive_whitelist);
676 }
678 EXPORT_SYMBOL(__ide_dma_good_drive);
680 int ide_use_dma(ide_drive_t *drive)
681 {
682 struct hd_driveid *id = drive->id;
683 ide_hwif_t *hwif = drive->hwif;
685 /* consult the list of known "bad" drives */
686 if (__ide_dma_bad_drive(drive))
687 return 0;
689 /* capable of UltraDMA modes */
690 if (id->field_valid & 4) {
691 if (hwif->ultra_mask & id->dma_ultra)
692 return 1;
693 }
695 /* capable of regular DMA modes */
696 if (id->field_valid & 2) {
697 if (hwif->mwdma_mask & id->dma_mword)
698 return 1;
699 if (hwif->swdma_mask & id->dma_1word)
700 return 1;
701 }
703 /* consult the list of known "good" drives */
704 if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
705 return 1;
707 return 0;
708 }
710 EXPORT_SYMBOL_GPL(ide_use_dma);
712 void ide_dma_verbose(ide_drive_t *drive)
713 {
714 struct hd_driveid *id = drive->id;
715 ide_hwif_t *hwif = HWIF(drive);
717 if (id->field_valid & 4) {
718 if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
719 goto bug_dma_off;
720 if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) {
721 if (((id->dma_ultra >> 11) & 0x1F) &&
722 eighty_ninty_three(drive)) {
723 if ((id->dma_ultra >> 15) & 1) {
724 printk(", UDMA(mode 7)");
725 } else if ((id->dma_ultra >> 14) & 1) {
726 printk(", UDMA(133)");
727 } else if ((id->dma_ultra >> 13) & 1) {
728 printk(", UDMA(100)");
729 } else if ((id->dma_ultra >> 12) & 1) {
730 printk(", UDMA(66)");
731 } else if ((id->dma_ultra >> 11) & 1) {
732 printk(", UDMA(44)");
733 } else
734 goto mode_two;
735 } else {
736 mode_two:
737 if ((id->dma_ultra >> 10) & 1) {
738 printk(", UDMA(33)");
739 } else if ((id->dma_ultra >> 9) & 1) {
740 printk(", UDMA(25)");
741 } else if ((id->dma_ultra >> 8) & 1) {
742 printk(", UDMA(16)");
743 }
744 }
745 } else {
746 printk(", (U)DMA"); /* Can be BIOS-enabled! */
747 }
748 } else if (id->field_valid & 2) {
749 if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
750 goto bug_dma_off;
751 printk(", DMA");
752 } else if (id->field_valid & 1) {
753 goto bug_dma_off;
754 }
755 return;
756 bug_dma_off:
757 printk(", BUG DMA OFF");
758 hwif->ide_dma_off_quietly(drive);
759 return;
760 }
762 EXPORT_SYMBOL(ide_dma_verbose);
764 #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
765 int __ide_dma_lostirq (ide_drive_t *drive)
766 {
767 printk("%s: DMA interrupt recovery\n", drive->name);
768 return 1;
769 }
771 EXPORT_SYMBOL(__ide_dma_lostirq);
773 int __ide_dma_timeout (ide_drive_t *drive)
774 {
775 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
776 if (HWIF(drive)->ide_dma_test_irq(drive))
777 return 0;
779 return HWIF(drive)->ide_dma_end(drive);
780 }
782 EXPORT_SYMBOL(__ide_dma_timeout);
784 /*
785 * Needed for allowing full modular support of ide-driver
786 */
787 static int ide_release_dma_engine(ide_hwif_t *hwif)
788 {
789 if (hwif->dmatable_cpu) {
790 pci_free_consistent(hwif->pci_dev,
791 PRD_ENTRIES * PRD_BYTES,
792 hwif->dmatable_cpu,
793 hwif->dmatable_dma);
794 hwif->dmatable_cpu = NULL;
795 }
796 return 1;
797 }
799 static int ide_release_iomio_dma(ide_hwif_t *hwif)
800 {
801 if ((hwif->dma_extra) && (hwif->channel == 0))
802 release_region((hwif->dma_base + 16), hwif->dma_extra);
803 release_region(hwif->dma_base, 8);
804 if (hwif->dma_base2)
805 release_region(hwif->dma_base, 8);
806 return 1;
807 }
809 /*
810 * Needed for allowing full modular support of ide-driver
811 */
812 int ide_release_dma (ide_hwif_t *hwif)
813 {
814 if (hwif->mmio == 2)
815 return 1;
816 if (hwif->chipset == ide_etrax100)
817 return 1;
819 ide_release_dma_engine(hwif);
820 return ide_release_iomio_dma(hwif);
821 }
823 static int ide_allocate_dma_engine(ide_hwif_t *hwif)
824 {
825 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
826 PRD_ENTRIES * PRD_BYTES,
827 &hwif->dmatable_dma);
829 if (hwif->dmatable_cpu)
830 return 0;
832 printk(KERN_ERR "%s: -- Error, unable to allocate%s DMA table(s).\n",
833 hwif->cds->name, !hwif->dmatable_cpu ? " CPU" : "");
835 ide_release_dma_engine(hwif);
836 return 1;
837 }
839 static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
840 {
841 printk(KERN_INFO " %s: MMIO-DMA ", hwif->name);
843 hwif->dma_base = base;
844 if (hwif->cds->extra && hwif->channel == 0)
845 hwif->dma_extra = hwif->cds->extra;
847 if(hwif->mate)
848 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
849 else
850 hwif->dma_master = base;
851 return 0;
852 }
854 static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
855 {
856 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
857 hwif->name, base, base + ports - 1);
858 if (!request_region(base, ports, hwif->name)) {
859 printk(" -- Error, ports in use.\n");
860 return 1;
861 }
862 hwif->dma_base = base;
863 if ((hwif->cds->extra) && (hwif->channel == 0)) {
864 request_region(base+16, hwif->cds->extra, hwif->cds->name);
865 hwif->dma_extra = hwif->cds->extra;
866 }
868 if(hwif->mate)
869 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
870 else
871 hwif->dma_master = base;
872 if (hwif->dma_base2) {
873 if (!request_region(hwif->dma_base2, ports, hwif->name))
874 {
875 printk(" -- Error, secondary ports in use.\n");
876 release_region(base, ports);
877 return 1;
878 }
879 }
880 return 0;
881 }
883 static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
884 {
885 if (hwif->mmio == 2)
886 return ide_mapped_mmio_dma(hwif, base,ports);
887 BUG_ON(hwif->mmio == 1);
888 return ide_iomio_dma(hwif, base, ports);
889 }
891 /*
892 * This can be called for a dynamically installed interface. Don't __init it
893 */
894 void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports)
895 {
896 if (ide_dma_iobase(hwif, dma_base, num_ports))
897 return;
899 if (ide_allocate_dma_engine(hwif)) {
900 ide_release_dma(hwif);
901 return;
902 }
904 if (!(hwif->dma_command))
905 hwif->dma_command = hwif->dma_base;
906 if (!(hwif->dma_vendor1))
907 hwif->dma_vendor1 = (hwif->dma_base + 1);
908 if (!(hwif->dma_status))
909 hwif->dma_status = (hwif->dma_base + 2);
910 if (!(hwif->dma_vendor3))
911 hwif->dma_vendor3 = (hwif->dma_base + 3);
912 if (!(hwif->dma_prdtable))
913 hwif->dma_prdtable = (hwif->dma_base + 4);
915 if (!hwif->ide_dma_off_quietly)
916 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
917 if (!hwif->ide_dma_host_off)
918 hwif->ide_dma_host_off = &__ide_dma_host_off;
919 if (!hwif->ide_dma_on)
920 hwif->ide_dma_on = &__ide_dma_on;
921 if (!hwif->ide_dma_host_on)
922 hwif->ide_dma_host_on = &__ide_dma_host_on;
923 if (!hwif->ide_dma_check)
924 hwif->ide_dma_check = &__ide_dma_check;
925 if (!hwif->dma_setup)
926 hwif->dma_setup = &ide_dma_setup;
927 if (!hwif->dma_exec_cmd)
928 hwif->dma_exec_cmd = &ide_dma_exec_cmd;
929 if (!hwif->dma_start)
930 hwif->dma_start = &ide_dma_start;
931 if (!hwif->ide_dma_end)
932 hwif->ide_dma_end = &__ide_dma_end;
933 if (!hwif->ide_dma_test_irq)
934 hwif->ide_dma_test_irq = &__ide_dma_test_irq;
935 if (!hwif->ide_dma_timeout)
936 hwif->ide_dma_timeout = &__ide_dma_timeout;
937 if (!hwif->ide_dma_lostirq)
938 hwif->ide_dma_lostirq = &__ide_dma_lostirq;
940 if (hwif->chipset != ide_trm290) {
941 u8 dma_stat = hwif->INB(hwif->dma_status);
942 printk(", BIOS settings: %s:%s, %s:%s",
943 hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio",
944 hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio");
945 }
946 printk("\n");
948 BUG_ON(!hwif->dma_master);
949 }
951 EXPORT_SYMBOL_GPL(ide_setup_dma);
952 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */