ia64/linux-2.6.18-xen.hg

view drivers/char/pc8736x_gpio.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /* linux/drivers/char/pc8736x_gpio.c
3 National Semiconductor PC8736x GPIO driver. Allows a user space
4 process to play with the GPIO pins.
6 Copyright (c) 2005,2006 Jim Cromie <jim.cromie@gmail.com>
8 adapted from linux/drivers/char/scx200_gpio.c
9 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>,
10 */
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/cdev.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/mutex.h>
21 #include <linux/nsc_gpio.h>
22 #include <linux/platform_device.h>
23 #include <asm/uaccess.h>
25 #define DEVNAME "pc8736x_gpio"
27 MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
28 MODULE_DESCRIPTION("NatSemi/Winbond PC-8736x GPIO Pin Driver");
29 MODULE_LICENSE("GPL");
31 static int major; /* default to dynamic major */
32 module_param(major, int, 0);
33 MODULE_PARM_DESC(major, "Major device number");
35 static DEFINE_MUTEX(pc8736x_gpio_config_lock);
36 static unsigned pc8736x_gpio_base;
37 static u8 pc8736x_gpio_shadow[4];
39 #define SIO_BASE1 0x2E /* 1st command-reg to check */
40 #define SIO_BASE2 0x4E /* alt command-reg to check */
42 #define SIO_SID 0x20 /* SuperI/O ID Register */
43 #define SIO_SID_VALUE 0xe9 /* Expected value in SuperI/O ID Register */
45 #define SIO_CF1 0x21 /* chip config, bit0 is chip enable */
47 #define PC8736X_GPIO_RANGE 16 /* ioaddr range */
48 #define PC8736X_GPIO_CT 32 /* minors matching 4 8 bit ports */
50 #define SIO_UNIT_SEL 0x7 /* unit select reg */
51 #define SIO_UNIT_ACT 0x30 /* unit enable */
52 #define SIO_GPIO_UNIT 0x7 /* unit number of GPIO */
53 #define SIO_VLM_UNIT 0x0D
54 #define SIO_TMS_UNIT 0x0E
56 /* config-space addrs to read/write each unit's runtime addr */
57 #define SIO_BASE_HADDR 0x60
58 #define SIO_BASE_LADDR 0x61
60 /* GPIO config-space pin-control addresses */
61 #define SIO_GPIO_PIN_SELECT 0xF0
62 #define SIO_GPIO_PIN_CONFIG 0xF1
63 #define SIO_GPIO_PIN_EVENT 0xF2
65 static unsigned char superio_cmd = 0;
66 static unsigned char selected_device = 0xFF; /* bogus start val */
68 /* GPIO port runtime access, functionality */
69 static int port_offset[] = { 0, 4, 8, 10 }; /* non-uniform offsets ! */
70 /* static int event_capable[] = { 1, 1, 0, 0 }; ports 2,3 are hobbled */
72 #define PORT_OUT 0
73 #define PORT_IN 1
74 #define PORT_EVT_EN 2
75 #define PORT_EVT_STST 3
77 static struct platform_device *pdev; /* use in dev_*() */
79 static inline void superio_outb(int addr, int val)
80 {
81 outb_p(addr, superio_cmd);
82 outb_p(val, superio_cmd + 1);
83 }
85 static inline int superio_inb(int addr)
86 {
87 outb_p(addr, superio_cmd);
88 return inb_p(superio_cmd + 1);
89 }
91 static int pc8736x_superio_present(void)
92 {
93 /* try the 2 possible values, read a hardware reg to verify */
94 superio_cmd = SIO_BASE1;
95 if (superio_inb(SIO_SID) == SIO_SID_VALUE)
96 return superio_cmd;
98 superio_cmd = SIO_BASE2;
99 if (superio_inb(SIO_SID) == SIO_SID_VALUE)
100 return superio_cmd;
102 return 0;
103 }
105 static void device_select(unsigned devldn)
106 {
107 superio_outb(SIO_UNIT_SEL, devldn);
108 selected_device = devldn;
109 }
111 static void select_pin(unsigned iminor)
112 {
113 /* select GPIO port/pin from device minor number */
114 device_select(SIO_GPIO_UNIT);
115 superio_outb(SIO_GPIO_PIN_SELECT,
116 ((iminor << 1) & 0xF0) | (iminor & 0x7));
117 }
119 static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits,
120 u32 func_slct)
121 {
122 u32 config, new_config;
124 mutex_lock(&pc8736x_gpio_config_lock);
126 device_select(SIO_GPIO_UNIT);
127 select_pin(index);
129 /* read current config value */
130 config = superio_inb(func_slct);
132 /* set new config */
133 new_config = (config & mask) | bits;
134 superio_outb(func_slct, new_config);
136 mutex_unlock(&pc8736x_gpio_config_lock);
138 return config;
139 }
141 static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits)
142 {
143 return pc8736x_gpio_configure_fn(index, mask, bits,
144 SIO_GPIO_PIN_CONFIG);
145 }
147 static int pc8736x_gpio_get(unsigned minor)
148 {
149 int port, bit, val;
151 port = minor >> 3;
152 bit = minor & 7;
153 val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
154 val >>= bit;
155 val &= 1;
157 dev_dbg(&pdev->dev, "_gpio_get(%d from %x bit %d) == val %d\n",
158 minor, pc8736x_gpio_base + port_offset[port] + PORT_IN, bit,
159 val);
161 return val;
162 }
164 static void pc8736x_gpio_set(unsigned minor, int val)
165 {
166 int port, bit, curval;
168 minor &= 0x1f;
169 port = minor >> 3;
170 bit = minor & 7;
171 curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
173 dev_dbg(&pdev->dev, "addr:%x cur:%x bit-pos:%d cur-bit:%x + new:%d -> bit-new:%d\n",
174 pc8736x_gpio_base + port_offset[port] + PORT_OUT,
175 curval, bit, (curval & ~(1 << bit)), val, (val << bit));
177 val = (curval & ~(1 << bit)) | (val << bit);
179 dev_dbg(&pdev->dev, "gpio_set(minor:%d port:%d bit:%d)"
180 " %2x -> %2x\n", minor, port, bit, curval, val);
182 outb_p(val, pc8736x_gpio_base + port_offset[port] + PORT_OUT);
184 curval = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_OUT);
185 val = inb_p(pc8736x_gpio_base + port_offset[port] + PORT_IN);
187 dev_dbg(&pdev->dev, "wrote %x, read: %x\n", curval, val);
188 pc8736x_gpio_shadow[port] = val;
189 }
191 static void pc8736x_gpio_set_high(unsigned index)
192 {
193 pc8736x_gpio_set(index, 1);
194 }
196 static void pc8736x_gpio_set_low(unsigned index)
197 {
198 pc8736x_gpio_set(index, 0);
199 }
201 static int pc8736x_gpio_current(unsigned minor)
202 {
203 int port, bit;
204 minor &= 0x1f;
205 port = minor >> 3;
206 bit = minor & 7;
207 return ((pc8736x_gpio_shadow[port] >> bit) & 0x01);
208 }
210 static void pc8736x_gpio_change(unsigned index)
211 {
212 pc8736x_gpio_set(index, !pc8736x_gpio_current(index));
213 }
215 static struct nsc_gpio_ops pc8736x_gpio_ops = {
216 .owner = THIS_MODULE,
217 .gpio_config = pc8736x_gpio_configure,
218 .gpio_dump = nsc_gpio_dump,
219 .gpio_get = pc8736x_gpio_get,
220 .gpio_set = pc8736x_gpio_set,
221 .gpio_change = pc8736x_gpio_change,
222 .gpio_current = pc8736x_gpio_current
223 };
225 static int pc8736x_gpio_open(struct inode *inode, struct file *file)
226 {
227 unsigned m = iminor(inode);
228 file->private_data = &pc8736x_gpio_ops;
230 dev_dbg(&pdev->dev, "open %d\n", m);
232 if (m >= PC8736X_GPIO_CT)
233 return -EINVAL;
234 return nonseekable_open(inode, file);
235 }
237 static const struct file_operations pc8736x_gpio_fileops = {
238 .owner = THIS_MODULE,
239 .open = pc8736x_gpio_open,
240 .write = nsc_gpio_write,
241 .read = nsc_gpio_read,
242 };
244 static void __init pc8736x_init_shadow(void)
245 {
246 int port;
248 /* read the current values driven on the GPIO signals */
249 for (port = 0; port < 4; ++port)
250 pc8736x_gpio_shadow[port]
251 = inb_p(pc8736x_gpio_base + port_offset[port]
252 + PORT_OUT);
254 }
256 static struct cdev pc8736x_gpio_cdev;
258 static int __init pc8736x_gpio_init(void)
259 {
260 int rc;
261 dev_t devid;
263 pdev = platform_device_alloc(DEVNAME, 0);
264 if (!pdev)
265 return -ENOMEM;
267 rc = platform_device_add(pdev);
268 if (rc) {
269 rc = -ENODEV;
270 goto undo_platform_dev_alloc;
271 }
272 dev_info(&pdev->dev, "NatSemi pc8736x GPIO Driver Initializing\n");
274 if (!pc8736x_superio_present()) {
275 rc = -ENODEV;
276 dev_err(&pdev->dev, "no device found\n");
277 goto undo_platform_dev_add;
278 }
279 pc8736x_gpio_ops.dev = &pdev->dev;
281 /* Verify that chip and it's GPIO unit are both enabled.
282 My BIOS does this, so I take minimum action here
283 */
284 rc = superio_inb(SIO_CF1);
285 if (!(rc & 0x01)) {
286 rc = -ENODEV;
287 dev_err(&pdev->dev, "device not enabled\n");
288 goto undo_platform_dev_add;
289 }
290 device_select(SIO_GPIO_UNIT);
291 if (!superio_inb(SIO_UNIT_ACT)) {
292 rc = -ENODEV;
293 dev_err(&pdev->dev, "GPIO unit not enabled\n");
294 goto undo_platform_dev_add;
295 }
297 /* read the GPIO unit base addr that chip responds to */
298 pc8736x_gpio_base = (superio_inb(SIO_BASE_HADDR) << 8
299 | superio_inb(SIO_BASE_LADDR));
301 if (!request_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE, DEVNAME)) {
302 rc = -ENODEV;
303 dev_err(&pdev->dev, "GPIO ioport %x busy\n",
304 pc8736x_gpio_base);
305 goto undo_platform_dev_add;
306 }
307 dev_info(&pdev->dev, "GPIO ioport %x reserved\n", pc8736x_gpio_base);
309 if (major) {
310 devid = MKDEV(major, 0);
311 rc = register_chrdev_region(devid, PC8736X_GPIO_CT, DEVNAME);
312 } else {
313 rc = alloc_chrdev_region(&devid, 0, PC8736X_GPIO_CT, DEVNAME);
314 major = MAJOR(devid);
315 }
317 if (rc < 0) {
318 dev_err(&pdev->dev, "register-chrdev failed: %d\n", rc);
319 goto undo_request_region;
320 }
321 if (!major) {
322 major = rc;
323 dev_dbg(&pdev->dev, "got dynamic major %d\n", major);
324 }
326 pc8736x_init_shadow();
328 /* ignore minor errs, and succeed */
329 cdev_init(&pc8736x_gpio_cdev, &pc8736x_gpio_fileops);
330 cdev_add(&pc8736x_gpio_cdev, devid, PC8736X_GPIO_CT);
332 return 0;
334 undo_request_region:
335 release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
336 undo_platform_dev_add:
337 platform_device_del(pdev);
338 undo_platform_dev_alloc:
339 platform_device_put(pdev);
341 return rc;
342 }
344 static void __exit pc8736x_gpio_cleanup(void)
345 {
346 dev_dbg(&pdev->dev, "cleanup\n");
348 cdev_del(&pc8736x_gpio_cdev);
349 unregister_chrdev_region(MKDEV(major,0), PC8736X_GPIO_CT);
350 release_region(pc8736x_gpio_base, PC8736X_GPIO_RANGE);
352 platform_device_del(pdev);
353 platform_device_put(pdev);
354 }
356 module_init(pc8736x_gpio_init);
357 module_exit(pc8736x_gpio_cleanup);