ia64/linux-2.6.18-xen.hg

view drivers/char/mwave/3780i.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
line source
1 /*
2 *
3 * 3780i.h -- declarations for 3780i.c
4 *
5 *
6 * Written By: Mike Sullivan IBM Corporation
7 *
8 * Copyright (C) 1999 IBM Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30 *
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 *
44 *
45 * 10/23/2000 - Alpha Release
46 * First release to the public
47 */
49 #ifndef _LINUX_3780I_H
50 #define _LINUX_3780I_H
52 #include <asm/io.h>
54 /* DSP I/O port offsets and definitions */
55 #define DSP_IsaSlaveControl 0x0000 /* ISA slave control register */
56 #define DSP_IsaSlaveStatus 0x0001 /* ISA slave status register */
57 #define DSP_ConfigAddress 0x0002 /* General config address register */
58 #define DSP_ConfigData 0x0003 /* General config data register */
59 #define DSP_HBridgeControl 0x0002 /* HBridge control register */
60 #define DSP_MsaAddrLow 0x0004 /* MSP System Address, low word */
61 #define DSP_MsaAddrHigh 0x0006 /* MSP System Address, high word */
62 #define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-store */
63 #define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
64 #define DSP_ReadAndClear 0x000C /* MSA read and clear data register */
65 #define DSP_Interrupt 0x000E /* Interrupt register (IPC source) */
67 typedef struct {
68 unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
71 unsigned char Reserved:5; /* 0: Reserved */
72 } DSP_ISA_SLAVE_CONTROL;
75 typedef struct {
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
80 unsigned short IsaPacingTimer:12; /* R: ISA access pacing timer: count of core cycles stolen */
81 } DSP_HBRIDGE_CONTROL;
84 /* DSP register indexes used with the configuration register address (index) register */
85 #define DSP_UartCfg1Index 0x0003 /* UART config register 1 */
86 #define DSP_UartCfg2Index 0x0004 /* UART config register 2 */
87 #define DSP_HBridgeCfg1Index 0x0007 /* HBridge config register 1 */
88 #define DSP_HBridgeCfg2Index 0x0008 /* HBridge config register 2 */
89 #define DSP_BusMasterCfg1Index 0x0009 /* ISA bus master config register 1 */
90 #define DSP_BusMasterCfg2Index 0x000A /* ISA bus master config register 2 */
91 #define DSP_IsaProtCfgIndex 0x000F /* ISA protocol control register */
92 #define DSP_PowerMgCfgIndex 0x0010 /* Low poser suspend/resume enable */
93 #define DSP_HBusTimerCfgIndex 0x0011 /* HBUS timer load value */
95 typedef struct {
96 unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
97 unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
98 unsigned char Irq:3; /* RW: IRQ selection */
99 unsigned char BaseIO:2; /* RW: Base I/O selection */
100 unsigned char Reserved:1; /* 0: Reserved */
101 } DSP_UART_CFG_1;
103 typedef struct {
104 unsigned char Enable:1; /* RW: Enable I/O and IRQ: 0=FALSE, 1=TRUE */
105 unsigned char Reserved:7; /* 0: Reserved */
106 } DSP_UART_CFG_2;
108 typedef struct {
109 unsigned char IrqActiveLow:1; /* RW: IRQ active high=0 or low=1 */
110 unsigned char IrqPulse:1; /* RW: IRQ pulse=1 or level=0 */
111 unsigned char Irq:3; /* RW: IRQ selection */
112 unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
113 unsigned char Reserved:2; /* 0: Reserved */
114 } DSP_HBRIDGE_CFG_1;
116 typedef struct {
117 unsigned char Enable:1; /* RW: enable I/O and IRQ: 0=FALSE, 1=TRUE */
118 unsigned char Reserved:7; /* 0: Reserved */
119 } DSP_HBRIDGE_CFG_2;
122 typedef struct {
123 unsigned char Dma:3; /* RW: DMA channel selection */
124 unsigned char NumTransfers:2; /* RW: Maximum # of transfers once being granted the ISA bus */
125 unsigned char ReRequest:2; /* RW: Minumum delay between releasing the ISA bus and requesting it again */
126 unsigned char MEMCS16:1; /* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
127 } DSP_BUSMASTER_CFG_1;
129 typedef struct {
130 unsigned char IsaMemCmdWidth:2; /* RW: ISA memory command width */
131 unsigned char Reserved:6; /* 0: Reserved */
132 } DSP_BUSMASTER_CFG_2;
135 typedef struct {
136 unsigned char GateIOCHRDY:1; /* RW: Enable IOCHRDY gating: 0=FALSE, 1=TRUE */
137 unsigned char Reserved:7; /* 0: Reserved */
138 } DSP_ISA_PROT_CFG;
140 typedef struct {
141 unsigned char Enable:1; /* RW: Enable low power suspend/resume 0=FALSE, 1=TRUE */
142 unsigned char Reserved:7; /* 0: Reserved */
143 } DSP_POWER_MGMT_CFG;
145 typedef struct {
146 unsigned char LoadValue:8; /* RW: HBUS timer load value */
147 } DSP_HBUS_TIMER_CFG;
151 /* DSP registers that exist in MSA I/O space */
152 #define DSP_ChipID 0x80000000
153 #define DSP_MspBootDomain 0x80000580
154 #define DSP_LBusTimeoutDisable 0x80000580
155 #define DSP_ClockControl_1 0x8000058A
156 #define DSP_ClockControl_2 0x8000058C
157 #define DSP_ChipReset 0x80000588
158 #define DSP_GpioModeControl_15_8 0x80000082
159 #define DSP_GpioDriverEnable_15_8 0x80000076
160 #define DSP_GpioOutputData_15_8 0x80000072
162 typedef struct {
163 unsigned short NMI:1; /* RW: non maskable interrupt */
164 unsigned short Halt:1; /* RW: Halt MSP clock */
165 unsigned short ResetCore:1; /* RW: Reset MSP core interface */
166 unsigned short Reserved:13; /* 0: Reserved */
167 } DSP_BOOT_DOMAIN;
169 typedef struct {
170 unsigned short DisableTimeout:1; /* RW: Disable LBus timeout */
171 unsigned short Reserved:15; /* 0: Reserved */
172 } DSP_LBUS_TIMEOUT_DISABLE;
174 typedef struct {
175 unsigned short Memory:1; /* RW: Reset memory interface */
176 unsigned short SerialPort1:1; /* RW: Reset serial port 1 interface */
177 unsigned short SerialPort2:1; /* RW: Reset serial port 2 interface */
178 unsigned short SerialPort3:1; /* RW: Reset serial port 3 interface */
179 unsigned short Gpio:1; /* RW: Reset GPIO interface */
180 unsigned short Dma:1; /* RW: Reset DMA interface */
181 unsigned short SoundBlaster:1; /* RW: Reset soundblaster interface */
182 unsigned short Uart:1; /* RW: Reset UART interface */
183 unsigned short Midi:1; /* RW: Reset MIDI interface */
184 unsigned short IsaMaster:1; /* RW: Reset ISA master interface */
185 unsigned short Reserved:6; /* 0: Reserved */
186 } DSP_CHIP_RESET;
188 typedef struct {
189 unsigned short N_Divisor:6; /* RW: (N) PLL output clock divisor */
190 unsigned short Reserved1:2; /* 0: reserved */
191 unsigned short M_Multiplier:6; /* RW: (M) PLL feedback clock multiplier */
192 unsigned short Reserved2:2; /* 0: reserved */
193 } DSP_CLOCK_CONTROL_1;
195 typedef struct {
196 unsigned short PllBypass:1; /* RW: PLL Bypass */
197 unsigned short Reserved:15; /* 0: Reserved */
198 } DSP_CLOCK_CONTROL_2;
200 typedef struct {
201 unsigned short Latch8:1;
202 unsigned short Latch9:1;
203 unsigned short Latch10:1;
204 unsigned short Latch11:1;
205 unsigned short Latch12:1;
206 unsigned short Latch13:1;
207 unsigned short Latch14:1;
208 unsigned short Latch15:1;
209 unsigned short Mask8:1;
210 unsigned short Mask9:1;
211 unsigned short Mask10:1;
212 unsigned short Mask11:1;
213 unsigned short Mask12:1;
214 unsigned short Mask13:1;
215 unsigned short Mask14:1;
216 unsigned short Mask15:1;
217 } DSP_GPIO_OUTPUT_DATA_15_8;
219 typedef struct {
220 unsigned short Enable8:1;
221 unsigned short Enable9:1;
222 unsigned short Enable10:1;
223 unsigned short Enable11:1;
224 unsigned short Enable12:1;
225 unsigned short Enable13:1;
226 unsigned short Enable14:1;
227 unsigned short Enable15:1;
228 unsigned short Mask8:1;
229 unsigned short Mask9:1;
230 unsigned short Mask10:1;
231 unsigned short Mask11:1;
232 unsigned short Mask12:1;
233 unsigned short Mask13:1;
234 unsigned short Mask14:1;
235 unsigned short Mask15:1;
236 } DSP_GPIO_DRIVER_ENABLE_15_8;
238 typedef struct {
239 unsigned short GpioMode8:2;
240 unsigned short GpioMode9:2;
241 unsigned short GpioMode10:2;
242 unsigned short GpioMode11:2;
243 unsigned short GpioMode12:2;
244 unsigned short GpioMode13:2;
245 unsigned short GpioMode14:2;
246 unsigned short GpioMode15:2;
247 } DSP_GPIO_MODE_15_8;
249 /* Component masks that are defined in dspmgr.h */
250 #define MW_ADC_MASK 0x0001
251 #define MW_AIC2_MASK 0x0006
252 #define MW_MIDI_MASK 0x0008
253 #define MW_CDDAC_MASK 0x8001
254 #define MW_AIC1_MASK 0xE006
255 #define MW_UART_MASK 0xE00A
256 #define MW_ACI_MASK 0xE00B
258 /*
259 * Definition of 3780i configuration structure. Unless otherwise stated,
260 * these values are provided as input to the 3780i support layer. At present,
261 * the only values maintained by the 3780i support layer are the saved UART
262 * registers.
263 */
264 typedef struct _DSP_3780I_CONFIG_SETTINGS {
266 /* Location of base configuration register */
267 unsigned short usBaseConfigIO;
269 /* Enables for various DSP components */
270 int bDSPEnabled;
271 int bModemEnabled;
272 int bInterruptClaimed;
274 /* IRQ, DMA, and Base I/O addresses for various DSP components */
275 unsigned short usDspIrq;
276 unsigned short usDspDma;
277 unsigned short usDspBaseIO;
278 unsigned short usUartIrq;
279 unsigned short usUartBaseIO;
281 /* IRQ modes for various DSP components */
282 int bDspIrqActiveLow;
283 int bUartIrqActiveLow;
284 int bDspIrqPulse;
285 int bUartIrqPulse;
287 /* Card abilities */
288 unsigned uIps;
289 unsigned uDStoreSize;
290 unsigned uIStoreSize;
291 unsigned uDmaBandwidth;
293 /* Adapter specific 3780i settings */
294 unsigned short usNumTransfers;
295 unsigned short usReRequest;
296 int bEnableMEMCS16;
297 unsigned short usIsaMemCmdWidth;
298 int bGateIOCHRDY;
299 int bEnablePwrMgmt;
300 unsigned short usHBusTimerLoadValue;
301 int bDisableLBusTimeout;
302 unsigned short usN_Divisor;
303 unsigned short usM_Multiplier;
304 int bPllBypass;
305 unsigned short usChipletEnable; /* Used with the chip reset register to enable specific chiplets */
307 /* Saved UART registers. These are maintained by the 3780i support layer. */
308 int bUartSaved; /* True after a successful save of the UART registers */
309 unsigned char ucIER; /* Interrupt enable register */
310 unsigned char ucFCR; /* FIFO control register */
311 unsigned char ucLCR; /* Line control register */
312 unsigned char ucMCR; /* Modem control register */
313 unsigned char ucSCR; /* Scratch register */
314 unsigned char ucDLL; /* Divisor latch, low byte */
315 unsigned char ucDLM; /* Divisor latch, high byte */
316 } DSP_3780I_CONFIG_SETTINGS;
319 /* 3780i support functions */
320 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
321 unsigned short *pIrqMap,
322 unsigned short *pDmaMap);
323 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings);
324 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings);
325 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings);
326 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
327 unsigned uCount, unsigned long ulDSPAddr);
328 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
329 void __user *pvBuffer, unsigned uCount,
330 unsigned long ulDSPAddr);
331 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
332 unsigned uCount, unsigned long ulDSPAddr);
333 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
334 unsigned uCount, unsigned long ulDSPAddr);
335 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
336 unsigned uCount, unsigned long ulDSPAddr);
337 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
338 unsigned long ulMsaAddr);
339 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
340 unsigned long ulMsaAddr, unsigned short usValue);
341 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
342 unsigned short *pusIPCSource);
344 /* I/O port access macros */
345 #define MKWORD(var) (*((unsigned short *)(&var)))
346 #define MKBYTE(var) (*((unsigned char *)(&var)))
348 #define WriteMsaCfg(addr,value) dsp3780I_WriteMsaCfg(usDspBaseIO,addr,value)
349 #define ReadMsaCfg(addr) dsp3780I_ReadMsaCfg(usDspBaseIO,addr)
350 #define WriteGenCfg(index,value) dsp3780I_WriteGenCfg(usDspBaseIO,index,value)
351 #define ReadGenCfg(index) dsp3780I_ReadGenCfg(usDspBaseIO,index)
353 #define InWordDsp(index) inw(usDspBaseIO+index)
354 #define InByteDsp(index) inb(usDspBaseIO+index)
355 #define OutWordDsp(index,value) outw(value,usDspBaseIO+index)
356 #define OutByteDsp(index,value) outb(value,usDspBaseIO+index)
358 #endif