ia64/linux-2.6.18-xen.hg

view arch/ia64/kernel/setup.c @ 708:e410857fd83c

Remove contiguous_bitmap[] as it's no longer needed.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Oct 22 14:55:29 2008 +0100 (2008-10-22)
parents c7ed6fe5dca0
children
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/pm.h>
45 #include <linux/cpufreq.h>
46 #include <linux/kexec.h>
47 #include <linux/crash_dump.h>
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #include <asm/system.h>
65 #ifdef CONFIG_XEN
66 #include <asm/hypervisor.h>
67 #include <asm/xen/xencomm.h>
68 #include <xen/xencons.h>
69 #endif
70 #include <linux/dma-mapping.h>
72 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
73 # error "struct cpuinfo_ia64 too big!"
74 #endif
76 #ifdef CONFIG_SMP
77 unsigned long __per_cpu_offset[NR_CPUS];
78 EXPORT_SYMBOL(__per_cpu_offset);
79 #endif
81 #ifdef CONFIG_XEN
82 static void
83 xen_panic_hypercall(struct unw_frame_info *info, void *arg)
84 {
85 current->thread.ksp = (__u64)info->sw - 16;
86 HYPERVISOR_shutdown(SHUTDOWN_crash);
87 /* we're never actually going to get here... */
88 }
90 static int
91 xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
92 {
93 unw_init_running(xen_panic_hypercall, NULL);
94 /* we're never actually going to get here... */
95 return NOTIFY_DONE;
96 }
98 static struct notifier_block xen_panic_block = {
99 xen_panic_event, NULL, 0 /* try to go last */
100 };
102 void xen_pm_power_off(void)
103 {
104 local_irq_disable();
105 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
106 }
107 #endif
109 extern void ia64_setup_printk_clock(void);
111 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
112 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
113 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
114 unsigned long ia64_cycles_per_usec;
115 struct ia64_boot_param *ia64_boot_param;
116 struct screen_info screen_info;
117 unsigned long vga_console_iobase;
118 unsigned long vga_console_membase;
120 static struct resource data_resource = {
121 .name = "Kernel data",
122 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
123 };
125 static struct resource code_resource = {
126 .name = "Kernel code",
127 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
128 };
129 extern void efi_initialize_iomem_resources(struct resource *,
130 struct resource *);
131 extern char _text[], _end[], _etext[];
133 unsigned long ia64_max_cacheline_size;
135 int dma_get_cache_alignment(void)
136 {
137 return ia64_max_cacheline_size;
138 }
139 EXPORT_SYMBOL(dma_get_cache_alignment);
141 unsigned long ia64_iobase; /* virtual address for I/O accesses */
142 EXPORT_SYMBOL(ia64_iobase);
143 struct io_space io_space[MAX_IO_SPACES];
144 EXPORT_SYMBOL(io_space);
145 unsigned int num_io_spaces;
147 /*
148 * "flush_icache_range()" needs to know what processor dependent stride size to use
149 * when it makes i-cache(s) coherent with d-caches.
150 */
151 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
152 unsigned long ia64_i_cache_stride_shift = ~0;
154 /*
155 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
156 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
157 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
158 * address of the second buffer must be aligned to (merge_mask+1) in order to be
159 * mergeable). By default, we assume there is no I/O MMU which can merge physically
160 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
161 * page-size of 2^64.
162 */
163 unsigned long ia64_max_iommu_merge_mask = ~0UL;
164 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
166 /*
167 * We use a special marker for the end of memory and it uses the extra (+1) slot
168 */
169 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
170 int num_rsvd_regions __initdata;
173 /*
174 * Filter incoming memory segments based on the primitive map created from the boot
175 * parameters. Segments contained in the map are removed from the memory ranges. A
176 * caller-specified function is called with the memory ranges that remain after filtering.
177 * This routine does not assume the incoming segments are sorted.
178 */
179 int __init
180 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
181 {
182 unsigned long range_start, range_end, prev_start;
183 void (*func)(unsigned long, unsigned long, int);
184 int i;
186 #if IGNORE_PFN0
187 if (start == PAGE_OFFSET) {
188 printk(KERN_WARNING "warning: skipping physical page 0\n");
189 start += PAGE_SIZE;
190 if (start >= end) return 0;
191 }
192 #endif
193 /*
194 * lowest possible address(walker uses virtual)
195 */
196 prev_start = PAGE_OFFSET;
197 func = arg;
199 for (i = 0; i < num_rsvd_regions; ++i) {
200 range_start = max(start, prev_start);
201 range_end = min(end, rsvd_region[i].start);
203 if (range_start < range_end)
204 call_pernode_memory(__pa(range_start), range_end - range_start, func);
206 /* nothing more available in this segment */
207 if (range_end == end) return 0;
209 prev_start = rsvd_region[i].end;
210 }
211 /* end of memory marker allows full processing inside loop body */
212 return 0;
213 }
215 static void __init
216 sort_regions (struct rsvd_region *rsvd_region, int max)
217 {
218 int j;
220 /* simple bubble sorting */
221 while (max--) {
222 for (j = 0; j < max; ++j) {
223 if (rsvd_region[j].start > rsvd_region[j+1].start) {
224 struct rsvd_region tmp;
225 tmp = rsvd_region[j];
226 rsvd_region[j] = rsvd_region[j + 1];
227 rsvd_region[j + 1] = tmp;
228 }
229 }
230 }
231 }
233 /*
234 * Request address space for all standard resources
235 */
236 static int __init register_memory(void)
237 {
238 code_resource.start = ia64_tpa(_text);
239 code_resource.end = ia64_tpa(_etext) - 1;
240 data_resource.start = ia64_tpa(_etext);
241 data_resource.end = ia64_tpa(_end) - 1;
242 efi_initialize_iomem_resources(&code_resource, &data_resource);
244 return 0;
245 }
247 __initcall(register_memory);
249 /**
250 * reserve_memory - setup reserved memory areas
251 *
252 * Setup the reserved memory areas set aside for the boot parameters,
253 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
254 * see include/asm-ia64/meminit.h if you need to define more.
255 */
256 void __init
257 reserve_memory (void)
258 {
259 int n = 0;
261 /*
262 * none of the entries in this table overlap
263 */
264 rsvd_region[n].start = (unsigned long) ia64_boot_param;
265 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
266 n++;
268 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
269 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
270 n++;
272 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
273 rsvd_region[n].end = (rsvd_region[n].start
274 + strlen(__va(ia64_boot_param->command_line)) + 1);
275 n++;
277 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
278 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
279 n++;
281 #ifdef CONFIG_XEN
282 if (is_running_on_xen()) {
283 rsvd_region[n].start = (unsigned long)__va((HYPERVISOR_shared_info->arch.start_info_pfn << PAGE_SHIFT));
284 rsvd_region[n].end = rsvd_region[n].start + PAGE_SIZE;
285 n++;
286 }
287 #endif
289 #ifdef CONFIG_BLK_DEV_INITRD
290 if (ia64_boot_param->initrd_start) {
291 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
292 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
293 n++;
294 }
295 #endif
297 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
298 n++;
300 #ifdef CONFIG_KEXEC
301 /* crashkernel=size@offset specifies the size to reserve for a crash
302 * kernel. If offset is 0, then it is determined automatically.
303 * By reserving this memory we guarantee that linux never set's it
304 * up as a DMA target.Useful for holding code to do something
305 * appropriate after a kernel panic.
306 */
307 {
308 char *from = strstr(saved_command_line, "crashkernel=");
309 unsigned long base, size;
310 #ifdef CONFIG_XEN
311 if (is_initial_xendomain() && from)
312 printk("Ignoring crashkernel command line, "
313 "parameter will be supplied by xen\n");
314 else {
315 #endif
316 if (from) {
317 size = memparse(from + 12, &from);
318 if (*from == '@')
319 base = memparse(from+1, &from);
320 else
321 base = 0;
322 if (size) {
323 if (!base) {
324 sort_regions(rsvd_region, n);
325 base = kdump_find_rsvd_region(size,
326 rsvd_region, n);
327 }
328 if (base != ~0UL) {
329 rsvd_region[n].start =
330 (unsigned long)__va(base);
331 rsvd_region[n].end =
332 (unsigned long)__va(base + size);
333 n++;
334 crashk_res.start = base;
335 crashk_res.end = base + size - 1;
336 }
337 }
338 }
339 efi_memmap_res.start = ia64_boot_param->efi_memmap;
340 efi_memmap_res.end = efi_memmap_res.start +
341 ia64_boot_param->efi_memmap_size;
342 boot_param_res.start = kexec_virt_to_phys(ia64_boot_param);
343 boot_param_res.end = boot_param_res.start +
344 sizeof(*ia64_boot_param);
345 #ifdef CONFIG_XEN
346 }
347 #endif
348 }
349 #endif
350 /* end of memory marker */
351 rsvd_region[n].start = ~0UL;
352 rsvd_region[n].end = ~0UL;
353 n++;
355 num_rsvd_regions = n;
356 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
358 sort_regions(rsvd_region, num_rsvd_regions);
359 }
362 /**
363 * find_initrd - get initrd parameters from the boot parameter structure
364 *
365 * Grab the initrd start and end from the boot parameter struct given us by
366 * the boot loader.
367 */
368 void __init
369 find_initrd (void)
370 {
371 #ifdef CONFIG_BLK_DEV_INITRD
372 if (ia64_boot_param->initrd_start) {
373 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
374 initrd_end = initrd_start+ia64_boot_param->initrd_size;
376 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
377 initrd_start, ia64_boot_param->initrd_size);
378 }
379 #endif
380 }
382 static void __init
383 io_port_init (void)
384 {
385 unsigned long phys_iobase;
387 /*
388 * Set `iobase' based on the EFI memory map or, failing that, the
389 * value firmware left in ar.k0.
390 *
391 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
392 * the port's virtual address, so ia32_load_state() loads it with a
393 * user virtual address. But in ia64 mode, glibc uses the
394 * *physical* address in ar.k0 to mmap the appropriate area from
395 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
396 * cases, user-mode can only use the legacy 0-64K I/O port space.
397 *
398 * ar.k0 is not involved in kernel I/O port accesses, which can use
399 * any of the I/O port spaces and are done via MMIO using the
400 * virtual mmio_base from the appropriate io_space[].
401 */
402 phys_iobase = efi_get_iobase();
403 if (!phys_iobase) {
404 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
405 printk(KERN_INFO "No I/O port range found in EFI memory map, "
406 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
407 }
408 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
409 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
411 /* setup legacy IO port space */
412 io_space[0].mmio_base = ia64_iobase;
413 io_space[0].sparse = 1;
414 num_io_spaces = 1;
415 }
417 /**
418 * early_console_setup - setup debugging console
419 *
420 * Consoles started here require little enough setup that we can start using
421 * them very early in the boot process, either right after the machine
422 * vector initialization, or even before if the drivers can detect their hw.
423 *
424 * Returns non-zero if a console couldn't be setup.
425 */
426 static inline int __init
427 early_console_setup (char *cmdline)
428 {
429 int earlycons = 0;
431 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
432 {
433 extern int sn_serial_console_early_setup(void);
434 if (!sn_serial_console_early_setup())
435 earlycons++;
436 }
437 #endif
438 #ifdef CONFIG_EFI_PCDP
439 if (!efi_setup_pcdp_console(cmdline))
440 earlycons++;
441 #endif
442 #ifdef CONFIG_SERIAL_8250_CONSOLE
443 if (!early_serial_console_init(cmdline))
444 earlycons++;
445 #endif
447 return (earlycons) ? 0 : -1;
448 }
450 static inline void
451 mark_bsp_online (void)
452 {
453 #ifdef CONFIG_SMP
454 /* If we register an early console, allow CPU 0 to printk */
455 cpu_set(smp_processor_id(), cpu_online_map);
456 #endif
457 }
459 #ifdef CONFIG_SMP
460 static void __init
461 check_for_logical_procs (void)
462 {
463 pal_logical_to_physical_t info;
464 s64 status;
466 status = ia64_pal_logical_to_phys(0, &info);
467 if (status == -1) {
468 printk(KERN_INFO "No logical to physical processor mapping "
469 "available\n");
470 return;
471 }
472 if (status) {
473 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
474 status);
475 return;
476 }
477 /*
478 * Total number of siblings that BSP has. Though not all of them
479 * may have booted successfully. The correct number of siblings
480 * booted is in info.overview_num_log.
481 */
482 smp_num_siblings = info.overview_tpc;
483 smp_num_cpucores = info.overview_cpp;
484 }
485 #endif
487 static __initdata int nomca;
488 static __init int setup_nomca(char *s)
489 {
490 nomca = 1;
491 return 0;
492 }
493 early_param("nomca", setup_nomca);
495 #ifdef CONFIG_PROC_VMCORE
496 /* elfcorehdr= specifies the location of elf core header
497 * stored by the crashed kernel.
498 */
499 static int __init parse_elfcorehdr(char *arg)
500 {
501 if (!arg)
502 return -EINVAL;
504 elfcorehdr_addr = memparse(arg, &arg);
505 return 0;
506 }
507 early_param("elfcorehdr", parse_elfcorehdr);
508 #endif /* CONFIG_PROC_VMCORE */
510 void __init
511 setup_arch (char **cmdline_p)
512 {
513 #ifdef CONFIG_XEN
514 shared_info_t *s = NULL;
515 if (is_running_on_xen()) {
516 s = HYPERVISOR_shared_info;
517 xen_start_info = __va(s->arch.start_info_pfn << PAGE_SHIFT);
518 }
519 #endif
521 unw_init();
523 #ifdef CONFIG_XEN
524 if (is_running_on_xen()) {
525 /* Must be done before any hypercall. */
526 xencomm_initialize();
528 setup_xen_features();
529 /* Register a call for panic conditions. */
530 atomic_notifier_chain_register(&panic_notifier_list,
531 &xen_panic_block);
532 pm_power_off = xen_pm_power_off;
534 xen_ia64_enable_opt_feature();
535 }
536 #endif
538 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
540 *cmdline_p = __va(ia64_boot_param->command_line);
541 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
543 efi_init();
544 io_port_init();
546 parse_early_param();
548 #ifdef CONFIG_IA64_GENERIC
549 machvec_init(NULL);
550 #endif
552 if (early_console_setup(*cmdline_p) == 0)
553 mark_bsp_online();
555 #ifdef CONFIG_ACPI
556 /* Initialize the ACPI boot-time table parser */
557 acpi_table_init();
558 # ifdef CONFIG_ACPI_NUMA
559 acpi_numa_init();
560 # endif
561 #else
562 # ifdef CONFIG_SMP
563 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
564 # endif
565 #endif /* CONFIG_APCI_BOOT */
567 find_memory();
569 /* process SAL system table: */
570 ia64_sal_init(__va(efi.sal_systab));
572 ia64_setup_printk_clock();
574 #ifdef CONFIG_SMP
575 cpu_physical_id(0) = hard_smp_processor_id();
577 cpu_set(0, cpu_sibling_map[0]);
578 cpu_set(0, cpu_core_map[0]);
580 check_for_logical_procs();
581 if (smp_num_cpucores > 1)
582 printk(KERN_INFO
583 "cpu package is Multi-Core capable: number of cores=%d\n",
584 smp_num_cpucores);
585 if (smp_num_siblings > 1)
586 printk(KERN_INFO
587 "cpu package is Multi-Threading capable: number of siblings=%d\n",
588 smp_num_siblings);
589 #endif
591 cpu_init(); /* initialize the bootstrap CPU */
592 mmu_context_init(); /* initialize context_id bitmap */
594 #ifdef CONFIG_ACPI
595 acpi_boot_init();
596 #endif
598 #ifdef CONFIG_XEN
599 if (is_running_on_xen()) {
600 printk("Running on Xen! start_info_pfn=0x%lx nr_pages=%ld "
601 "flags=0x%x\n", s->arch.start_info_pfn,
602 xen_start_info->nr_pages, xen_start_info->flags);
604 /*
605 * If a console= is NOT specified, we assume using the
606 * xencons console is desired. By default, this is xvc0
607 * for both dom0 and domU.
608 */
609 if (!strstr(*cmdline_p, "console=")) {
610 char *p, *q, name[5] = "xvc";
611 int offset = 0;
613 #if defined(CONFIG_VGA_CONSOLE)
614 /*
615 * conswitchp might be set intelligently from the
616 * PCDP code. If set to VGA console, use it.
617 */
618 if (is_initial_xendomain() && conswitchp == &vga_con)
619 strncpy(name, "tty", 3);
620 #endif
622 p = strstr(*cmdline_p, "xencons=");
624 if (p) {
625 p += 8;
626 if (!strncmp(p, "ttyS", 4)) {
627 strncpy(name, p, 4);
628 p += 4;
629 offset = simple_strtol(p, &q, 10);
630 if (p == q)
631 offset = 0;
632 } else if (!strncmp(p, "tty", 3) ||
633 !strncmp(p, "xvc", 3)) {
634 strncpy(name, p, 3);
635 p += 3;
636 offset = simple_strtol(p, &q, 10);
637 if (p == q)
638 offset = 0;
639 } else if (!strncmp(p, "off", 3))
640 offset = -1;
641 }
643 if (offset >= 0)
644 add_preferred_console(name, offset, NULL);
645 }
646 }
647 #endif
649 #ifdef CONFIG_VT
650 if (!conswitchp) {
651 # if defined(CONFIG_DUMMY_CONSOLE)
652 conswitchp = &dummy_con;
653 # endif
654 # if defined(CONFIG_VGA_CONSOLE)
655 /*
656 * Non-legacy systems may route legacy VGA MMIO range to system
657 * memory. vga_con probes the MMIO hole, so memory looks like
658 * a VGA device to it. The EFI memory map can tell us if it's
659 * memory so we can avoid this problem.
660 */
661 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
662 conswitchp = &vga_con;
663 # endif
664 }
665 #endif
667 /* enable IA-64 Machine Check Abort Handling unless disabled */
668 #ifdef CONFIG_XEN
669 if (is_running_on_xen() && !is_initial_xendomain()) {
670 nomca = 1;
671 #if !defined(CONFIG_VT) || !defined(CONFIG_DUMMY_CONSOLE)
672 conswitchp = NULL;
673 #endif
674 }
675 #endif
676 if (!nomca)
677 ia64_mca_init();
679 platform_setup(cmdline_p);
680 #ifdef CONFIG_XEN
681 if (is_running_on_xen() && !ia64_platform_is("xen")) {
682 extern ia64_mv_setup_t xen_setup;
683 xen_setup(cmdline_p);
684 }
685 #endif
686 paging_init();
687 }
689 /*
690 * Display cpu info for all cpu's.
691 */
692 static int
693 show_cpuinfo (struct seq_file *m, void *v)
694 {
695 #ifdef CONFIG_SMP
696 # define lpj c->loops_per_jiffy
697 # define cpunum c->cpu
698 #else
699 # define lpj loops_per_jiffy
700 # define cpunum 0
701 #endif
702 static struct {
703 unsigned long mask;
704 const char *feature_name;
705 } feature_bits[] = {
706 { 1UL << 0, "branchlong" },
707 { 1UL << 1, "spontaneous deferral"},
708 { 1UL << 2, "16-byte atomic ops" }
709 };
710 char family[32], features[128], *cp, sep;
711 struct cpuinfo_ia64 *c = v;
712 unsigned long mask;
713 unsigned long proc_freq;
714 int i;
716 mask = c->features;
718 switch (c->family) {
719 case 0x07: memcpy(family, "Itanium", 8); break;
720 case 0x1f: memcpy(family, "Itanium 2", 10); break;
721 default: sprintf(family, "%u", c->family); break;
722 }
724 /* build the feature string: */
725 memcpy(features, " standard", 10);
726 cp = features;
727 sep = 0;
728 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
729 if (mask & feature_bits[i].mask) {
730 if (sep)
731 *cp++ = sep;
732 sep = ',';
733 *cp++ = ' ';
734 strcpy(cp, feature_bits[i].feature_name);
735 cp += strlen(feature_bits[i].feature_name);
736 mask &= ~feature_bits[i].mask;
737 }
738 }
739 if (mask) {
740 /* print unknown features as a hex value: */
741 if (sep)
742 *cp++ = sep;
743 sprintf(cp, " 0x%lx", mask);
744 }
746 proc_freq = cpufreq_quick_get(cpunum);
747 if (!proc_freq)
748 proc_freq = c->proc_freq / 1000;
750 seq_printf(m,
751 "processor : %d\n"
752 "vendor : %s\n"
753 "arch : IA-64\n"
754 "family : %s\n"
755 "model : %u\n"
756 "revision : %u\n"
757 "archrev : %u\n"
758 "features :%s\n" /* don't change this---it _is_ right! */
759 "cpu number : %lu\n"
760 "cpu regs : %u\n"
761 "cpu MHz : %lu.%06lu\n"
762 "itc MHz : %lu.%06lu\n"
763 "BogoMIPS : %lu.%02lu\n",
764 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
765 features, c->ppn, c->number,
766 proc_freq / 1000, proc_freq % 1000,
767 c->itc_freq / 1000000, c->itc_freq % 1000000,
768 lpj*HZ/500000, (lpj*HZ/5000) % 100);
769 #ifdef CONFIG_SMP
770 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
771 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
772 seq_printf(m,
773 "physical id: %u\n"
774 "core id : %u\n"
775 "thread id : %u\n",
776 c->socket_id, c->core_id, c->thread_id);
777 #endif
778 seq_printf(m,"\n");
780 return 0;
781 }
783 static void *
784 c_start (struct seq_file *m, loff_t *pos)
785 {
786 #ifdef CONFIG_SMP
787 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
788 ++*pos;
789 #endif
790 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
791 }
793 static void *
794 c_next (struct seq_file *m, void *v, loff_t *pos)
795 {
796 ++*pos;
797 return c_start(m, pos);
798 }
800 static void
801 c_stop (struct seq_file *m, void *v)
802 {
803 }
805 struct seq_operations cpuinfo_op = {
806 .start = c_start,
807 .next = c_next,
808 .stop = c_stop,
809 .show = show_cpuinfo
810 };
812 static void __cpuinit
813 identify_cpu (struct cpuinfo_ia64 *c)
814 {
815 union {
816 unsigned long bits[5];
817 struct {
818 /* id 0 & 1: */
819 char vendor[16];
821 /* id 2 */
822 u64 ppn; /* processor serial number */
824 /* id 3: */
825 unsigned number : 8;
826 unsigned revision : 8;
827 unsigned model : 8;
828 unsigned family : 8;
829 unsigned archrev : 8;
830 unsigned reserved : 24;
832 /* id 4: */
833 u64 features;
834 } field;
835 } cpuid;
836 pal_vm_info_1_u_t vm1;
837 pal_vm_info_2_u_t vm2;
838 pal_status_t status;
839 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
840 int i;
842 for (i = 0; i < 5; ++i)
843 cpuid.bits[i] = ia64_get_cpuid(i);
845 memcpy(c->vendor, cpuid.field.vendor, 16);
846 #ifdef CONFIG_SMP
847 c->cpu = smp_processor_id();
849 /* below default values will be overwritten by identify_siblings()
850 * for Multi-Threading/Multi-Core capable cpu's
851 */
852 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
853 c->socket_id = -1;
855 identify_siblings(c);
856 #endif
857 c->ppn = cpuid.field.ppn;
858 c->number = cpuid.field.number;
859 c->revision = cpuid.field.revision;
860 c->model = cpuid.field.model;
861 c->family = cpuid.field.family;
862 c->archrev = cpuid.field.archrev;
863 c->features = cpuid.field.features;
865 status = ia64_pal_vm_summary(&vm1, &vm2);
866 if (status == PAL_STATUS_SUCCESS) {
867 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
868 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
869 }
870 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
871 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
872 }
874 void
875 setup_per_cpu_areas (void)
876 {
877 /* start_kernel() requires this... */
878 #ifdef CONFIG_ACPI_HOTPLUG_CPU
879 prefill_possible_map();
880 #endif
881 }
883 /*
884 * Calculate the max. cache line size.
885 *
886 * In addition, the minimum of the i-cache stride sizes is calculated for
887 * "flush_icache_range()".
888 */
889 static void __cpuinit
890 get_max_cacheline_size (void)
891 {
892 unsigned long line_size, max = 1;
893 unsigned int cache_size = 0;
894 u64 l, levels, unique_caches;
895 pal_cache_config_info_t cci;
896 s64 status;
898 status = ia64_pal_cache_summary(&levels, &unique_caches);
899 if (status != 0) {
900 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
901 __FUNCTION__, status);
902 max = SMP_CACHE_BYTES;
903 /* Safest setup for "flush_icache_range()" */
904 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
905 goto out;
906 }
908 for (l = 0; l < levels; ++l) {
909 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
910 &cci);
911 if (status != 0) {
912 printk(KERN_ERR
913 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
914 __FUNCTION__, l, status);
915 max = SMP_CACHE_BYTES;
916 /* The safest setup for "flush_icache_range()" */
917 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
918 cci.pcci_unified = 1;
919 }
920 line_size = 1 << cci.pcci_line_size;
921 if (line_size > max)
922 max = line_size;
923 if (cache_size < cci.pcci_cache_size)
924 cache_size = cci.pcci_cache_size;
925 if (!cci.pcci_unified) {
926 status = ia64_pal_cache_config_info(l,
927 /* cache_type (instruction)= */ 1,
928 &cci);
929 if (status != 0) {
930 printk(KERN_ERR
931 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
932 __FUNCTION__, l, status);
933 /* The safest setup for "flush_icache_range()" */
934 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
935 }
936 }
937 if (cci.pcci_stride < ia64_i_cache_stride_shift)
938 ia64_i_cache_stride_shift = cci.pcci_stride;
939 }
940 out:
941 #ifdef CONFIG_SMP
942 max_cache_size = max(max_cache_size, cache_size);
943 #endif
944 if (max > ia64_max_cacheline_size)
945 ia64_max_cacheline_size = max;
946 }
948 /*
949 * cpu_init() initializes state that is per-CPU. This function acts
950 * as a 'CPU state barrier', nothing should get across.
951 */
952 void __cpuinit
953 cpu_init (void)
954 {
955 extern void __cpuinit ia64_mmu_init (void *);
956 unsigned long num_phys_stacked;
957 pal_vm_info_2_u_t vmi;
958 unsigned int max_ctx;
959 struct cpuinfo_ia64 *cpu_info;
960 void *cpu_data;
962 cpu_data = per_cpu_init();
964 /*
965 * We set ar.k3 so that assembly code in MCA handler can compute
966 * physical addresses of per cpu variables with a simple:
967 * phys = ar.k3 + &per_cpu_var
968 */
969 ia64_set_kr(IA64_KR_PER_CPU_DATA,
970 ia64_tpa(cpu_data) - (long) __per_cpu_start);
972 get_max_cacheline_size();
974 /*
975 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
976 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
977 * depends on the data returned by identify_cpu(). We break the dependency by
978 * accessing cpu_data() through the canonical per-CPU address.
979 */
980 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
981 identify_cpu(cpu_info);
983 #ifdef CONFIG_MCKINLEY
984 {
985 # define FEATURE_SET 16
986 struct ia64_pal_retval iprv;
988 if (cpu_info->family == 0x1f) {
989 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
990 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
991 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
992 (iprv.v1 | 0x80), FEATURE_SET, 0);
993 }
994 }
995 #endif
997 /* Clear the stack memory reserved for pt_regs: */
998 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
1000 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
1002 /*
1003 * Initialize the page-table base register to a global
1004 * directory with all zeroes. This ensure that we can handle
1005 * TLB-misses to user address-space even before we created the
1006 * first user address-space. This may happen, e.g., due to
1007 * aggressive use of lfetch.fault.
1008 */
1009 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
1011 /*
1012 * Initialize default control register to defer speculative faults except
1013 * for those arising from TLB misses, which are not deferred. The
1014 * kernel MUST NOT depend on a particular setting of these bits (in other words,
1015 * the kernel must have recovery code for all speculative accesses). Turn on
1016 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
1017 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
1018 * be fine).
1019 */
1020 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
1021 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
1022 atomic_inc(&init_mm.mm_count);
1023 current->active_mm = &init_mm;
1024 if (current->mm)
1025 BUG();
1027 ia64_mmu_init(ia64_imva(cpu_data));
1028 ia64_mca_cpu_init(ia64_imva(cpu_data));
1030 #ifdef CONFIG_IA32_SUPPORT
1031 ia32_cpu_init();
1032 #endif
1034 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
1035 ia64_set_itc(0);
1037 /* disable all local interrupt sources: */
1038 ia64_set_itv(1 << 16);
1039 ia64_set_lrr0(1 << 16);
1040 ia64_set_lrr1(1 << 16);
1041 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
1042 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
1044 /* clear TPR & XTP to enable all interrupt classes: */
1045 ia64_setreg(_IA64_REG_CR_TPR, 0);
1046 #ifdef CONFIG_SMP
1047 normal_xtp();
1048 #endif
1050 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
1051 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
1052 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
1053 else {
1054 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
1055 max_ctx = (1U << 15) - 1; /* use architected minimum */
1057 while (max_ctx < ia64_ctx.max_ctx) {
1058 unsigned int old = ia64_ctx.max_ctx;
1059 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
1060 break;
1063 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
1064 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
1065 "stacked regs\n");
1066 num_phys_stacked = 96;
1068 /* size of physical stacked register partition plus 8 bytes: */
1069 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
1070 platform_cpu_init();
1071 #ifdef CONFIG_XEN
1072 if (is_running_on_xen() && !ia64_platform_is("xen")) {
1073 extern ia64_mv_cpu_init_t xen_cpu_init;
1074 xen_cpu_init();
1076 #endif
1078 pm_idle = default_idle;
1081 /*
1082 * On SMP systems, when the scheduler does migration-cost autodetection,
1083 * it needs a way to flush as much of the CPU's caches as possible.
1084 */
1085 void sched_cacheflush(void)
1087 ia64_sal_cache_flush(3);
1090 void __init
1091 check_bugs (void)
1093 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1094 (unsigned long) __end___mckinley_e9_bundles);
1097 static int __init run_dmi_scan(void)
1099 dmi_scan_machine();
1100 return 0;
1102 core_initcall(run_dmi_scan);