ia64/linux-2.6.18-xen.hg

view include/asm-v850/v850e_timer_c.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-v850/v850e_timer_c.h -- `Timer C' component often used
3 * with the V850E cpu core
4 *
5 * Copyright (C) 2001,03 NEC Electronics Corporation
6 * Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 *
12 * Written by Miles Bader <miles@gnu.org>
13 */
15 /* NOTE: this include file currently contains only enough to allow us to
16 use timer C as an interrupt pass-through. */
18 #ifndef __V850_V850E_TIMER_C_H__
19 #define __V850_V850E_TIMER_C_H__
21 #include <asm/types.h>
22 #include <asm/machdep.h> /* Pick up chip-specific defs. */
25 /* Timer C (16-bit interval timers). */
27 /* Control register 0 for timer C. */
28 #define V850E_TIMER_C_TMCC0_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x6 + 0x10 *(n))
29 #define V850E_TIMER_C_TMCC0(n) (*(volatile u8 *)V850E_TIMER_C_TMCC0_ADDR(n))
30 #define V850E_TIMER_C_TMCC0_CAE 0x01 /* clock action enable */
31 #define V850E_TIMER_C_TMCC0_CE 0x02 /* count enable */
32 /* ... */
34 /* Control register 1 for timer C. */
35 #define V850E_TIMER_C_TMCC1_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x8 + 0x10 *(n))
36 #define V850E_TIMER_C_TMCC1(n) (*(volatile u8 *)V850E_TIMER_C_TMCC1_ADDR(n))
37 #define V850E_TIMER_C_TMCC1_CMS0 0x01 /* capture/compare mode select (ccc0) */
38 #define V850E_TIMER_C_TMCC1_CMS1 0x02 /* capture/compare mode select (ccc1) */
39 /* ... */
41 /* Interrupt edge-sensitivity control for timer C. */
42 #define V850E_TIMER_C_SESC_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x9 + 0x10 *(n))
43 #define V850E_TIMER_C_SESC(n) (*(volatile u8 *)V850E_TIMER_C_SESC_ADDR(n))
45 /* ...etc... */
48 #endif /* __V850_V850E_TIMER_C_H__ */