ia64/linux-2.6.18-xen.hg

view include/asm-v850/v850e2_cache.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
3 * cache memories
4 *
5 * Copyright (C) 2003,05 NEC Electronics Corporation
6 * Copyright (C) 2003,05 Miles Bader <miles@gnu.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 *
12 * Written by Miles Bader <miles@gnu.org>
13 */
15 #ifndef __V850_V850E2_CACHE_H__
16 #define __V850_V850E2_CACHE_H__
18 #include <asm/types.h>
21 /* Cache control registers. */
23 /* Bus Transaction Control */
24 #define V850E2_CACHE_BTSC_ADDR 0xFFFFF070
25 #define V850E2_CACHE_BTSC (*(volatile u16 *)V850E2_CACHE_BTSC_ADDR)
26 #define V850E2_CACHE_BTSC_ICM 0x0001 /* icache enable */
27 #define V850E2_CACHE_BTSC_DCM0 0x0004 /* dcache enable, bit 0 */
28 #define V850E2_CACHE_BTSC_DCM1 0x0008 /* dcache enable, bit 1 */
29 #define V850E2_CACHE_BTSC_DCM_WT /* write-through */ \
30 V850E2_CACHE_BTSC_DCM0
31 #ifdef CONFIG_V850E2_V850E2S
32 # define V850E2_CACHE_BTSC_DCM_WB_NO_ALLOC /* write-back, non-alloc */ \
33 V850E2_CACHE_BTSC_DCM1
34 # define V850E2_CACHE_BTSC_DCM_WB_ALLOC /* write-back, non-alloc */ \
35 (V850E2_CACHE_BTSC_DCM1 | V850E2_CACHE_BTSC_DCM0)
36 # define V850E2_CACHE_BTSC_ISEQ 0x0010 /* icache `address sequence mode' */
37 # define V850E2_CACHE_BTSC_DSEQ 0x0020 /* dcache `address sequence mode' */
38 # define V850E2_CACHE_BTSC_IRFC 0x0030
39 # define V850E2_CACHE_BTSC_ILCD 0x4000
40 # define V850E2_CACHE_BTSC_VABE 0x8000
41 #endif /* CONFIG_V850E2_V850E2S */
43 /* Cache operation start address register (low-bits). */
44 #define V850E2_CACHE_CADL_ADDR 0xFFFFF074
45 #define V850E2_CACHE_CADL (*(volatile u16 *)V850E2_CACHE_CADL_ADDR)
46 /* Cache operation start address register (high-bits). */
47 #define V850E2_CACHE_CADH_ADDR 0xFFFFF076
48 #define V850E2_CACHE_CADH (*(volatile u16 *)V850E2_CACHE_CADH_ADDR)
49 /* Cache operation count register. */
50 #define V850E2_CACHE_CCNT_ADDR 0xFFFFF078
51 #define V850E2_CACHE_CCNT (*(volatile u16 *)V850E2_CACHE_CCNT_ADDR)
52 /* Cache operation specification register. */
53 #define V850E2_CACHE_COPR_ADDR 0xFFFFF07A
54 #define V850E2_CACHE_COPR (*(volatile u16 *)V850E2_CACHE_COPR_ADDR)
55 #define V850E2_CACHE_COPR_STRT 0x0001 /* start cache operation */
56 #define V850E2_CACHE_COPR_LBSL 0x0100 /* 0 = icache, 1 = dcache */
57 #define V850E2_CACHE_COPR_WSLE 0x0200 /* operate on cache way */
58 #define V850E2_CACHE_COPR_WSL(way) ((way) * 0x0400) /* way select */
59 #define V850E2_CACHE_COPR_CFC(op) ((op) * 0x1000) /* cache function code */
62 /* Size of a cache line in bytes. */
63 #define V850E2_CACHE_LINE_SIZE_BITS 4
64 #define V850E2_CACHE_LINE_SIZE (1 << V850E2_CACHE_LINE_SIZE_BITS)
66 /* The size of each cache `way' in lines. */
67 #define V850E2_CACHE_WAY_SIZE 256
70 /* For <asm/cache.h> */
71 #define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE
72 #define L1_CACHE_SHIFT V850E2_CACHE_LINE_SIZE_BITS
75 #endif /* __V850_V850E2_CACHE_H__ */