ia64/linux-2.6.18-xen.hg

view include/asm-v850/fpga85e2c.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-v850/fpga85e2c.h -- Machine-dependent defs for
3 * FPGA implementation of V850E2/NA85E2C
4 *
5 * Copyright (C) 2002,03 NEC Electronics Corporation
6 * Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 *
12 * Written by Miles Bader <miles@gnu.org>
13 */
15 #ifndef __V850_FPGA85E2C_H__
16 #define __V850_FPGA85E2C_H__
18 #include <asm/v850e2.h>
19 #include <asm/clinkage.h>
22 #define CPU_MODEL "v850e2/fpga85e2c"
23 #define CPU_MODEL_LONG "NEC V850E2/NA85E2C"
24 #define PLATFORM "fpga85e2c"
25 #define PLATFORM_LONG "NA85E2C FPGA implementation"
28 /* `external ram'. */
29 #define ERAM_ADDR 0
30 #define ERAM_SIZE 0x00100000 /* 1MB */
33 /* FPGA specific control registers. */
35 /* Writing a non-zero value to FLGREG(0) will signal the controlling CPU
36 to stop execution. */
37 #define FLGREG_ADDR(n) (0xFFE80100 + 2*(n))
38 #define FLGREG(n) (*(volatile unsigned char *)FLGREG_ADDR (n))
39 #define FLGREG_NUM 2
41 #define CSDEV_ADDR(n) (0xFFE80110 + 2*(n))
42 #define CSDEV(n) (*(volatile unsigned char *)CSDEV_ADDR (n))
45 /* Timer interrupts 0-3, interrupt at intervals from CLK/4096 to CLK/16384. */
46 #define IRQ_RPU(n) (60 + (n))
47 #define IRQ_RPU_NUM 4
49 /* For <asm/irq.h> */
50 #define NUM_CPU_IRQS 64
53 /* General-purpose timer. */
54 /* control/status register (can only be read/written via bit insns) */
55 #define RPU_GTMC_ADDR 0xFFFFFB00
56 #define RPU_GTMC (*(volatile unsigned char *)RPU_GTMC_ADDR)
57 #define RPU_GTMC_CE_BIT 7 /* clock enable (control) */
58 #define RPU_GTMC_OV_BIT 6 /* overflow (status) */
59 #define RPU_GTMC_CLK_BIT 1 /* 0 = .5 MHz CLK, 1 = 1 Mhz (control) */
60 /* 32-bit count (8 least-significant bits are always zero). */
61 #define RPU_GTM_ADDR 0xFFFFFB28
62 #define RPU_GTM (*(volatile unsigned long *)RPU_GTMC_ADDR)
65 /* For <asm/page.h> */
66 #define PAGE_OFFSET ERAM_ADDR /* minimum allocatable address */
69 /* For <asm/entry.h> */
70 /* `R0 RAM', used for a few miscellaneous variables that must be accessible
71 using a load instruction relative to R0. The FPGA implementation
72 actually has no on-chip RAM, so we use part of main ram just after the
73 interrupt vectors. */
74 #ifdef __ASSEMBLY__
75 #define R0_RAM_ADDR lo(C_SYMBOL_NAME(_r0_ram))
76 #else
77 extern char _r0_ram;
78 #define R0_RAM_ADDR ((unsigned long)&_r0_ram);
79 #endif
82 /* For <asm/param.h> */
83 #ifndef HZ
84 #define HZ 122 /* actually, 8.192ms ticks =~ 122.07 */
85 #endif
88 #endif /* __V850_FPGA85E2C_H__ */