ia64/linux-2.6.18-xen.hg

view include/asm-v850/as85ep1.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-v850/as85ep1.h -- AS85EP1 evaluation CPU chip/board
3 *
4 * Copyright (C) 2001,02,03 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
14 #ifndef __V850_AS85EP1_H__
15 #define __V850_AS85EP1_H__
17 #include <asm/v850e.h>
20 #define CPU_MODEL "as85ep1"
21 #define CPU_MODEL_LONG "NEC V850E/AS85EP1"
22 #define PLATFORM "AS85EP1"
23 #define PLATFORM_LONG "NEC V850E/AS85EP1 evaluation board"
25 #define CPU_CLOCK_FREQ 96000000 /* 96MHz */
26 #define SYS_CLOCK_FREQ CPU_CLOCK_FREQ
29 /* 1MB of static RAM. */
30 #define SRAM_ADDR 0x00400000
31 #define SRAM_SIZE 0x00100000 /* 1MB */
32 /* About 58MB of DRAM. This can actually be at one of two positions,
33 determined by jump JP3; we have to use the first position because the
34 second is partially out of processor instruction addressing range
35 (though in the second position there's actually 64MB available). */
36 #define SDRAM_ADDR 0x00600000
37 #define SDRAM_SIZE 0x039F8000 /* approx 58MB */
39 /* For <asm/page.h> */
40 #define PAGE_OFFSET SRAM_ADDR
42 /* We use on-chip RAM, for a few miscellaneous variables that must be
43 accessible using a load instruction relative to R0. The AS85EP1 chip
44 16K of internal RAM located slightly before I/O space. */
45 #define R0_RAM_ADDR 0xFFFF8000
48 /* AS85EP1 specific control registers. */
49 #define AS85EP1_CSC_ADDR(n) (0xFFFFF060 + (n) * 2)
50 #define AS85EP1_CSC(n) (*(volatile u16 *)AS85EP1_CSC_ADDR(n))
51 #define AS85EP1_BSC_ADDR 0xFFFFF066
52 #define AS85EP1_BSC (*(volatile u16 *)AS85EP1_BSC_ADDR)
53 #define AS85EP1_BCT_ADDR(n) (0xFFFFF480 + (n) * 2)
54 #define AS85EP1_BCT(n) (*(volatile u16 *)AS85EP1_BCT_ADDR(n))
55 #define AS85EP1_DWC_ADDR(n) (0xFFFFF484 + (n) * 2)
56 #define AS85EP1_DWC(n) (*(volatile u16 *)AS85EP1_DWC_ADDR(n))
57 #define AS85EP1_BCC_ADDR 0xFFFFF488
58 #define AS85EP1_BCC (*(volatile u16 *)AS85EP1_BCC_ADDR)
59 #define AS85EP1_ASC_ADDR 0xFFFFF48A
60 #define AS85EP1_ASC (*(volatile u16 *)AS85EP1_ASC_ADDR)
61 #define AS85EP1_BCP_ADDR 0xFFFFF48C
62 #define AS85EP1_BCP (*(volatile u16 *)AS85EP1_BCP_ADDR)
63 #define AS85EP1_LBS_ADDR 0xFFFFF48E
64 #define AS85EP1_LBS (*(volatile u16 *)AS85EP1_LBS_ADDR)
65 #define AS85EP1_BMC_ADDR 0xFFFFF498
66 #define AS85EP1_BMC (*(volatile u16 *)AS85EP1_BMC_ADDR)
67 #define AS85EP1_PRC_ADDR 0xFFFFF49A
68 #define AS85EP1_PRC (*(volatile u16 *)AS85EP1_PRC_ADDR)
69 #define AS85EP1_SCR_ADDR(n) (0xFFFFF4A0 + (n) * 4)
70 #define AS85EP1_SCR(n) (*(volatile u16 *)AS85EP1_SCR_ADDR(n))
71 #define AS85EP1_RFS_ADDR(n) (0xFFFFF4A2 + (n) * 4)
72 #define AS85EP1_RFS(n) (*(volatile u16 *)AS85EP1_RFS_ADDR(n))
73 #define AS85EP1_IRAMM_ADDR 0xFFFFF80A
74 #define AS85EP1_IRAMM (*(volatile u8 *)AS85EP1_IRAMM_ADDR)
78 /* I/O port P0-P13. */
79 /* Direct I/O. Bits 0-7 are pins Pn0-Pn7. */
80 #define AS85EP1_PORT_IO_ADDR(n) (0xFFFFF400 + (n) * 2)
81 #define AS85EP1_PORT_IO(n) (*(volatile u8 *)AS85EP1_PORT_IO_ADDR(n))
82 /* Port mode (for direct I/O, 0 = output, 1 = input). */
83 #define AS85EP1_PORT_PM_ADDR(n) (0xFFFFF420 + (n) * 2)
84 #define AS85EP1_PORT_PM(n) (*(volatile u8 *)AS85EP1_PORT_PM_ADDR(n))
85 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
86 #define AS85EP1_PORT_PMC_ADDR(n) (0xFFFFF440 + (n) * 2)
87 #define AS85EP1_PORT_PMC(n) (*(volatile u8 *)AS85EP1_PORT_PMC_ADDR(n))
90 /* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
91 #define IRQ_INTCCC(n) (0x0C + (n))
92 #define IRQ_INTCCC_NUM 8
93 #define IRQ_INTCMD(n) (0x14 + (n)) /* interval timer interrupts 0-5 */
94 #define IRQ_INTCMD_NUM 6
95 #define IRQ_INTSRE(n) (0x1E + (n)*3) /* UART 0-1 reception error */
96 #define IRQ_INTSRE_NUM 2
97 #define IRQ_INTSR(n) (0x1F + (n)*3) /* UART 0-1 reception completion */
98 #define IRQ_INTSR_NUM 2
99 #define IRQ_INTST(n) (0x20 + (n)*3) /* UART 0-1 transmission completion */
100 #define IRQ_INTST_NUM 2
102 #define NUM_CPU_IRQS 64
104 #ifndef __ASSEMBLY__
105 /* Initialize chip interrupts. */
106 extern void as85ep1_init_irqs (void);
107 #endif
110 /* AS85EP1 UART details (basically the same as the V850E/MA1, but 2 channels). */
111 #define V850E_UART_NUM_CHANNELS 2
112 #define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 4)
113 #define V850E_UART_CHIP_NAME "V850E/NA85E"
115 /* This is a function that gets called before configuring the UART. */
116 #define V850E_UART_PRE_CONFIGURE as85ep1_uart_pre_configure
117 #ifndef __ASSEMBLY__
118 extern void as85ep1_uart_pre_configure (unsigned chan,
119 unsigned cflags, unsigned baud);
120 #endif
122 /* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
124 /* CTS for UART channel 1 is pin P54 (bit 4 of port 5). */
125 #define V850E_UART_CTS(chan) ((chan) == 1 ? !(AS85EP1_PORT_IO(5) & 0x10) : 1)
126 /* RTS for UART channel 1 is pin P53 (bit 3 of port 5). */
127 #define V850E_UART_SET_RTS(chan, val) \
128 do { \
129 if (chan == 1) { \
130 unsigned old = AS85EP1_PORT_IO(5); \
131 if (val) \
132 AS85EP1_PORT_IO(5) = old & ~0x8; \
133 else \
134 AS85EP1_PORT_IO(5) = old | 0x8; \
135 } \
136 } while (0)
139 /* Timer C details. */
140 #define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
142 /* Timer D details (the AS85EP1 actually has 5 of these; should change later). */
143 #define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
144 #define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
145 #define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
146 #define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
148 #define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
149 #define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */
152 /* For <asm/param.h> */
153 #ifndef HZ
154 #define HZ 100
155 #endif
158 #endif /* __V850_AS85EP1_H__ */