ia64/linux-2.6.18-xen.hg

view include/asm-ppc/io.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 #ifdef __KERNEL__
2 #ifndef _PPC_IO_H
3 #define _PPC_IO_H
5 #include <linux/string.h>
6 #include <linux/types.h>
8 #include <asm/page.h>
9 #include <asm/byteorder.h>
10 #include <asm/synch.h>
11 #include <asm/mmu.h>
13 #define SIO_CONFIG_RA 0x398
14 #define SIO_CONFIG_RD 0x399
16 #define SLOW_DOWN_IO
18 #define PMAC_ISA_MEM_BASE 0
19 #define PMAC_PCI_DRAM_OFFSET 0
20 #define CHRP_ISA_IO_BASE 0xf8000000
21 #define CHRP_ISA_MEM_BASE 0xf7000000
22 #define CHRP_PCI_DRAM_OFFSET 0
23 #define PREP_ISA_IO_BASE 0x80000000
24 #define PREP_ISA_MEM_BASE 0xc0000000
25 #define PREP_PCI_DRAM_OFFSET 0x80000000
27 #if defined(CONFIG_4xx)
28 #include <asm/ibm4xx.h>
29 #elif defined(CONFIG_PPC_MPC52xx)
30 #include <asm/mpc52xx.h>
31 #elif defined(CONFIG_8xx)
32 #include <asm/mpc8xx.h>
33 #elif defined(CONFIG_8260)
34 #include <asm/mpc8260.h>
35 #elif defined(CONFIG_83xx)
36 #include <asm/mpc83xx.h>
37 #elif defined(CONFIG_85xx)
38 #include <asm/mpc85xx.h>
39 #elif defined(CONFIG_APUS)
40 #define _IO_BASE 0
41 #define _ISA_MEM_BASE 0
42 #define PCI_DRAM_OFFSET 0
43 #else /* Everyone else */
44 #define _IO_BASE isa_io_base
45 #define _ISA_MEM_BASE isa_mem_base
46 #define PCI_DRAM_OFFSET pci_dram_offset
47 #endif /* Platform-dependent I/O */
49 #define ___IO_BASE ((void __iomem *)_IO_BASE)
50 extern unsigned long isa_io_base;
51 extern unsigned long isa_mem_base;
52 extern unsigned long pci_dram_offset;
54 /*
55 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
56 *
57 * Read operations have additional twi & isync to make sure the read
58 * is actually performed (i.e. the data has come back) before we start
59 * executing any following instructions.
60 */
61 extern inline int in_8(const volatile unsigned char __iomem *addr)
62 {
63 int ret;
65 __asm__ __volatile__(
66 "sync; lbz%U1%X1 %0,%1;\n"
67 "twi 0,%0,0;\n"
68 "isync" : "=r" (ret) : "m" (*addr));
69 return ret;
70 }
72 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
73 {
74 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
75 }
77 extern inline int in_le16(const volatile unsigned short __iomem *addr)
78 {
79 int ret;
81 __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
82 "twi 0,%0,0;\n"
83 "isync" : "=r" (ret) :
84 "r" (addr), "m" (*addr));
85 return ret;
86 }
88 extern inline int in_be16(const volatile unsigned short __iomem *addr)
89 {
90 int ret;
92 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
93 "twi 0,%0,0;\n"
94 "isync" : "=r" (ret) : "m" (*addr));
95 return ret;
96 }
98 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
99 {
100 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
101 "r" (val), "r" (addr));
102 }
104 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
105 {
106 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
107 }
109 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
110 {
111 unsigned ret;
113 __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
114 "twi 0,%0,0;\n"
115 "isync" : "=r" (ret) :
116 "r" (addr), "m" (*addr));
117 return ret;
118 }
120 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
121 {
122 unsigned ret;
124 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
125 "twi 0,%0,0;\n"
126 "isync" : "=r" (ret) : "m" (*addr));
127 return ret;
128 }
130 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
131 {
132 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
133 "r" (val), "r" (addr));
134 }
136 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
137 {
138 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
139 }
140 #if defined (CONFIG_8260_PCI9)
141 #define readb(addr) in_8((volatile u8 *)(addr))
142 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
143 #else
144 static inline __u8 readb(const volatile void __iomem *addr)
145 {
146 return in_8(addr);
147 }
148 static inline void writeb(__u8 b, volatile void __iomem *addr)
149 {
150 out_8(addr, b);
151 }
152 #endif
154 #if defined(CONFIG_APUS)
155 static inline __u16 readw(const volatile void __iomem *addr)
156 {
157 return *(__force volatile __u16 *)(addr);
158 }
159 static inline __u32 readl(const volatile void __iomem *addr)
160 {
161 return *(__force volatile __u32 *)(addr);
162 }
163 static inline void writew(__u16 b, volatile void __iomem *addr)
164 {
165 *(__force volatile __u16 *)(addr) = b;
166 }
167 static inline void writel(__u32 b, volatile void __iomem *addr)
168 {
169 *(__force volatile __u32 *)(addr) = b;
170 }
171 #elif defined (CONFIG_8260_PCI9)
172 /* Use macros if PCI9 workaround enabled */
173 #define readw(addr) in_le16((volatile u16 *)(addr))
174 #define readl(addr) in_le32((volatile u32 *)(addr))
175 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
176 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
177 #else
178 static inline __u16 readw(const volatile void __iomem *addr)
179 {
180 return in_le16(addr);
181 }
182 static inline __u32 readl(const volatile void __iomem *addr)
183 {
184 return in_le32(addr);
185 }
186 static inline void writew(__u16 b, volatile void __iomem *addr)
187 {
188 out_le16(addr, b);
189 }
190 static inline void writel(__u32 b, volatile void __iomem *addr)
191 {
192 out_le32(addr, b);
193 }
194 #endif /* CONFIG_APUS */
196 #define readb_relaxed(addr) readb(addr)
197 #define readw_relaxed(addr) readw(addr)
198 #define readl_relaxed(addr) readl(addr)
200 static inline __u8 __raw_readb(const volatile void __iomem *addr)
201 {
202 return *(__force volatile __u8 *)(addr);
203 }
204 static inline __u16 __raw_readw(const volatile void __iomem *addr)
205 {
206 return *(__force volatile __u16 *)(addr);
207 }
208 static inline __u32 __raw_readl(const volatile void __iomem *addr)
209 {
210 return *(__force volatile __u32 *)(addr);
211 }
212 static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
213 {
214 *(__force volatile __u8 *)(addr) = b;
215 }
216 static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
217 {
218 *(__force volatile __u16 *)(addr) = b;
219 }
220 static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
221 {
222 *(__force volatile __u32 *)(addr) = b;
223 }
225 #define mmiowb()
227 /*
228 * The insw/outsw/insl/outsl macros don't do byte-swapping.
229 * They are only used in practice for transferring buffers which
230 * are arrays of bytes, and byte-swapping is not appropriate in
231 * that case. - paulus
232 */
233 #define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
234 #define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
235 #define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
236 #define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
237 #define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
238 #define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
240 /*
241 * On powermacs and 8xx we will get a machine check exception
242 * if we try to read data from a non-existent I/O port. Because
243 * the machine check is an asynchronous exception, it isn't
244 * well-defined which instruction SRR0 will point to when the
245 * exception occurs.
246 * With the sequence below (twi; isync; nop), we have found that
247 * the machine check occurs on one of the three instructions on
248 * all PPC implementations tested so far. The twi and isync are
249 * needed on the 601 (in fact twi; sync works too), the isync and
250 * nop are needed on 604[e|r], and any of twi, sync or isync will
251 * work on 603[e], 750, 74xx.
252 * The twi creates an explicit data dependency on the returned
253 * value which seems to be needed to make the 601 wait for the
254 * load to finish.
255 */
257 #define __do_in_asm(name, op) \
258 extern __inline__ unsigned int name(unsigned int port) \
259 { \
260 unsigned int x; \
261 __asm__ __volatile__( \
262 "sync\n" \
263 "0:" op " %0,0,%1\n" \
264 "1: twi 0,%0,0\n" \
265 "2: isync\n" \
266 "3: nop\n" \
267 "4:\n" \
268 ".section .fixup,\"ax\"\n" \
269 "5: li %0,-1\n" \
270 " b 4b\n" \
271 ".previous\n" \
272 ".section __ex_table,\"a\"\n" \
273 " .align 2\n" \
274 " .long 0b,5b\n" \
275 " .long 1b,5b\n" \
276 " .long 2b,5b\n" \
277 " .long 3b,5b\n" \
278 ".previous" \
279 : "=&r" (x) \
280 : "r" (port + ___IO_BASE)); \
281 return x; \
282 }
284 #define __do_out_asm(name, op) \
285 extern __inline__ void name(unsigned int val, unsigned int port) \
286 { \
287 __asm__ __volatile__( \
288 "sync\n" \
289 "0:" op " %0,0,%1\n" \
290 "1: sync\n" \
291 "2:\n" \
292 ".section __ex_table,\"a\"\n" \
293 " .align 2\n" \
294 " .long 0b,2b\n" \
295 " .long 1b,2b\n" \
296 ".previous" \
297 : : "r" (val), "r" (port + ___IO_BASE)); \
298 }
300 __do_out_asm(outb, "stbx")
301 #ifdef CONFIG_APUS
302 __do_in_asm(inb, "lbzx")
303 __do_in_asm(inw, "lhz%U1%X1")
304 __do_in_asm(inl, "lwz%U1%X1")
305 __do_out_asm(outl,"stw%U0%X0")
306 __do_out_asm(outw, "sth%U0%X0")
307 #elif defined (CONFIG_8260_PCI9)
308 /* in asm cannot be defined if PCI9 workaround is used */
309 #define inb(port) in_8((port)+___IO_BASE)
310 #define inw(port) in_le16((port)+___IO_BASE)
311 #define inl(port) in_le32((port)+___IO_BASE)
312 __do_out_asm(outw, "sthbrx")
313 __do_out_asm(outl, "stwbrx")
314 #else
315 __do_in_asm(inb, "lbzx")
316 __do_in_asm(inw, "lhbrx")
317 __do_in_asm(inl, "lwbrx")
318 __do_out_asm(outw, "sthbrx")
319 __do_out_asm(outl, "stwbrx")
321 #endif
323 #define inb_p(port) inb((port))
324 #define outb_p(val, port) outb((val), (port))
325 #define inw_p(port) inw((port))
326 #define outw_p(val, port) outw((val), (port))
327 #define inl_p(port) inl((port))
328 #define outl_p(val, port) outl((val), (port))
330 extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
331 extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
332 extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
333 extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
334 extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
335 extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
336 extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
337 extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
338 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
339 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
341 /*
342 * The *_ns versions below don't do byte-swapping.
343 * Neither do the standard versions now, these are just here
344 * for older code.
345 */
346 #define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
347 #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
348 #define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
349 #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
352 #define IO_SPACE_LIMIT ~0
354 #if defined (CONFIG_8260_PCI9)
355 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
356 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
357 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
358 #else
359 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
360 {
361 memset((void __force *)addr, val, count);
362 }
363 static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
364 {
365 memcpy(dst, (void __force *) src, count);
366 }
367 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
368 {
369 memcpy((void __force *) dst, src, count);
370 }
371 #endif
373 #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
375 /*
376 * Map in an area of physical address space, for accessing
377 * I/O devices etc.
378 */
379 extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
380 unsigned long flags);
381 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
382 #ifdef CONFIG_44x
383 extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
384 #endif
385 #define ioremap_nocache(addr, size) ioremap((addr), (size))
386 extern void iounmap(volatile void __iomem *addr);
387 extern unsigned long iopa(unsigned long addr);
388 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
389 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
390 unsigned int size, int flags);
392 /*
393 * The PCI bus is inherently Little-Endian. The PowerPC is being
394 * run Big-Endian. Thus all values which cross the [PCI] barrier
395 * must be endian-adjusted. Also, the local DRAM has a different
396 * address from the PCI point of view, thus buffer addresses also
397 * have to be modified [mapped] appropriately.
398 */
399 extern inline unsigned long virt_to_bus(volatile void * address)
400 {
401 #ifndef CONFIG_APUS
402 if (address == (void *)0)
403 return 0;
404 return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
405 #else
406 return iopa ((unsigned long) address);
407 #endif
408 }
410 extern inline void * bus_to_virt(unsigned long address)
411 {
412 #ifndef CONFIG_APUS
413 if (address == 0)
414 return NULL;
415 return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
416 #else
417 return (void*) mm_ptov (address);
418 #endif
419 }
421 /*
422 * Change virtual addresses to physical addresses and vv, for
423 * addresses in the area where the kernel has the RAM mapped.
424 */
425 extern inline unsigned long virt_to_phys(volatile void * address)
426 {
427 #ifndef CONFIG_APUS
428 return (unsigned long) address - KERNELBASE;
429 #else
430 return iopa ((unsigned long) address);
431 #endif
432 }
434 extern inline void * phys_to_virt(unsigned long address)
435 {
436 #ifndef CONFIG_APUS
437 return (void *) (address + KERNELBASE);
438 #else
439 return (void*) mm_ptov (address);
440 #endif
441 }
443 /*
444 * Change "struct page" to physical address.
445 */
446 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
447 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
449 /* Enforce in-order execution of data I/O.
450 * No distinction between read/write on PPC; use eieio for all three.
451 */
452 #define iobarrier_rw() eieio()
453 #define iobarrier_r() eieio()
454 #define iobarrier_w() eieio()
456 static inline int check_signature(volatile void __iomem * io_addr,
457 const unsigned char *signature, int length)
458 {
459 int retval = 0;
460 do {
461 if (readb(io_addr) != *signature)
462 goto out;
463 io_addr++;
464 signature++;
465 length--;
466 } while (length);
467 retval = 1;
468 out:
469 return retval;
470 }
472 /*
473 * Here comes the ppc implementation of the IOMAP
474 * interfaces.
475 */
476 static inline unsigned int ioread8(void __iomem *addr)
477 {
478 return readb(addr);
479 }
481 static inline unsigned int ioread16(void __iomem *addr)
482 {
483 return readw(addr);
484 }
486 static inline unsigned int ioread32(void __iomem *addr)
487 {
488 return readl(addr);
489 }
491 static inline void iowrite8(u8 val, void __iomem *addr)
492 {
493 writeb(val, addr);
494 }
496 static inline void iowrite16(u16 val, void __iomem *addr)
497 {
498 writew(val, addr);
499 }
501 static inline void iowrite32(u32 val, void __iomem *addr)
502 {
503 writel(val, addr);
504 }
506 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
507 {
508 _insb(addr, dst, count);
509 }
511 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
512 {
513 _insw_ns(addr, dst, count);
514 }
516 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
517 {
518 _insl_ns(addr, dst, count);
519 }
521 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
522 {
523 _outsb(addr, src, count);
524 }
526 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
527 {
528 _outsw_ns(addr, src, count);
529 }
531 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
532 {
533 _outsl_ns(addr, src, count);
534 }
536 /* Create a virtual mapping cookie for an IO port range */
537 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
538 extern void ioport_unmap(void __iomem *);
540 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
541 struct pci_dev;
542 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
543 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
545 #endif /* _PPC_IO_H */
547 #ifdef CONFIG_8260_PCI9
548 #include <asm/mpc8260_pci9.h>
549 #endif
551 #ifdef CONFIG_NOT_COHERENT_CACHE
553 #define dma_cache_inv(_start,_size) \
554 invalidate_dcache_range(_start, (_start + _size))
555 #define dma_cache_wback(_start,_size) \
556 clean_dcache_range(_start, (_start + _size))
557 #define dma_cache_wback_inv(_start,_size) \
558 flush_dcache_range(_start, (_start + _size))
560 #else
562 #define dma_cache_inv(_start,_size) do { } while (0)
563 #define dma_cache_wback(_start,_size) do { } while (0)
564 #define dma_cache_wback_inv(_start,_size) do { } while (0)
566 #endif
568 /*
569 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
570 * access
571 */
572 #define xlate_dev_mem_ptr(p) __va(p)
574 /*
575 * Convert a virtual cached pointer to an uncached pointer
576 */
577 #define xlate_dev_kmem_ptr(p) p
579 /* access ports */
580 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
581 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
583 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
584 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
586 #endif /* __KERNEL__ */