ia64/linux-2.6.18-xen.hg

view include/asm-m68knommu/m520xsim.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /****************************************************************************/
3 /*
4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
5 *
6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
7 */
9 /****************************************************************************/
10 #ifndef m520xsim_h
11 #define m520xsim_h
12 /****************************************************************************/
15 /*
16 * Define the 5282 SIM register set addresses.
17 */
18 #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
19 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
20 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
21 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
22 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
23 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
24 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
25 #define MCFINTC_ICR0 0x40 /* Base ICR register */
27 #define MCFINT_VECBASE 64
28 #define MCFINT_UART0 26 /* Interrupt number for UART0 */
29 #define MCFINT_UART1 27 /* Interrupt number for UART1 */
30 #define MCFINT_UART2 28 /* Interrupt number for UART2 */
31 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
32 #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
35 #define MCF_GPIO_PAR_UART (0xA4036)
36 #define MCF_GPIO_PAR_FECI2C (0xA4033)
37 #define MCF_GPIO_PAR_FEC (0xA4038)
39 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
40 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
42 #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
43 #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
45 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
46 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
48 #define ICR_INTRCONF 0x05
49 #define MCFPIT_IMR MCFINTC_IMRL
50 #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
52 /****************************************************************************/
53 #endif /* m520xsim_h */