ia64/linux-2.6.18-xen.hg

view include/asm-m68knommu/MC68328.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
2 /* include/asm-m68knommu/MC68328.h: '328 control registers
3 *
4 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
5 * Bear & Hare Software, Inc.
6 *
7 * Based on include/asm-m68knommu/MC68332.h
8 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
9 *
10 */
12 #ifndef _MC68328_H_
13 #define _MC68328_H_
15 #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
16 #define WORD_REF(addr) (*((volatile unsigned short*)addr))
17 #define LONG_REF(addr) (*((volatile unsigned long*)addr))
19 #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
20 #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
22 /**********
23 *
24 * 0xFFFFF0xx -- System Control
25 *
26 **********/
28 /*
29 * System Control Register (SCR)
30 */
31 #define SCR_ADDR 0xfffff000
32 #define SCR BYTE_REF(SCR_ADDR)
34 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
35 #define SCR_DMAP 0x04 /* Double Map */
36 #define SCR_SO 0x08 /* Supervisor Only */
37 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
38 #define SCR_PRV 0x20 /* Privilege Violation */
39 #define SCR_WPV 0x40 /* Write Protect Violation */
40 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
42 /*
43 * Mask Revision Register
44 */
45 #define MRR_ADDR 0xfffff004
46 #define MRR LONG_REF(MRR_ADDR)
48 /**********
49 *
50 * 0xFFFFF1xx -- Chip-Select logic
51 *
52 **********/
54 /**********
55 *
56 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
57 *
58 **********/
60 /*
61 * Group Base Address Registers
62 */
63 #define GRPBASEA_ADDR 0xfffff100
64 #define GRPBASEB_ADDR 0xfffff102
65 #define GRPBASEC_ADDR 0xfffff104
66 #define GRPBASED_ADDR 0xfffff106
68 #define GRPBASEA WORD_REF(GRPBASEA_ADDR)
69 #define GRPBASEB WORD_REF(GRPBASEB_ADDR)
70 #define GRPBASEC WORD_REF(GRPBASEC_ADDR)
71 #define GRPBASED WORD_REF(GRPBASED_ADDR)
73 #define GRPBASE_V 0x0001 /* Valid */
74 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
76 /*
77 * Group Base Address Mask Registers
78 */
79 #define GRPMASKA_ADDR 0xfffff108
80 #define GRPMASKB_ADDR 0xfffff10a
81 #define GRPMASKC_ADDR 0xfffff10c
82 #define GRPMASKD_ADDR 0xfffff10e
84 #define GRPMASKA WORD_REF(GRPMASKA_ADDR)
85 #define GRPMASKB WORD_REF(GRPMASKB_ADDR)
86 #define GRPMASKC WORD_REF(GRPMASKC_ADDR)
87 #define GRPMASKD WORD_REF(GRPMASKD_ADDR)
89 #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
91 /*
92 * Chip-Select Option Registers (group A)
93 */
94 #define CSA0_ADDR 0xfffff110
95 #define CSA1_ADDR 0xfffff114
96 #define CSA2_ADDR 0xfffff118
97 #define CSA3_ADDR 0xfffff11c
99 #define CSA0 LONG_REF(CSA0_ADDR)
100 #define CSA1 LONG_REF(CSA1_ADDR)
101 #define CSA2 LONG_REF(CSA2_ADDR)
102 #define CSA3 LONG_REF(CSA3_ADDR)
104 #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
105 #define CSA_WAIT_SHIFT 0
106 #define CSA_RO 0x00000008 /* Read-Only */
107 #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
108 #define CSA_AM_SHIFT 8
109 #define CSA_BUSW 0x00010000 /* Bus Width Select */
110 #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
111 #define CSA_AC_SHIFT 24
113 /*
114 * Chip-Select Option Registers (group B)
115 */
116 #define CSB0_ADDR 0xfffff120
117 #define CSB1_ADDR 0xfffff124
118 #define CSB2_ADDR 0xfffff128
119 #define CSB3_ADDR 0xfffff12c
121 #define CSB0 LONG_REF(CSB0_ADDR)
122 #define CSB1 LONG_REF(CSB1_ADDR)
123 #define CSB2 LONG_REF(CSB2_ADDR)
124 #define CSB3 LONG_REF(CSB3_ADDR)
126 #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
127 #define CSB_WAIT_SHIFT 0
128 #define CSB_RO 0x00000008 /* Read-Only */
129 #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
130 #define CSB_AM_SHIFT 8
131 #define CSB_BUSW 0x00010000 /* Bus Width Select */
132 #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
133 #define CSB_AC_SHIFT 24
135 /*
136 * Chip-Select Option Registers (group C)
137 */
138 #define CSC0_ADDR 0xfffff130
139 #define CSC1_ADDR 0xfffff134
140 #define CSC2_ADDR 0xfffff138
141 #define CSC3_ADDR 0xfffff13c
143 #define CSC0 LONG_REF(CSC0_ADDR)
144 #define CSC1 LONG_REF(CSC1_ADDR)
145 #define CSC2 LONG_REF(CSC2_ADDR)
146 #define CSC3 LONG_REF(CSC3_ADDR)
148 #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
149 #define CSC_WAIT_SHIFT 0
150 #define CSC_RO 0x00000008 /* Read-Only */
151 #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
152 #define CSC_AM_SHIFT 4
153 #define CSC_BUSW 0x00010000 /* Bus Width Select */
154 #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
155 #define CSC_AC_SHIFT 20
157 /*
158 * Chip-Select Option Registers (group D)
159 */
160 #define CSD0_ADDR 0xfffff140
161 #define CSD1_ADDR 0xfffff144
162 #define CSD2_ADDR 0xfffff148
163 #define CSD3_ADDR 0xfffff14c
165 #define CSD0 LONG_REF(CSD0_ADDR)
166 #define CSD1 LONG_REF(CSD1_ADDR)
167 #define CSD2 LONG_REF(CSD2_ADDR)
168 #define CSD3 LONG_REF(CSD3_ADDR)
170 #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
171 #define CSD_WAIT_SHIFT 0
172 #define CSD_RO 0x00000008 /* Read-Only */
173 #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
174 #define CSD_AM_SHIFT 4
175 #define CSD_BUSW 0x00010000 /* Bus Width Select */
176 #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
177 #define CSD_AC_SHIFT 20
179 /**********
180 *
181 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
182 *
183 **********/
185 /*
186 * PLL Control Register
187 */
188 #define PLLCR_ADDR 0xfffff200
189 #define PLLCR WORD_REF(PLLCR_ADDR)
191 #define PLLCR_DISPLL 0x0008 /* Disable PLL */
192 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
193 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
194 #define PLLCR_SYSCLK_SEL_SHIFT 8
195 #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
196 #define PLLCR_PIXCLK_SEL_SHIFT 11
198 /* 'EZ328-compatible definitions */
199 #define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
200 #define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
202 /*
203 * PLL Frequency Select Register
204 */
205 #define PLLFSR_ADDR 0xfffff202
206 #define PLLFSR WORD_REF(PLLFSR_ADDR)
208 #define PLLFSR_PC_MASK 0x00ff /* P Count */
209 #define PLLFSR_PC_SHIFT 0
210 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
211 #define PLLFSR_QC_SHIFT 8
212 #define PLLFSR_PROT 0x4000 /* Protect P & Q */
213 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
215 /*
216 * Power Control Register
217 */
218 #define PCTRL_ADDR 0xfffff207
219 #define PCTRL BYTE_REF(PCTRL_ADDR)
221 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
222 #define PCTRL_WIDTH_SHIFT 0
223 #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
224 #define PCTRL_PCEN 0x80 /* Power Control Enable */
226 /**********
227 *
228 * 0xFFFFF3xx -- Interrupt Controller
229 *
230 **********/
232 /*
233 * Interrupt Vector Register
234 */
235 #define IVR_ADDR 0xfffff300
236 #define IVR BYTE_REF(IVR_ADDR)
238 #define IVR_VECTOR_MASK 0xF8
240 /*
241 * Interrupt control Register
242 */
243 #define ICR_ADRR 0xfffff302
244 #define ICR WORD_REF(ICR_ADDR)
246 #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
247 #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
248 #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
249 #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
250 #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
251 #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
252 #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
253 #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
255 /*
256 * Interrupt Mask Register
257 */
258 #define IMR_ADDR 0xfffff304
259 #define IMR LONG_REF(IMR_ADDR)
261 /*
262 * Define the names for bit positions first. This is useful for
263 * request_irq
264 */
265 #define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
266 #define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
267 #define UART_IRQ_NUM 2 /* UART interrupt */
268 #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
269 #define RTC_IRQ_NUM 4 /* RTC interrupt */
270 #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
271 #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
272 #define INT0_IRQ_NUM 8 /* External INT0 */
273 #define INT1_IRQ_NUM 9 /* External INT1 */
274 #define INT2_IRQ_NUM 10 /* External INT2 */
275 #define INT3_IRQ_NUM 11 /* External INT3 */
276 #define INT4_IRQ_NUM 12 /* External INT4 */
277 #define INT5_IRQ_NUM 13 /* External INT5 */
278 #define INT6_IRQ_NUM 14 /* External INT6 */
279 #define INT7_IRQ_NUM 15 /* External INT7 */
280 #define IRQ1_IRQ_NUM 16 /* IRQ1 */
281 #define IRQ2_IRQ_NUM 17 /* IRQ2 */
282 #define IRQ3_IRQ_NUM 18 /* IRQ3 */
283 #define IRQ6_IRQ_NUM 19 /* IRQ6 */
284 #define PEN_IRQ_NUM 20 /* Pen Interrupt */
285 #define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
286 #define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
287 #define IRQ7_IRQ_NUM 23 /* IRQ7 */
289 /* '328-compatible definitions */
290 #define SPI_IRQ_NUM SPIM_IRQ_NUM
291 #define TMR_IRQ_NUM TMR1_IRQ_NUM
293 /*
294 * Here go the bitmasks themselves
295 */
296 #define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */
297 #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
298 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
299 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
300 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
301 #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
302 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
303 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
304 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
305 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
306 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
307 #define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
308 #define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
309 #define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
310 #define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
311 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
312 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
313 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
314 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
315 #define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
316 #define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
317 #define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
318 #define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
320 /* 'EZ328-compatible definitions */
321 #define IMR_MSPI IMR_MSPIM
322 #define IMR_MTMR IMR_MTMR1
324 /*
325 * Interrupt Wake-Up Enable Register
326 */
327 #define IWR_ADDR 0xfffff308
328 #define IWR LONG_REF(IWR_ADDR)
330 #define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
331 #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
332 #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
333 #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
334 #define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
335 #define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
336 #define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
337 #define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
338 #define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
339 #define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
340 #define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
341 #define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
342 #define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
343 #define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
344 #define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
345 #define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
346 #define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
347 #define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
348 #define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
349 #define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
350 #define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
351 #define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
352 #define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
354 /*
355 * Interrupt Status Register
356 */
357 #define ISR_ADDR 0xfffff30c
358 #define ISR LONG_REF(ISR_ADDR)
360 #define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
361 #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
362 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
363 #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
364 #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
365 #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
366 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
367 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
368 #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
369 #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
370 #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
371 #define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
372 #define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
373 #define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
374 #define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
375 #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
376 #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
377 #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
378 #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
379 #define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
380 #define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
381 #define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
382 #define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
384 /* 'EZ328-compatible definitions */
385 #define ISR_SPI ISR_SPIM
386 #define ISR_TMR ISR_TMR1
388 /*
389 * Interrupt Pending Register
390 */
391 #define IPR_ADDR 0xfffff310
392 #define IPR LONG_REF(IPR_ADDR)
394 #define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
395 #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
396 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
397 #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
398 #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
399 #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
400 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
401 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
402 #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
403 #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
404 #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
405 #define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
406 #define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
407 #define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
408 #define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
409 #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
410 #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
411 #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
412 #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
413 #define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
414 #define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
415 #define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
416 #define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
418 /* 'EZ328-compatible definitions */
419 #define IPR_SPI IPR_SPIM
420 #define IPR_TMR IPR_TMR1
422 /**********
423 *
424 * 0xFFFFF4xx -- Parallel Ports
425 *
426 **********/
428 /*
429 * Port A
430 */
431 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
432 #define PADATA_ADDR 0xfffff401 /* Port A data register */
433 #define PASEL_ADDR 0xfffff403 /* Port A Select register */
435 #define PADIR BYTE_REF(PADIR_ADDR)
436 #define PADATA BYTE_REF(PADATA_ADDR)
437 #define PASEL BYTE_REF(PASEL_ADDR)
439 #define PA(x) (1 << (x))
440 #define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
442 #define PA_A16 PA(0) /* Use A16 as PA(0) */
443 #define PA_A17 PA(1) /* Use A17 as PA(1) */
444 #define PA_A18 PA(2) /* Use A18 as PA(2) */
445 #define PA_A19 PA(3) /* Use A19 as PA(3) */
446 #define PA_A20 PA(4) /* Use A20 as PA(4) */
447 #define PA_A21 PA(5) /* Use A21 as PA(5) */
448 #define PA_A22 PA(6) /* Use A22 as PA(6) */
449 #define PA_A23 PA(7) /* Use A23 as PA(7) */
451 /*
452 * Port B
453 */
454 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
455 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
456 #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
458 #define PBDIR BYTE_REF(PBDIR_ADDR)
459 #define PBDATA BYTE_REF(PBDATA_ADDR)
460 #define PBSEL BYTE_REF(PBSEL_ADDR)
462 #define PB(x) (1 << (x))
463 #define PB_D(x) PB(x) /* This is specific to port B only */
465 #define PB_D0 PB(0) /* Use D0 as PB(0) */
466 #define PB_D1 PB(1) /* Use D1 as PB(1) */
467 #define PB_D2 PB(2) /* Use D2 as PB(2) */
468 #define PB_D3 PB(3) /* Use D3 as PB(3) */
469 #define PB_D4 PB(4) /* Use D4 as PB(4) */
470 #define PB_D5 PB(5) /* Use D5 as PB(5) */
471 #define PB_D6 PB(6) /* Use D6 as PB(6) */
472 #define PB_D7 PB(7) /* Use D7 as PB(7) */
474 /*
475 * Port C
476 */
477 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
478 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
479 #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
481 #define PCDIR BYTE_REF(PCDIR_ADDR)
482 #define PCDATA BYTE_REF(PCDATA_ADDR)
483 #define PCSEL BYTE_REF(PCSEL_ADDR)
485 #define PC(x) (1 << (x))
487 #define PC_WE PC(6) /* Use WE as PC(6) */
488 #define PC_DTACK PC(5) /* Use DTACK as PC(5) */
489 #define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
490 #define PC_LDS PC(2) /* Use LDS as PC(2) */
491 #define PC_UDS PC(1) /* Use UDS as PC(1) */
492 #define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
494 /*
495 * Port D
496 */
497 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
498 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
499 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
500 #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
501 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
502 #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
504 #define PDDIR BYTE_REF(PDDIR_ADDR)
505 #define PDDATA BYTE_REF(PDDATA_ADDR)
506 #define PDPUEN BYTE_REF(PDPUEN_ADDR)
507 #define PDPOL BYTE_REF(PDPOL_ADDR)
508 #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
509 #define PDIQEG BYTE_REF(PDIQEG_ADDR)
511 #define PD(x) (1 << (x))
512 #define PD_KB(x) PD(x) /* This is specific for Port D only */
514 #define PD_KB0 PD(0) /* Use KB0 as PD(0) */
515 #define PD_KB1 PD(1) /* Use KB1 as PD(1) */
516 #define PD_KB2 PD(2) /* Use KB2 as PD(2) */
517 #define PD_KB3 PD(3) /* Use KB3 as PD(3) */
518 #define PD_KB4 PD(4) /* Use KB4 as PD(4) */
519 #define PD_KB5 PD(5) /* Use KB5 as PD(5) */
520 #define PD_KB6 PD(6) /* Use KB6 as PD(6) */
521 #define PD_KB7 PD(7) /* Use KB7 as PD(7) */
523 /*
524 * Port E
525 */
526 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
527 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
528 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
529 #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
531 #define PEDIR BYTE_REF(PEDIR_ADDR)
532 #define PEDATA BYTE_REF(PEDATA_ADDR)
533 #define PEPUEN BYTE_REF(PEPUEN_ADDR)
534 #define PESEL BYTE_REF(PESEL_ADDR)
536 #define PE(x) (1 << (x))
538 #define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
539 #define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
540 #define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
541 #define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
542 #define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
543 #define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
544 #define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
546 /*
547 * Port F
548 */
549 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
550 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
551 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
552 #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
554 #define PFDIR BYTE_REF(PFDIR_ADDR)
555 #define PFDATA BYTE_REF(PFDATA_ADDR)
556 #define PFPUEN BYTE_REF(PFPUEN_ADDR)
557 #define PFSEL BYTE_REF(PFSEL_ADDR)
559 #define PF(x) (1 << (x))
560 #define PF_A(x) PF((x) - 24) /* This is Port F specific only */
562 #define PF_A24 PF(0) /* Use A24 as PF(0) */
563 #define PF_A25 PF(1) /* Use A25 as PF(1) */
564 #define PF_A26 PF(2) /* Use A26 as PF(2) */
565 #define PF_A27 PF(3) /* Use A27 as PF(3) */
566 #define PF_A28 PF(4) /* Use A28 as PF(4) */
567 #define PF_A29 PF(5) /* Use A29 as PF(5) */
568 #define PF_A30 PF(6) /* Use A30 as PF(6) */
569 #define PF_A31 PF(7) /* Use A31 as PF(7) */
571 /*
572 * Port G
573 */
574 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
575 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
576 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
577 #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
579 #define PGDIR BYTE_REF(PGDIR_ADDR)
580 #define PGDATA BYTE_REF(PGDATA_ADDR)
581 #define PGPUEN BYTE_REF(PGPUEN_ADDR)
582 #define PGSEL BYTE_REF(PGSEL_ADDR)
584 #define PG(x) (1 << (x))
586 #define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
587 #define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
588 #define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
589 #define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
590 #define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
591 #define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
592 #define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
593 #define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
595 /*
596 * Port J
597 */
598 #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
599 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
600 #define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
602 #define PJDIR BYTE_REF(PJDIR_ADDR)
603 #define PJDATA BYTE_REF(PJDATA_ADDR)
604 #define PJSEL BYTE_REF(PJSEL_ADDR)
606 #define PJ(x) (1 << (x))
608 #define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
610 /*
611 * Port K
612 */
613 #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
614 #define PKDATA_ADDR 0xfffff441 /* Port K data register */
615 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
616 #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
618 #define PKDIR BYTE_REF(PKDIR_ADDR)
619 #define PKDATA BYTE_REF(PKDATA_ADDR)
620 #define PKPUEN BYTE_REF(PKPUEN_ADDR)
621 #define PKSEL BYTE_REF(PKSEL_ADDR)
623 #define PK(x) (1 << (x))
625 /*
626 * Port M
627 */
628 #define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
629 #define PMDATA_ADDR 0xfffff439 /* Port M data register */
630 #define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
631 #define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
633 #define PMDIR BYTE_REF(PMDIR_ADDR)
634 #define PMDATA BYTE_REF(PMDATA_ADDR)
635 #define PMPUEN BYTE_REF(PMPUEN_ADDR)
636 #define PMSEL BYTE_REF(PMSEL_ADDR)
638 #define PM(x) (1 << (x))
640 /**********
641 *
642 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
643 *
644 **********/
646 /*
647 * PWM Control Register
648 */
649 #define PWMC_ADDR 0xfffff500
650 #define PWMC WORD_REF(PWMC_ADDR)
652 #define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
653 #define PWMC_CLKSEL_SHIFT 0
654 #define PWMC_PWMEN 0x0010 /* Enable PWM */
655 #define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
656 #define PWMC_PIN 0x0080 /* Current PWM output pin status */
657 #define PWMC_LOAD 0x0100 /* Force a new period */
658 #define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
659 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
661 /* 'EZ328-compatible definitions */
662 #define PWMC_EN PWMC_PWMEN
664 /*
665 * PWM Period Register
666 */
667 #define PWMP_ADDR 0xfffff502
668 #define PWMP WORD_REF(PWMP_ADDR)
670 /*
671 * PWM Width Register
672 */
673 #define PWMW_ADDR 0xfffff504
674 #define PWMW WORD_REF(PWMW_ADDR)
676 /*
677 * PWM Counter Register
678 */
679 #define PWMCNT_ADDR 0xfffff506
680 #define PWMCNT WORD_REF(PWMCNT_ADDR)
682 /**********
683 *
684 * 0xFFFFF6xx -- General-Purpose Timers
685 *
686 **********/
688 /*
689 * Timer Unit 1 and 2 Control Registers
690 */
691 #define TCTL1_ADDR 0xfffff600
692 #define TCTL1 WORD_REF(TCTL1_ADDR)
693 #define TCTL2_ADDR 0xfffff60c
694 #define TCTL2 WORD_REF(TCTL2_ADDR)
696 #define TCTL_TEN 0x0001 /* Timer Enable */
697 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
698 #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
699 #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
700 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
701 #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
702 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
703 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
704 #define TCTL_OM 0x0020 /* Output Mode */
705 #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
706 #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
707 #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
708 #define TCTL_FRR 0x0010 /* Free-Run Mode */
710 /* 'EZ328-compatible definitions */
711 #define TCTL_ADDR TCTL1_ADDR
712 #define TCTL TCTL1
714 /*
715 * Timer Unit 1 and 2 Prescaler Registers
716 */
717 #define TPRER1_ADDR 0xfffff602
718 #define TPRER1 WORD_REF(TPRER1_ADDR)
719 #define TPRER2_ADDR 0xfffff60e
720 #define TPRER2 WORD_REF(TPRER2_ADDR)
722 /* 'EZ328-compatible definitions */
723 #define TPRER_ADDR TPRER1_ADDR
724 #define TPRER TPRER1
726 /*
727 * Timer Unit 1 and 2 Compare Registers
728 */
729 #define TCMP1_ADDR 0xfffff604
730 #define TCMP1 WORD_REF(TCMP1_ADDR)
731 #define TCMP2_ADDR 0xfffff610
732 #define TCMP2 WORD_REF(TCMP2_ADDR)
734 /* 'EZ328-compatible definitions */
735 #define TCMP_ADDR TCMP1_ADDR
736 #define TCMP TCMP1
738 /*
739 * Timer Unit 1 and 2 Capture Registers
740 */
741 #define TCR1_ADDR 0xfffff606
742 #define TCR1 WORD_REF(TCR1_ADDR)
743 #define TCR2_ADDR 0xfffff612
744 #define TCR2 WORD_REF(TCR2_ADDR)
746 /* 'EZ328-compatible definitions */
747 #define TCR_ADDR TCR1_ADDR
748 #define TCR TCR1
750 /*
751 * Timer Unit 1 and 2 Counter Registers
752 */
753 #define TCN1_ADDR 0xfffff608
754 #define TCN1 WORD_REF(TCN1_ADDR)
755 #define TCN2_ADDR 0xfffff614
756 #define TCN2 WORD_REF(TCN2_ADDR)
758 /* 'EZ328-compatible definitions */
759 #define TCN_ADDR TCN1_ADDR
760 #define TCN TCN
762 /*
763 * Timer Unit 1 and 2 Status Registers
764 */
765 #define TSTAT1_ADDR 0xfffff60a
766 #define TSTAT1 WORD_REF(TSTAT1_ADDR)
767 #define TSTAT2_ADDR 0xfffff616
768 #define TSTAT2 WORD_REF(TSTAT2_ADDR)
770 #define TSTAT_COMP 0x0001 /* Compare Event occurred */
771 #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
773 /* 'EZ328-compatible definitions */
774 #define TSTAT_ADDR TSTAT1_ADDR
775 #define TSTAT TSTAT1
777 /*
778 * Watchdog Compare Register
779 */
780 #define WRR_ADDR 0xfffff61a
781 #define WRR WORD_REF(WRR_ADDR)
783 /*
784 * Watchdog Counter Register
785 */
786 #define WCN_ADDR 0xfffff61c
787 #define WCN WORD_REF(WCN_ADDR)
789 /*
790 * Watchdog Control and Status Register
791 */
792 #define WCSR_ADDR 0xfffff618
793 #define WCSR WORD_REF(WCSR_ADDR)
795 #define WCSR_WDEN 0x0001 /* Watchdog Enable */
796 #define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
797 #define WCSR_WRST 0x0004 /* Watchdog Reset */
799 /**********
800 *
801 * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
802 *
803 **********/
805 /*
806 * SPI Slave Register
807 */
808 #define SPISR_ADDR 0xfffff700
809 #define SPISR WORD_REF(SPISR_ADDR)
811 #define SPISR_DATA_ADDR 0xfffff701
812 #define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
814 #define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
815 #define SPISR_DATA_SHIFT 0
816 #define SPISR_SPISEN 0x0100 /* SPIS module enable */
817 #define SPISR_POL 0x0200 /* SPSCLK polarity control */
818 #define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
819 #define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
820 #define SPISR_DATARDY 0x1000 /* Data ready */
821 #define SPISR_ENPOL 0x2000 /* Enable Polarity */
822 #define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
823 #define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
825 /**********
826 *
827 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
828 *
829 **********/
831 /*
832 * SPIM Data Register
833 */
834 #define SPIMDATA_ADDR 0xfffff800
835 #define SPIMDATA WORD_REF(SPIMDATA_ADDR)
837 /*
838 * SPIM Control/Status Register
839 */
840 #define SPIMCONT_ADDR 0xfffff802
841 #define SPIMCONT WORD_REF(SPIMCONT_ADDR)
843 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
844 #define SPIMCONT_BIT_COUNT_SHIFT 0
845 #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
846 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
847 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
848 #define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
849 #define SPIMCONT_XCH 0x0100 /* Exchange */
850 #define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
851 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
852 #define SPIMCONT_DATA_RATE_SHIFT 13
854 /* 'EZ328-compatible definitions */
855 #define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
856 #define SPIMCONT_ENABLE SPIMCONT_SPIMEN
857 /**********
858 *
859 * 0xFFFFF9xx -- UART
860 *
861 **********/
863 /*
864 * UART Status/Control Register
865 */
866 #define USTCNT_ADDR 0xfffff900
867 #define USTCNT WORD_REF(USTCNT_ADDR)
869 #define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
870 #define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
871 #define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
872 #define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
873 #define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
874 #define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
875 #define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
876 #define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
877 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
878 #define USTCNT_STOP 0x0200 /* Stop bit transmission */
879 #define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
880 #define USTCNT_PARITYEN 0x0800 /* Parity Enable */
881 #define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
882 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
883 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
884 #define USTCNT_UARTEN 0x8000 /* UART Enable */
886 /* 'EZ328-compatible definitions */
887 #define USTCNT_TXAE USTCNT_TXAVAILEN
888 #define USTCNT_TXHE USTCNT_TXHALFEN
889 #define USTCNT_TXEE USTCNT_TXEMPTYEN
890 #define USTCNT_RXRE USTCNT_RXREADYEN
891 #define USTCNT_RXHE USTCNT_RXHALFEN
892 #define USTCNT_RXFE USTCNT_RXFULLEN
893 #define USTCNT_CTSD USTCNT_CTSDELTAEN
894 #define USTCNT_ODD USTCNT_ODD_EVEN
895 #define USTCNT_PEN USTCNT_PARITYEN
896 #define USTCNT_CLKM USTCNT_CLKMODE
897 #define USTCNT_UEN USTCNT_UARTEN
899 /*
900 * UART Baud Control Register
901 */
902 #define UBAUD_ADDR 0xfffff902
903 #define UBAUD WORD_REF(UBAUD_ADDR)
905 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
906 #define UBAUD_PRESCALER_SHIFT 0
907 #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
908 #define UBAUD_DIVIDE_SHIFT 8
909 #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
910 #define UBAUD_GPIOSRC 0x1000 /* GPIO source */
911 #define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
912 #define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
913 #define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
915 /*
916 * UART Receiver Register
917 */
918 #define URX_ADDR 0xfffff904
919 #define URX WORD_REF(URX_ADDR)
921 #define URX_RXDATA_ADDR 0xfffff905
922 #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
924 #define URX_RXDATA_MASK 0x00ff /* Received data */
925 #define URX_RXDATA_SHIFT 0
926 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
927 #define URX_BREAK 0x0200 /* Break Detected */
928 #define URX_FRAME_ERROR 0x0400 /* Framing Error */
929 #define URX_OVRUN 0x0800 /* Serial Overrun */
930 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
931 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
932 #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
934 /*
935 * UART Transmitter Register
936 */
937 #define UTX_ADDR 0xfffff906
938 #define UTX WORD_REF(UTX_ADDR)
940 #define UTX_TXDATA_ADDR 0xfffff907
941 #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
943 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
944 #define UTX_TXDATA_SHIFT 0
945 #define UTX_CTS_DELTA 0x0100 /* CTS changed */
946 #define UTX_CTS_STATUS 0x0200 /* CTS State */
947 #define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
948 #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
949 #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
950 #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
951 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
953 /* 'EZ328-compatible definitions */
954 #define UTX_CTS_STAT UTX_CTS_STATUS
955 #define UTX_NOCTS UTX_IGNORE_CTS
957 /*
958 * UART Miscellaneous Register
959 */
960 #define UMISC_ADDR 0xfffff908
961 #define UMISC WORD_REF(UMISC_ADDR)
963 #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
964 #define UMISC_RX_POL 0x0008 /* Receive Polarity */
965 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
966 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
967 #define UMISC_RTS 0x0040 /* Set RTS status */
968 #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
969 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
970 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
971 #define UMISC_CLKSRC 0x4000 /* Clock Source */
974 /* generalization of uart control registers to support multiple ports: */
975 typedef volatile struct {
976 volatile unsigned short int ustcnt;
977 volatile unsigned short int ubaud;
978 union {
979 volatile unsigned short int w;
980 struct {
981 volatile unsigned char status;
982 volatile unsigned char rxdata;
983 } b;
984 } urx;
985 union {
986 volatile unsigned short int w;
987 struct {
988 volatile unsigned char status;
989 volatile unsigned char txdata;
990 } b;
991 } utx;
992 volatile unsigned short int umisc;
993 volatile unsigned short int pad1;
994 volatile unsigned short int pad2;
995 volatile unsigned short int pad3;
996 } __attribute__((packed)) m68328_uart;
999 /**********
1001 * 0xFFFFFAxx -- LCD Controller
1003 **********/
1005 /*
1006 * LCD Screen Starting Address Register
1007 */
1008 #define LSSA_ADDR 0xfffffa00
1009 #define LSSA LONG_REF(LSSA_ADDR)
1011 #define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
1013 /*
1014 * LCD Virtual Page Width Register
1015 */
1016 #define LVPW_ADDR 0xfffffa05
1017 #define LVPW BYTE_REF(LVPW_ADDR)
1019 /*
1020 * LCD Screen Width Register (not compatible with 'EZ328 !!!)
1021 */
1022 #define LXMAX_ADDR 0xfffffa08
1023 #define LXMAX WORD_REF(LXMAX_ADDR)
1025 #define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
1027 /*
1028 * LCD Screen Height Register
1029 */
1030 #define LYMAX_ADDR 0xfffffa0a
1031 #define LYMAX WORD_REF(LYMAX_ADDR)
1033 #define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
1035 /*
1036 * LCD Cursor X Position Register
1037 */
1038 #define LCXP_ADDR 0xfffffa18
1039 #define LCXP WORD_REF(LCXP_ADDR)
1041 #define LCXP_CC_MASK 0xc000 /* Cursor Control */
1042 #define LCXP_CC_TRAMSPARENT 0x0000
1043 #define LCXP_CC_BLACK 0x4000
1044 #define LCXP_CC_REVERSED 0x8000
1045 #define LCXP_CC_WHITE 0xc000
1046 #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
1048 /*
1049 * LCD Cursor Y Position Register
1050 */
1051 #define LCYP_ADDR 0xfffffa1a
1052 #define LCYP WORD_REF(LCYP_ADDR)
1054 #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
1056 /*
1057 * LCD Cursor Width and Heigth Register
1058 */
1059 #define LCWCH_ADDR 0xfffffa1c
1060 #define LCWCH WORD_REF(LCWCH_ADDR)
1062 #define LCWCH_CH_MASK 0x001f /* Cursor Height */
1063 #define LCWCH_CH_SHIFT 0
1064 #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
1065 #define LCWCH_CW_SHIFT 8
1067 /*
1068 * LCD Blink Control Register
1069 */
1070 #define LBLKC_ADDR 0xfffffa1f
1071 #define LBLKC BYTE_REF(LBLKC_ADDR)
1073 #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
1074 #define LBLKC_BD_SHIFT 0
1075 #define LBLKC_BKEN 0x80 /* Blink Enabled */
1077 /*
1078 * LCD Panel Interface Configuration Register
1079 */
1080 #define LPICF_ADDR 0xfffffa20
1081 #define LPICF BYTE_REF(LPICF_ADDR)
1083 #define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
1084 #define LPICF_GS_BW 0x00
1085 #define LPICF_GS_GRAY_4 0x01
1086 #define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
1087 #define LPICF_PBSIZ_1 0x00
1088 #define LPICF_PBSIZ_2 0x02
1089 #define LPICF_PBSIZ_4 0x04
1091 /*
1092 * LCD Polarity Configuration Register
1093 */
1094 #define LPOLCF_ADDR 0xfffffa21
1095 #define LPOLCF BYTE_REF(LPOLCF_ADDR)
1097 #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
1098 #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
1099 #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
1100 #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
1102 /*
1103 * LACD (LCD Alternate Crystal Direction) Rate Control Register
1104 */
1105 #define LACDRC_ADDR 0xfffffa23
1106 #define LACDRC BYTE_REF(LACDRC_ADDR)
1108 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
1109 #define LACDRC_ACD_SHIFT 0
1111 /*
1112 * LCD Pixel Clock Divider Register
1113 */
1114 #define LPXCD_ADDR 0xfffffa25
1115 #define LPXCD BYTE_REF(LPXCD_ADDR)
1117 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
1118 #define LPXCD_PCD_SHIFT 0
1120 /*
1121 * LCD Clocking Control Register
1122 */
1123 #define LCKCON_ADDR 0xfffffa27
1124 #define LCKCON BYTE_REF(LCKCON_ADDR)
1126 #define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
1127 #define LCKCON_DWIDTH 0x02 /* Display Memory Width */
1128 #define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
1129 #define LCKCON_DWS_SHIFT 2
1130 #define LCKCON_DMA16 0x40 /* DMA burst length */
1131 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
1133 /* 'EZ328-compatible definitions */
1134 #define LCKCON_DW_MASK LCKCON_DWS_MASK
1135 #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
1137 /*
1138 * LCD Last Buffer Address Register
1139 */
1140 #define LLBAR_ADDR 0xfffffa29
1141 #define LLBAR BYTE_REF(LLBAR_ADDR)
1143 #define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
1144 #define LLBAR_LBAR_SHIFT 0
1146 /*
1147 * LCD Octet Terminal Count Register
1148 */
1149 #define LOTCR_ADDR 0xfffffa2b
1150 #define LOTCR BYTE_REF(LOTCR_ADDR)
1152 /*
1153 * LCD Panning Offset Register
1154 */
1155 #define LPOSR_ADDR 0xfffffa2d
1156 #define LPOSR BYTE_REF(LPOSR_ADDR)
1158 #define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
1159 #define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
1160 #define LPOSR_POS_SHIFT 0
1162 /*
1163 * LCD Frame Rate Control Modulation Register
1164 */
1165 #define LFRCM_ADDR 0xfffffa31
1166 #define LFRCM BYTE_REF(LFRCM_ADDR)
1168 #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
1169 #define LFRCM_YMOD_SHIFT 0
1170 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
1171 #define LFRCM_XMOD_SHIFT 4
1173 /*
1174 * LCD Gray Palette Mapping Register
1175 */
1176 #define LGPMR_ADDR 0xfffffa32
1177 #define LGPMR WORD_REF(LGPMR_ADDR)
1179 #define LGPMR_GLEVEL3_MASK 0x000f
1180 #define LGPMR_GLEVEL3_SHIFT 0
1181 #define LGPMR_GLEVEL2_MASK 0x00f0
1182 #define LGPMR_GLEVEL2_SHIFT 4
1183 #define LGPMR_GLEVEL0_MASK 0x0f00
1184 #define LGPMR_GLEVEL0_SHIFT 8
1185 #define LGPMR_GLEVEL1_MASK 0xf000
1186 #define LGPMR_GLEVEL1_SHIFT 12
1188 /**********
1190 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1192 **********/
1194 /*
1195 * RTC Hours Minutes and Seconds Register
1196 */
1197 #define RTCTIME_ADDR 0xfffffb00
1198 #define RTCTIME LONG_REF(RTCTIME_ADDR)
1200 #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1201 #define RTCTIME_SECONDS_SHIFT 0
1202 #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1203 #define RTCTIME_MINUTES_SHIFT 16
1204 #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1205 #define RTCTIME_HOURS_SHIFT 24
1207 /*
1208 * RTC Alarm Register
1209 */
1210 #define RTCALRM_ADDR 0xfffffb04
1211 #define RTCALRM LONG_REF(RTCALRM_ADDR)
1213 #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1214 #define RTCALRM_SECONDS_SHIFT 0
1215 #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1216 #define RTCALRM_MINUTES_SHIFT 16
1217 #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1218 #define RTCALRM_HOURS_SHIFT 24
1220 /*
1221 * RTC Control Register
1222 */
1223 #define RTCCTL_ADDR 0xfffffb0c
1224 #define RTCCTL WORD_REF(RTCCTL_ADDR)
1226 #define RTCCTL_384 0x0020 /* Crystal Selection */
1227 #define RTCCTL_ENABLE 0x0080 /* RTC Enable */
1229 /* 'EZ328-compatible definitions */
1230 #define RTCCTL_XTL RTCCTL_384
1231 #define RTCCTL_EN RTCCTL_ENABLE
1233 /*
1234 * RTC Interrupt Status Register
1235 */
1236 #define RTCISR_ADDR 0xfffffb0e
1237 #define RTCISR WORD_REF(RTCISR_ADDR)
1239 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1240 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1241 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1242 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1243 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1245 /*
1246 * RTC Interrupt Enable Register
1247 */
1248 #define RTCIENR_ADDR 0xfffffb10
1249 #define RTCIENR WORD_REF(RTCIENR_ADDR)
1251 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1252 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1253 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1254 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1255 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1257 /*
1258 * Stopwatch Minutes Register
1259 */
1260 #define STPWCH_ADDR 0xfffffb12
1261 #define STPWCH WORD_REF(STPWCH)
1263 #define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
1264 #define SPTWCH_CNT_SHIFT 0
1266 #endif /* _MC68328_H_ */