ia64/linux-2.6.18-xen.hg

view include/asm-m68k/q40_master.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * Q40 master Chip Control
3 * RTC stuff merged for compactnes..
4 */
6 #ifndef _Q40_MASTER_H
7 #define _Q40_MASTER_H
9 #include <asm/raw_io.h>
12 #define q40_master_addr 0xff000000
14 #define IIRQ_REG 0x0 /* internal IRQ reg */
15 #define EIRQ_REG 0x4 /* external ... */
16 #define KEYCODE_REG 0x1c /* value of received scancode */
17 #define DISPLAY_CONTROL_REG 0x18
18 #define FRAME_CLEAR_REG 0x24
19 #define LED_REG 0x30
21 #define Q40_LED_ON() master_outb(1,LED_REG)
22 #define Q40_LED_OFF() master_outb(0,LED_REG)
24 #define INTERRUPT_REG IIRQ_REG /* "native" ints */
25 #define KEY_IRQ_ENABLE_REG 0x08 /**/
26 #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */
28 #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */
29 #define SAMPLE_RATE_REG 0x2c
30 #define SAMPLE_CLEAR_REG 0x28
31 #define SAMPLE_LOW 0x00
32 #define SAMPLE_HIGH 0x01
34 #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */
36 #if 0
37 #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */
38 #endif
39 #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */
42 #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_)
43 #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_)
45 /* RTC defines */
47 #define Q40_RTC_BASE (0xff021ffc)
49 #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0))
50 #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4))
51 #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8))
52 #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12))
53 #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16))
54 #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20))
55 #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24))
56 #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28))
58 /* some control bits */
59 #define Q40_RTC_READ 64 /* prepare for reading */
60 #define Q40_RTC_WRITE 128
62 /* define some Q40 specific ints */
63 #include "q40ints.h"
65 /* misc defs */
66 #define DAC_LEFT ((unsigned char *)0xff008000)
67 #define DAC_RIGHT ((unsigned char *)0xff008004)
69 #endif /* _Q40_MASTER_H */