ia64/linux-2.6.18-xen.hg

view include/asm-m68k/macints.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 ** macints.h -- Macintosh Linux interrupt handling structs and prototypes
3 **
4 ** Copyright 1997 by Michael Schmitz
5 **
6 ** This file is subject to the terms and conditions of the GNU General Public
7 ** License. See the file COPYING in the main directory of this archive
8 ** for more details.
9 **
10 */
12 #ifndef _ASM_MACINTS_H_
13 #define _ASM_MACINTS_H_
15 #include <asm/irq.h>
17 /* Setting this prints debugging info for unclaimed interrupts */
19 #define DEBUG_SPURIOUS
21 /* Setting this prints debugging info on each autovector interrupt */
23 /* #define DEBUG_IRQS */
25 /* Setting this prints debugging info on each Nubus interrupt */
27 /* #define DEBUG_NUBUS_INT */
29 /* Setting this prints debugging info on irqs as they enabled and disabled. */
31 /* #define DEBUG_IRQUSE */
33 /*
34 * Base IRQ number for all Mac68K interrupt sources. Each source
35 * has eight indexes (base -> base+7).
36 */
38 #define VIA1_SOURCE_BASE 8
39 #define VIA2_SOURCE_BASE 16
40 #define MAC_SCC_SOURCE_BASE 24
41 #define PSC3_SOURCE_BASE 24
42 #define PSC4_SOURCE_BASE 32
43 #define PSC5_SOURCE_BASE 40
44 #define PSC6_SOURCE_BASE 48
45 #define NUBUS_SOURCE_BASE 56
46 #define BABOON_SOURCE_BASE 64
48 /*
49 * Maximum IRQ number is BABOON_SOURCE_BASE + 7,
50 * giving us IRQs up through 71
51 */
53 #define NUM_MAC_SOURCES 72
55 /*
56 * clean way to separate IRQ into its source and index
57 */
59 #define IRQ_SRC(irq) (irq >> 3)
60 #define IRQ_IDX(irq) (irq & 7)
62 /* VIA1 interrupts */
63 #define IRQ_VIA1_0 (8) /* one second int. */
64 #define IRQ_VIA1_1 (9) /* VBlank int. */
65 #define IRQ_MAC_VBL IRQ_VIA1_1
66 #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
67 #define IRQ_MAC_ADB IRQ_VIA1_2
68 #define IRQ_MAC_ADB_SR IRQ_VIA1_2
69 #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
70 #define IRQ_MAC_ADB_SD IRQ_VIA1_3
71 #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
72 #define IRQ_MAC_ADB_CL IRQ_VIA1_4
73 #define IRQ_VIA1_5 (13)
74 #define IRQ_MAC_TIMER_2 IRQ_VIA1_5
75 #define IRQ_VIA1_6 (14)
76 #define IRQ_MAC_TIMER_1 IRQ_VIA1_6
77 #define IRQ_VIA1_7 (15)
79 /* VIA2/RBV interrupts */
80 #define IRQ_VIA2_0 (16)
81 #define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
82 #define IRQ_VIA2_1 (17)
83 #define IRQ_MAC_NUBUS IRQ_VIA2_1
84 #define IRQ_VIA2_2 (18)
85 #define IRQ_VIA2_3 (19)
86 #define IRQ_MAC_SCSI IRQ_VIA2_3
87 #define IRQ_VIA2_4 (20)
88 #define IRQ_VIA2_5 (21)
89 #define IRQ_VIA2_6 (22)
90 #define IRQ_VIA2_7 (23)
92 /* Level 3 (PSC, AV Macs only) interrupts */
93 #define IRQ_PSC3_0 (24)
94 #define IRQ_MAC_MACE IRQ_PSC3_0
95 #define IRQ_PSC3_1 (25)
96 #define IRQ_PSC3_2 (26)
97 #define IRQ_PSC3_3 (27)
99 /* Level 4 (SCC) interrupts */
100 #define IRQ_SCC (32)
101 #define IRQ_SCCA (33)
102 #define IRQ_SCCB (34)
103 #if 0 /* FIXME: are there multiple interrupt conditions on the SCC ?? */
104 /* SCC interrupts */
105 #define IRQ_SCCB_TX (32)
106 #define IRQ_SCCB_STAT (33)
107 #define IRQ_SCCB_RX (34)
108 #define IRQ_SCCB_SPCOND (35)
109 #define IRQ_SCCA_TX (36)
110 #define IRQ_SCCA_STAT (37)
111 #define IRQ_SCCA_RX (38)
112 #define IRQ_SCCA_SPCOND (39)
113 #endif
115 /* Level 4 (PSC, AV Macs only) interrupts */
116 #define IRQ_PSC4_0 (32)
117 #define IRQ_PSC4_1 (33)
118 #define IRQ_PSC4_2 (34)
119 #define IRQ_PSC4_3 (35)
120 #define IRQ_MAC_MACE_DMA IRQ_PSC4_3
122 /* Level 5 (PSC, AV Macs only) interrupts */
123 #define IRQ_PSC5_0 (40)
124 #define IRQ_PSC5_1 (41)
125 #define IRQ_PSC5_2 (42)
126 #define IRQ_PSC5_3 (43)
128 /* Level 6 (PSC, AV Macs only) interrupts */
129 #define IRQ_PSC6_0 (48)
130 #define IRQ_PSC6_1 (49)
131 #define IRQ_PSC6_2 (50)
132 #define IRQ_PSC6_3 (51)
134 /* Nubus interrupts (cascaded to VIA2) */
135 #define IRQ_NUBUS_9 (56)
136 #define IRQ_NUBUS_A (57)
137 #define IRQ_NUBUS_B (58)
138 #define IRQ_NUBUS_C (59)
139 #define IRQ_NUBUS_D (60)
140 #define IRQ_NUBUS_E (61)
141 #define IRQ_NUBUS_F (62)
143 /* Baboon interrupts (cascaded to nubus slot $C) */
144 #define IRQ_BABOON_0 (64)
145 #define IRQ_BABOON_1 (65)
146 #define IRQ_BABOON_2 (66)
147 #define IRQ_BABOON_3 (67)
149 #define SLOT2IRQ(x) (x + 47)
150 #define IRQ2SLOT(x) (x - 47)
152 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
153 #define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
155 #endif /* asm/macints.h */