ia64/linux-2.6.18-xen.hg

view include/asm-m68k/mac_via.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * 6522 Versatile Interface Adapter (VIA)
3 *
4 * There are two of these on the Mac II. Some IRQ's are vectored
5 * via them as are assorted bits and bobs - eg rtc, adb. The picture
6 * is a bit incomplete as the Mac documentation doesn't cover this well
7 */
9 #ifndef _ASM_MAC_VIA_H_
10 #define _ASM_MAC_VIA_H_
12 /*
13 * Base addresses for the VIAs. There are two in every machine,
14 * although on some machines the second is an RBV or an OSS.
15 * The OSS is different enough that it's handled separately.
16 *
17 * Do not use these values directly; use the via1 and via2 variables
18 * instead (and don't forget to check rbv_present when using via2!)
19 */
21 #define VIA1_BASE (0x50F00000)
22 #define VIA2_BASE (0x50F02000)
23 #define RBV_BASE (0x50F26000)
25 /*
26 * Not all of these are true post MacII I think.
27 * CSA: probably the ones CHRP marks as 'unused' change purposes
28 * when the IWM becomes the SWIM.
29 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
30 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
31 *
32 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the
33 * following changes for IIfx:
34 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
35 * Also, "All of the functionality of VIA2 has been moved to other chips".
36 */
38 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
39 * [CHRP] SCC WREQ: Reflects the state of the
40 * Wait/Request pins from the SCC.
41 * [Macintosh Family Hardware]
42 * as CHRP on SE/30,II,IIx,IIcx,IIci.
43 * on IIfx, "0 means an active request"
44 */
45 #define VIA1A_vRev8 0x40 /* Revision 8 board ???
46 * [CHRP] En WaitReqB: Lets the WaitReq_L
47 * signal from port B of the SCC appear on
48 * the PA7 input pin. Output.
49 * [Macintosh Family] On the SE/30, this
50 * is the bit to flip screen buffers.
51 * 0=alternate, 1=main.
52 * on II,IIx,IIcx,IIci,IIfx this is a bit
53 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
54 */
55 #define VIA1A_vHeadSel 0x20 /* Head select for IWM.
56 * [CHRP] unused.
57 * [Macintosh Family] "Floppy disk
58 * state-control line SEL" on all but IIfx
59 */
60 #define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
61 * this bit enables the "Overlay" address
62 * map in the address decoders as it is on
63 * reset for mapping the ROM over the reset
64 * vector. 1=use overlay map.
65 * On the IIci,IIfx it is another bit of the
66 * CPU ID: 0=normal IIci, 1=IIci with parity
67 * feature or IIfx.
68 * [CHRP] En WaitReqA: Lets the WaitReq_L
69 * signal from port A of the SCC appear
70 * on the PA7 input pin (CHRP). Output.
71 * [MkLinux] "Drive Select"
72 * (with 0x20 being 'disk head select')
73 */
74 #define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
75 * 1: select the external serial clock to
76 * drive the SCC's /RTxCA pin.
77 * 0: Select the 3.6864MHz clock to drive
78 * the SCC cell.
79 * [Macintosh Family] Correct on all but IIfx
80 */
82 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
83 * on Macs which had the PWM sound hardware. Reserved on newer models.
84 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
85 * bit 2: 1=IIci, 0=IIfx
86 * bit 1: 1 on both IIci and IIfx.
87 * MkLinux sez bit 0 is 'burnin flag' in this case.
88 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
89 * inputs, these bits will read 0.
90 */
91 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
92 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
93 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
94 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
95 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
97 /* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
98 * CHRP offers no info. */
99 #define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
100 * PWM hardware) 0=enabled.
101 * Also, on IIci w/parity, shows parity error
102 * 0=error, 1=OK. */
103 #define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
104 * On SE/30, vertical sync interrupt enable.
105 * 0=enabled. This vSync interrupt shows up
106 * as a slot $E interrupt. */
107 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
108 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
109 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
110 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
111 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
112 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
114 /* MkLinux defines the following "VIA1 Register B contents where they
115 * differ from standard VIA1". From the naming scheme, we assume they
116 * correspond to a VIA work-alike named 'EVR'. */
117 #define EVRB_XCVR 0x08 /* XCVR_SESSION* */
118 #define EVRB_FULL 0x10 /* VIA_FULL */
119 #define EVRB_SYSES 0x20 /* SYS_SESSION */
120 #define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
121 #define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
122 #define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
123 #define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
125 /*
126 * VIA2 A register is the interrupt lines raised off the nubus
127 * slots.
128 * The below info is from 'Macintosh Family Hardware.'
129 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
130 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
131 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
132 * Perhaps OSS uses vRAM1 and vRAM2 for ADB.
133 */
135 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
136 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
137 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
138 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
139 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
140 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
141 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
142 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
144 /* RAM size bits decoded as follows:
145 * bit1 bit0 size of ICs in bank A
146 * 0 0 256 kbit
147 * 0 1 1 Mbit
148 * 1 0 4 Mbit
149 * 1 1 16 Mbit
150 */
152 /*
153 * Register B has the fun stuff in it
154 */
156 #define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
157 * timer T1.
158 * on IIci, parity test: 0=test mode.
159 * [MkLinux] RBV_PARODD: 1=odd,0=even. */
160 #define VIA2B_vSndJck 0x40 /* External sound jack status.
161 * 0=plug is inserted. On SE/30, always 0 */
162 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
163 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
164 #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
165 * on II, AMU/PMMU control.
166 * if AMU, 0=24bit to 32bit translation
167 * if PMMU, 1=PMMU is accessing page table.
168 * on SE/30 tied low.
169 * on IIx,IIcx,IIfx, unused.
170 * on IIci/RBV, cache control. 0=flush cache.
171 */
172 #define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
173 * on SE/30 this signal sent to PDS card. */
174 #define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
175 * on SE/30 sent to PDS card. */
176 #define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
177 * on others, 0=disable processor's instruction
178 * and data caches. */
180 /* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
181 * Another example of a valid function that has no ROM support is the use
182 * of the alternate video page for page-flipping animation. Since there
183 * is no ROM call to flip pages, it is necessary to go play with the
184 * right bit in the VIA chip (6522 Versatile Interface Adapter).
185 * [CSA: don't know which one this is, but it's one of 'em!]
186 */
188 /*
189 * 6522 registers - see databook.
190 * CSA: Assignments for VIA1 confirmed from CHRP spec.
191 */
193 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
194 /* Note: 15 VIA regs, 8 RBV regs */
196 #define vBufB 0x0000 /* [VIA/RBV] Register B */
197 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
198 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
199 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
200 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
201 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
202 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
203 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
204 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
205 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
206 #define vSR 0x1400 /* [VIA only] Shift register. */
207 #define vACR 0x1600 /* [VIA only] Auxilary control register. */
208 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
209 /* CHRP sez never ever to *write* this.
210 * Mac family says never to *change* this.
211 * In fact we need to initialize it once at start. */
212 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
213 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
214 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
216 /* The RBV only decodes the bottom eight address lines; the VIA doesn't
217 * decode the bottom eight -- so vBufB | rBufB will always get you BufB */
218 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
219 * BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
220 * to matter. In fact *all* of the top 8 bits seem to matter;
221 * setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
222 * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
223 */
225 #define rBufB 0x0000 /* [VIA/RBV] Register B */
226 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
227 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
228 #define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
229 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
230 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
231 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
232 #define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
233 #define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */
235 /*
236 * Video monitor parameters, for rMonP:
237 */
238 #define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
239 #define RBV_MONID 0x38 /* monitor type, as below. */
240 #define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
241 /* Supported monitor types: */
242 #define MON_15BW (1<<3) /* 15" BW portrait. */
243 #define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */
244 #define MON_15RGB (5<<3) /* 15" RGB portrait. */
245 #define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */
246 #define MON_NONE (7<<3) /* No monitor attached. */
248 /* To clarify IER manipulations */
249 #define IER_SET_BIT(b) (0x80 | (1<<(b)) )
250 #define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
252 #ifndef __ASSEMBLY__
254 extern volatile __u8 *via1,*via2;
255 extern int rbv_present,via_alt_mapping;
256 extern __u8 rbv_clear;
258 static inline int rbv_set_video_bpp(int bpp)
259 {
260 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
261 if (!rbv_present || val<0) return -1;
262 via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val;
263 return 0;
264 }
266 #endif /* __ASSEMBLY__ */
268 #endif /* _ASM_MAC_VIA_H_ */