ia64/linux-2.6.18-xen.hg

view include/asm-m68k/dvma.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /* $Id: dvma.h,v 1.4 1999/03/27 20:23:41 tsbogend Exp $
2 * include/asm-m68k/dma.h
3 *
4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
5 *
6 * Hacked to fit Sun3x needs by Thomas Bogendoerfer
7 */
9 #ifndef __M68K_DVMA_H
10 #define __M68K_DVMA_H
13 #define DVMA_PAGE_SHIFT 13
14 #define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
15 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
16 #define DVMA_PAGE_ALIGN(addr) (((addr)+DVMA_PAGE_SIZE-1)&DVMA_PAGE_MASK)
18 extern void dvma_init(void);
19 extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
20 int len);
22 #define dvma_malloc(x) dvma_malloc_align(x, 0)
23 #define dvma_map(x, y) dvma_map_align(x, y, 0)
24 #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
25 #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
26 extern unsigned long dvma_map_align(unsigned long kaddr, int len,
27 int align);
28 extern void *dvma_malloc_align(unsigned long len, unsigned long align);
30 extern void dvma_unmap(void *baddr);
31 extern void dvma_free(void *vaddr);
34 #ifdef CONFIG_SUN3
35 /* sun3 dvma page support */
37 /* memory and pmegs potentially reserved for dvma */
38 #define DVMA_PMEG_START 10
39 #define DVMA_PMEG_END 16
40 #define DVMA_START 0xf00000
41 #define DVMA_END 0xfe0000
42 #define DVMA_SIZE (DVMA_END-DVMA_START)
43 #define IOMMU_TOTAL_ENTRIES 128
44 #define IOMMU_ENTRIES 120
46 /* empirical kludge -- dvma regions only seem to work right on 0x10000
47 byte boundaries */
48 #define DVMA_REGION_SIZE 0x10000
49 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
50 ~(DVMA_REGION_SIZE-1))
52 /* virt <-> phys conversions */
53 #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
54 #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
55 #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
56 #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
57 #define dvma_vtob(x) dvma_vtop(x)
58 #define dvma_btov(x) dvma_ptov(x)
60 static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
61 int len)
62 {
63 return 0;
64 }
66 extern unsigned long dvma_page(unsigned long kaddr, unsigned long vaddr);
68 #else /* Sun3x */
70 /* sun3x dvma page support */
72 #define DVMA_START 0x0
73 #define DVMA_END 0xf00000
74 #define DVMA_SIZE (DVMA_END-DVMA_START)
75 #define IOMMU_TOTAL_ENTRIES 2048
76 /* the prom takes the top meg */
77 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
79 #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
80 #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
82 extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
86 /* everything below this line is specific to dma used for the onboard
87 ESP scsi on sun3x */
89 /* Structure to describe the current status of DMA registers on the Sparc */
90 struct sparc_dma_registers {
91 __volatile__ unsigned long cond_reg; /* DMA condition register */
92 __volatile__ unsigned long st_addr; /* Start address of this transfer */
93 __volatile__ unsigned long cnt; /* How many bytes to transfer */
94 __volatile__ unsigned long dma_test; /* DMA test register */
95 };
97 /* DVMA chip revisions */
98 enum dvma_rev {
99 dvmarev0,
100 dvmaesc1,
101 dvmarev1,
102 dvmarev2,
103 dvmarev3,
104 dvmarevplus,
105 dvmahme
106 };
108 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
110 /* Linux DMA information structure, filled during probe. */
111 struct Linux_SBus_DMA {
112 struct Linux_SBus_DMA *next;
113 struct linux_sbus_device *SBus_dev;
114 struct sparc_dma_registers *regs;
116 /* Status, misc info */
117 int node; /* Prom node for this DMA device */
118 int running; /* Are we doing DMA now? */
119 int allocated; /* Are we "owned" by anyone yet? */
121 /* Transfer information. */
122 unsigned long addr; /* Start address of current transfer */
123 int nbytes; /* Size of current transfer */
124 int realbytes; /* For splitting up large transfers, etc. */
126 /* DMA revision */
127 enum dvma_rev revision;
128 };
130 extern struct Linux_SBus_DMA *dma_chain;
132 /* Broken hardware... */
133 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
134 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
136 /* Fields in the cond_reg register */
137 /* First, the version identification bits */
138 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
139 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
140 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
141 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
142 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
143 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
144 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
146 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
147 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
148 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
149 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
150 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
151 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
152 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
153 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
154 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
155 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
156 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
157 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
158 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
159 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
160 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
161 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
162 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
163 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
164 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
165 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
166 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
167 #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
168 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
169 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
170 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
171 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
172 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
173 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
174 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
175 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
176 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
177 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
178 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
179 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
180 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
181 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
182 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
184 /* Values describing the burst-size property from the PROM */
185 #define DMA_BURST1 0x01
186 #define DMA_BURST2 0x02
187 #define DMA_BURST4 0x04
188 #define DMA_BURST8 0x08
189 #define DMA_BURST16 0x10
190 #define DMA_BURST32 0x20
191 #define DMA_BURST64 0x40
192 #define DMA_BURSTBITS 0x7f
194 /* Determine highest possible final transfer address given a base */
195 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
197 /* Yes, I hack a lot of elisp in my spare time... */
198 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
199 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
200 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
201 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
202 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
203 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
204 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
205 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
206 #define DMA_BEGINDMA_W(regs) \
207 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
208 #define DMA_BEGINDMA_R(regs) \
209 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
211 /* For certain DMA chips, we need to disable ints upon irq entry
212 * and turn them back on when we are done. So in any ESP interrupt
213 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
214 * when leaving the handler. You have been warned...
215 */
216 #define DMA_IRQ_ENTRY(dma, dregs) do { \
217 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
218 } while (0)
220 #define DMA_IRQ_EXIT(dma, dregs) do { \
221 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
222 } while(0)
224 /* Reset the friggin' thing... */
225 #define DMA_RESET(dma) do { \
226 struct sparc_dma_registers *regs = dma->regs; \
227 /* Let the current FIFO drain itself */ \
228 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
229 /* Reset the logic */ \
230 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
231 __delay(400); /* let the bits set ;) */ \
232 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
233 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
234 /* Enable FAST transfers if available */ \
235 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
236 dma->running = 0; \
237 } while(0)
240 #endif /* !CONFIG_SUN3 */
242 #endif /* !(__M68K_DVMA_H) */