ia64/linux-2.6.18-xen.hg

view include/asm-m32r/irq.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 #ifdef __KERNEL__
2 #ifndef _ASM_M32R_IRQ_H
3 #define _ASM_M32R_IRQ_H
6 #if defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_USRV)
7 /*
8 * IRQ definitions for M32700UT
9 * M32700 Chip: 64 interrupts
10 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
11 */
12 #define M32700UT_NUM_CPU_IRQ (64)
13 #define M32700UT_NUM_PLD_IRQ (32)
14 #define M32700UT_IRQ_BASE 0
15 #define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
16 #define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
18 #define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
19 #elif defined(CONFIG_PLAT_M32700UT)
20 /*
21 * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
22 * M32700 Chip: 64 interrupts
23 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
24 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
25 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
26 */
27 #define M32700UT_NUM_CPU_IRQ (64)
28 #define M32700UT_NUM_PLD_IRQ (32)
29 #define M32700UT_NUM_LCD_PLD_IRQ (32)
30 #define M32700UT_NUM_LAN_PLD_IRQ (32)
31 #define M32700UT_IRQ_BASE 0
32 #define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
33 #define M32700UT_PLD_IRQ_BASE \
34 (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
35 #define M32700UT_LCD_PLD_IRQ_BASE \
36 (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
37 #define M32700UT_LAN_PLD_IRQ_BASE \
38 (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
40 #define NR_IRQS \
41 (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
42 + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
43 #elif defined(CONFIG_PLAT_OPSPUT)
44 /*
45 * IRQ definitions for OPSPUT + M32R-LAN
46 * OPSP Chip: 64 interrupts
47 * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
48 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
49 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
50 */
51 #define OPSPUT_NUM_CPU_IRQ (64)
52 #define OPSPUT_NUM_PLD_IRQ (32)
53 #define OPSPUT_NUM_LCD_PLD_IRQ (32)
54 #define OPSPUT_NUM_LAN_PLD_IRQ (32)
55 #define OPSPUT_IRQ_BASE 0
56 #define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
57 #define OPSPUT_PLD_IRQ_BASE \
58 (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
59 #define OPSPUT_LCD_PLD_IRQ_BASE \
60 (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
61 #define OPSPUT_LAN_PLD_IRQ_BASE \
62 (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
64 #define NR_IRQS \
65 (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
66 + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
68 #elif defined(CONFIG_PLAT_M32104UT)
69 /*
70 * IRQ definitions for M32104UT
71 * M32104 Chip: 64 interrupts
72 * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
73 */
74 #define M32104UT_NUM_CPU_IRQ (64)
75 #define M32104UT_NUM_PLD_IRQ (32)
76 #define M32104UT_IRQ_BASE 0
77 #define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
78 #define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
80 #define NR_IRQS \
81 (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
83 #else
84 #define NR_IRQS 64
85 #endif
87 #define irq_canonicalize(irq) (irq)
89 #endif /* _ASM_M32R_IRQ_H */
90 #endif /* __KERNEL__ */