ia64/linux-2.6.18-xen.hg

view include/asm-i386/processor.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <asm/msr.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
27 struct desc_struct {
28 unsigned long a,b;
29 };
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36 /*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
42 /*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
48 struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 char fdiv_bug;
65 char f00f_bug;
66 char coma_bug;
67 char pad0;
68 int x86_power;
69 unsigned long loops_per_jiffy;
70 #ifdef CONFIG_SMP
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
72 #endif
73 unsigned char x86_max_cores; /* cpuid returned max cores value */
74 unsigned char apicid;
75 #ifdef CONFIG_SMP
76 unsigned char booted_cores; /* number of cores as seen by OS */
77 __u8 phys_proc_id; /* Physical processor id. */
78 __u8 cpu_core_id; /* Core id */
79 #endif
80 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
82 #define X86_VENDOR_INTEL 0
83 #define X86_VENDOR_CYRIX 1
84 #define X86_VENDOR_AMD 2
85 #define X86_VENDOR_UMC 3
86 #define X86_VENDOR_NEXGEN 4
87 #define X86_VENDOR_CENTAUR 5
88 #define X86_VENDOR_RISE 6
89 #define X86_VENDOR_TRANSMETA 7
90 #define X86_VENDOR_NSC 8
91 #define X86_VENDOR_NUM 9
92 #define X86_VENDOR_UNKNOWN 0xff
94 /*
95 * capabilities of CPUs
96 */
98 extern struct cpuinfo_x86 boot_cpu_data;
99 extern struct cpuinfo_x86 new_cpu_data;
100 extern struct tss_struct doublefault_tss;
101 DECLARE_PER_CPU(struct tss_struct, init_tss);
103 #ifdef CONFIG_SMP
104 extern struct cpuinfo_x86 cpu_data[];
105 #define current_cpu_data cpu_data[smp_processor_id()]
106 #else
107 #define cpu_data (&boot_cpu_data)
108 #define current_cpu_data boot_cpu_data
109 #endif
111 extern int cpu_llc_id[NR_CPUS];
112 extern char ignore_fpu_irq;
114 extern void identify_cpu(struct cpuinfo_x86 *);
115 extern void print_cpu_info(struct cpuinfo_x86 *);
116 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
117 extern unsigned short num_cache_leaves;
119 #ifdef CONFIG_X86_HT
120 extern void detect_ht(struct cpuinfo_x86 *c);
121 #else
122 static inline void detect_ht(struct cpuinfo_x86 *c) {}
123 #endif
125 /*
126 * EFLAGS bits
127 */
128 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
129 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
130 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
131 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
132 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
133 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
134 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
135 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
136 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
137 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
138 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
139 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
140 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
141 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
142 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
143 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
144 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
146 /*
147 * Generic CPUID function
148 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
149 * resulting in stale register contents being returned.
150 */
151 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
152 {
153 __asm__("cpuid"
154 : "=a" (*eax),
155 "=b" (*ebx),
156 "=c" (*ecx),
157 "=d" (*edx)
158 : "0" (op), "c"(0));
159 }
161 /* Some CPUID calls want 'count' to be placed in ecx */
162 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
163 int *edx)
164 {
165 __asm__("cpuid"
166 : "=a" (*eax),
167 "=b" (*ebx),
168 "=c" (*ecx),
169 "=d" (*edx)
170 : "0" (op), "c" (count));
171 }
173 /*
174 * CPUID functions returning a single datum
175 */
176 static inline unsigned int cpuid_eax(unsigned int op)
177 {
178 unsigned int eax;
180 __asm__("cpuid"
181 : "=a" (eax)
182 : "0" (op)
183 : "bx", "cx", "dx");
184 return eax;
185 }
186 static inline unsigned int cpuid_ebx(unsigned int op)
187 {
188 unsigned int eax, ebx;
190 __asm__("cpuid"
191 : "=a" (eax), "=b" (ebx)
192 : "0" (op)
193 : "cx", "dx" );
194 return ebx;
195 }
196 static inline unsigned int cpuid_ecx(unsigned int op)
197 {
198 unsigned int eax, ecx;
200 __asm__("cpuid"
201 : "=a" (eax), "=c" (ecx)
202 : "0" (op)
203 : "bx", "dx" );
204 return ecx;
205 }
206 static inline unsigned int cpuid_edx(unsigned int op)
207 {
208 unsigned int eax, edx;
210 __asm__("cpuid"
211 : "=a" (eax), "=d" (edx)
212 : "0" (op)
213 : "bx", "cx");
214 return edx;
215 }
217 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
219 /*
220 * Intel CPU features in CR4
221 */
222 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
223 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
224 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
225 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
226 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
227 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
228 #define X86_CR4_MCE 0x0040 /* Machine check enable */
229 #define X86_CR4_PGE 0x0080 /* enable global pages */
230 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
231 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
232 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
234 /*
235 * Save the cr4 feature set we're using (ie
236 * Pentium 4MB enable and PPro Global page
237 * enable), so that any CPU's that boot up
238 * after us can get the correct flags.
239 */
240 extern unsigned long mmu_cr4_features;
242 static inline void set_in_cr4 (unsigned long mask)
243 {
244 unsigned cr4;
245 mmu_cr4_features |= mask;
246 cr4 = read_cr4();
247 cr4 |= mask;
248 write_cr4(cr4);
249 }
251 static inline void clear_in_cr4 (unsigned long mask)
252 {
253 unsigned cr4;
254 mmu_cr4_features &= ~mask;
255 cr4 = read_cr4();
256 cr4 &= ~mask;
257 write_cr4(cr4);
258 }
260 /*
261 * NSC/Cyrix CPU configuration register indexes
262 */
264 #define CX86_PCR0 0x20
265 #define CX86_GCR 0xb8
266 #define CX86_CCR0 0xc0
267 #define CX86_CCR1 0xc1
268 #define CX86_CCR2 0xc2
269 #define CX86_CCR3 0xc3
270 #define CX86_CCR4 0xe8
271 #define CX86_CCR5 0xe9
272 #define CX86_CCR6 0xea
273 #define CX86_CCR7 0xeb
274 #define CX86_PCR1 0xf0
275 #define CX86_DIR0 0xfe
276 #define CX86_DIR1 0xff
277 #define CX86_ARR_BASE 0xc4
278 #define CX86_RCR_BASE 0xdc
280 /*
281 * NSC/Cyrix CPU indexed register access macros
282 */
284 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
286 #define setCx86(reg, data) do { \
287 outb((reg), 0x22); \
288 outb((data), 0x23); \
289 } while (0)
291 /* Stop speculative execution */
292 static inline void sync_core(void)
293 {
294 int tmp;
295 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
296 }
298 static inline void __monitor(const void *eax, unsigned long ecx,
299 unsigned long edx)
300 {
301 /* "monitor %eax,%ecx,%edx;" */
302 asm volatile(
303 ".byte 0x0f,0x01,0xc8;"
304 : :"a" (eax), "c" (ecx), "d"(edx));
305 }
307 static inline void __mwait(unsigned long eax, unsigned long ecx)
308 {
309 /* "mwait %eax,%ecx;" */
310 asm volatile(
311 ".byte 0x0f,0x01,0xc9;"
312 : :"a" (eax), "c" (ecx));
313 }
315 /* from system description table in BIOS. Mostly for MCA use, but
316 others may find it useful. */
317 extern unsigned int machine_id;
318 extern unsigned int machine_submodel_id;
319 extern unsigned int BIOS_revision;
320 extern unsigned int mca_pentium_flag;
322 /* Boot loader type from the setup header */
323 extern int bootloader_type;
325 /*
326 * User space process size: 3GB (default).
327 */
328 #define TASK_SIZE (PAGE_OFFSET)
330 /* This decides where the kernel will search for a free chunk of vm
331 * space during mmap's.
332 */
333 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
335 #define HAVE_ARCH_PICK_MMAP_LAYOUT
337 /*
338 * Size of io_bitmap.
339 */
340 #define IO_BITMAP_BITS 65536
341 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
342 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
343 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
344 #define INVALID_IO_BITMAP_OFFSET 0x8000
345 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
347 struct i387_fsave_struct {
348 long cwd;
349 long swd;
350 long twd;
351 long fip;
352 long fcs;
353 long foo;
354 long fos;
355 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
356 long status; /* software status information */
357 };
359 struct i387_fxsave_struct {
360 unsigned short cwd;
361 unsigned short swd;
362 unsigned short twd;
363 unsigned short fop;
364 long fip;
365 long fcs;
366 long foo;
367 long fos;
368 long mxcsr;
369 long mxcsr_mask;
370 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
371 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
372 long padding[56];
373 } __attribute__ ((aligned (16)));
375 struct i387_soft_struct {
376 long cwd;
377 long swd;
378 long twd;
379 long fip;
380 long fcs;
381 long foo;
382 long fos;
383 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
384 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
385 struct info *info;
386 unsigned long entry_eip;
387 };
389 union i387_union {
390 struct i387_fsave_struct fsave;
391 struct i387_fxsave_struct fxsave;
392 struct i387_soft_struct soft;
393 };
395 typedef struct {
396 unsigned long seg;
397 } mm_segment_t;
399 struct thread_struct;
401 struct tss_struct {
402 unsigned short back_link,__blh;
403 unsigned long esp0;
404 unsigned short ss0,__ss0h;
405 unsigned long esp1;
406 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
407 unsigned long esp2;
408 unsigned short ss2,__ss2h;
409 unsigned long __cr3;
410 unsigned long eip;
411 unsigned long eflags;
412 unsigned long eax,ecx,edx,ebx;
413 unsigned long esp;
414 unsigned long ebp;
415 unsigned long esi;
416 unsigned long edi;
417 unsigned short es, __esh;
418 unsigned short cs, __csh;
419 unsigned short ss, __ssh;
420 unsigned short ds, __dsh;
421 unsigned short fs, __fsh;
422 unsigned short gs, __gsh;
423 unsigned short ldt, __ldth;
424 unsigned short trace, io_bitmap_base;
425 /*
426 * The extra 1 is there because the CPU will access an
427 * additional byte beyond the end of the IO permission
428 * bitmap. The extra byte must be all 1 bits, and must
429 * be within the limit.
430 */
431 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
432 /*
433 * Cache the current maximum and the last task that used the bitmap:
434 */
435 unsigned long io_bitmap_max;
436 struct thread_struct *io_bitmap_owner;
437 /*
438 * pads the TSS to be cacheline-aligned (size is 0x100)
439 */
440 unsigned long __cacheline_filler[35];
441 /*
442 * .. and then another 0x100 bytes for emergency kernel stack
443 */
444 unsigned long stack[64];
445 } __attribute__((packed));
447 #define ARCH_MIN_TASKALIGN 16
449 struct thread_struct {
450 /* cached TLS descriptors. */
451 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
452 unsigned long esp0;
453 unsigned long sysenter_cs;
454 unsigned long eip;
455 unsigned long esp;
456 unsigned long fs;
457 unsigned long gs;
458 /* Hardware debugging registers */
459 unsigned long debugreg[8]; /* %%db0-7 debug registers */
460 /* fault info */
461 unsigned long cr2, trap_no, error_code;
462 /* floating point info */
463 union i387_union i387;
464 /* virtual 86 mode info */
465 struct vm86_struct __user * vm86_info;
466 unsigned long screen_bitmap;
467 unsigned long v86flags, v86mask, saved_esp0;
468 unsigned int saved_fs, saved_gs;
469 /* IO permissions */
470 unsigned long *io_bitmap_ptr;
471 unsigned long iopl;
472 /* max allowed port in the bitmap, in bytes: */
473 unsigned long io_bitmap_max;
474 };
476 #define INIT_THREAD { \
477 .vm86_info = NULL, \
478 .sysenter_cs = __KERNEL_CS, \
479 .io_bitmap_ptr = NULL, \
480 }
482 /*
483 * Note that the .io_bitmap member must be extra-big. This is because
484 * the CPU will access an additional byte beyond the end of the IO
485 * permission bitmap. The extra byte must be all 1 bits, and must
486 * be within the limit.
487 */
488 #define INIT_TSS { \
489 .esp0 = sizeof(init_stack) + (long)&init_stack, \
490 .ss0 = __KERNEL_DS, \
491 .ss1 = __KERNEL_CS, \
492 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
493 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
494 }
496 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
497 {
498 tss->esp0 = thread->esp0;
499 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
500 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
501 tss->ss1 = thread->sysenter_cs;
502 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
503 }
504 }
506 #define start_thread(regs, new_eip, new_esp) do { \
507 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
508 set_fs(USER_DS); \
509 regs->xds = __USER_DS; \
510 regs->xes = __USER_DS; \
511 regs->xss = __USER_DS; \
512 regs->xcs = __USER_CS; \
513 regs->eip = new_eip; \
514 regs->esp = new_esp; \
515 } while (0)
517 /*
518 * These special macros can be used to get or set a debugging register
519 */
520 #define get_debugreg(var, register) \
521 __asm__("movl %%db" #register ", %0" \
522 :"=r" (var))
523 #define set_debugreg(value, register) \
524 __asm__("movl %0,%%db" #register \
525 : /* no output */ \
526 :"r" (value))
528 /*
529 * Set IOPL bits in EFLAGS from given mask
530 */
531 static inline void set_iopl_mask(unsigned mask)
532 {
533 unsigned int reg;
534 __asm__ __volatile__ ("pushfl;"
535 "popl %0;"
536 "andl %1, %0;"
537 "orl %2, %0;"
538 "pushl %0;"
539 "popfl"
540 : "=&r" (reg)
541 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
542 }
544 /* Forward declaration, a strange C thing */
545 struct task_struct;
546 struct mm_struct;
548 /* Free all resources held by a thread. */
549 extern void release_thread(struct task_struct *);
551 /* Prepare to copy thread state - unlazy all lazy status */
552 extern void prepare_to_copy(struct task_struct *tsk);
554 /*
555 * create a kernel thread without removing it from tasklists
556 */
557 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
559 extern unsigned long thread_saved_pc(struct task_struct *tsk);
560 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
562 unsigned long get_wchan(struct task_struct *p);
564 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
565 #define KSTK_TOP(info) \
566 ({ \
567 unsigned long *__ptr = (unsigned long *)(info); \
568 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
569 })
571 /*
572 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
573 * This is necessary to guarantee that the entire "struct pt_regs"
574 * is accessable even if the CPU haven't stored the SS/ESP registers
575 * on the stack (interrupt gate does not save these registers
576 * when switching to the same priv ring).
577 * Therefore beware: accessing the xss/esp fields of the
578 * "struct pt_regs" is possible, but they may contain the
579 * completely wrong values.
580 */
581 #define task_pt_regs(task) \
582 ({ \
583 struct pt_regs *__regs__; \
584 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
585 __regs__ - 1; \
586 })
588 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
589 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
592 struct microcode_header {
593 unsigned int hdrver;
594 unsigned int rev;
595 unsigned int date;
596 unsigned int sig;
597 unsigned int cksum;
598 unsigned int ldrver;
599 unsigned int pf;
600 unsigned int datasize;
601 unsigned int totalsize;
602 unsigned int reserved[3];
603 };
605 struct microcode {
606 struct microcode_header hdr;
607 unsigned int bits[0];
608 };
610 typedef struct microcode microcode_t;
611 typedef struct microcode_header microcode_header_t;
613 /* microcode format is extended from prescott processors */
614 struct extended_signature {
615 unsigned int sig;
616 unsigned int pf;
617 unsigned int cksum;
618 };
620 struct extended_sigtable {
621 unsigned int count;
622 unsigned int cksum;
623 unsigned int reserved[3];
624 struct extended_signature sigs[0];
625 };
627 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
628 static inline void rep_nop(void)
629 {
630 __asm__ __volatile__("rep;nop": : :"memory");
631 }
633 #define cpu_relax() rep_nop()
635 /* generic versions from gas */
636 #define GENERIC_NOP1 ".byte 0x90\n"
637 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
638 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
639 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
640 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
641 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
642 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
643 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
645 /* Opteron nops */
646 #define K8_NOP1 GENERIC_NOP1
647 #define K8_NOP2 ".byte 0x66,0x90\n"
648 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
649 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
650 #define K8_NOP5 K8_NOP3 K8_NOP2
651 #define K8_NOP6 K8_NOP3 K8_NOP3
652 #define K8_NOP7 K8_NOP4 K8_NOP3
653 #define K8_NOP8 K8_NOP4 K8_NOP4
655 /* K7 nops */
656 /* uses eax dependencies (arbitary choice) */
657 #define K7_NOP1 GENERIC_NOP1
658 #define K7_NOP2 ".byte 0x8b,0xc0\n"
659 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
660 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
661 #define K7_NOP5 K7_NOP4 ASM_NOP1
662 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
663 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
664 #define K7_NOP8 K7_NOP7 ASM_NOP1
666 #ifdef CONFIG_MK8
667 #define ASM_NOP1 K8_NOP1
668 #define ASM_NOP2 K8_NOP2
669 #define ASM_NOP3 K8_NOP3
670 #define ASM_NOP4 K8_NOP4
671 #define ASM_NOP5 K8_NOP5
672 #define ASM_NOP6 K8_NOP6
673 #define ASM_NOP7 K8_NOP7
674 #define ASM_NOP8 K8_NOP8
675 #elif defined(CONFIG_MK7)
676 #define ASM_NOP1 K7_NOP1
677 #define ASM_NOP2 K7_NOP2
678 #define ASM_NOP3 K7_NOP3
679 #define ASM_NOP4 K7_NOP4
680 #define ASM_NOP5 K7_NOP5
681 #define ASM_NOP6 K7_NOP6
682 #define ASM_NOP7 K7_NOP7
683 #define ASM_NOP8 K7_NOP8
684 #else
685 #define ASM_NOP1 GENERIC_NOP1
686 #define ASM_NOP2 GENERIC_NOP2
687 #define ASM_NOP3 GENERIC_NOP3
688 #define ASM_NOP4 GENERIC_NOP4
689 #define ASM_NOP5 GENERIC_NOP5
690 #define ASM_NOP6 GENERIC_NOP6
691 #define ASM_NOP7 GENERIC_NOP7
692 #define ASM_NOP8 GENERIC_NOP8
693 #endif
695 #define ASM_NOP_MAX 8
697 /* Prefetch instructions for Pentium III and AMD Athlon */
698 /* It's not worth to care about 3dnow! prefetches for the K6
699 because they are microcoded there and very slow.
700 However we don't do prefetches for pre XP Athlons currently
701 That should be fixed. */
702 #define ARCH_HAS_PREFETCH
703 static inline void prefetch(const void *x)
704 {
705 alternative_input(ASM_NOP4,
706 "prefetchnta (%1)",
707 X86_FEATURE_XMM,
708 "r" (x));
709 }
711 #define ARCH_HAS_PREFETCH
712 #define ARCH_HAS_PREFETCHW
713 #define ARCH_HAS_SPINLOCK_PREFETCH
715 /* 3dnow! prefetch to get an exclusive cache line. Useful for
716 spinlocks to avoid one state transition in the cache coherency protocol. */
717 static inline void prefetchw(const void *x)
718 {
719 alternative_input(ASM_NOP4,
720 "prefetchw (%1)",
721 X86_FEATURE_3DNOW,
722 "r" (x));
723 }
724 #define spin_lock_prefetch(x) prefetchw(x)
726 extern void select_idle_routine(const struct cpuinfo_x86 *c);
728 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
730 extern unsigned long boot_option_idle_override;
731 extern void enable_sep_cpu(void);
732 extern int sysenter_setup(void);
734 #endif /* __ASM_I386_PROCESSOR_H */