ia64/linux-2.6.18-xen.hg

view include/asm-i386/pgtable-3level.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 #ifndef _I386_PGTABLE_3LEVEL_H
2 #define _I386_PGTABLE_3LEVEL_H
4 #include <asm-generic/pgtable-nopud.h>
6 /*
7 * Intel Physical Address Extension (PAE) Mode - three-level page
8 * tables on PPro+ CPUs.
9 *
10 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
11 */
13 #define pte_ERROR(e) \
14 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15 #define pmd_ERROR(e) \
16 printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
17 #define pgd_ERROR(e) \
18 printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
20 #define pud_none(pud) 0
21 #define pud_bad(pud) 0
22 #define pud_present(pud) 1
24 /*
25 * Is the pte executable?
26 */
27 static inline int pte_x(pte_t pte)
28 {
29 return !(pte_val(pte) & _PAGE_NX);
30 }
32 /*
33 * All present user-pages with !NX bit are user-executable:
34 */
35 static inline int pte_exec(pte_t pte)
36 {
37 return pte_user(pte) && pte_x(pte);
38 }
39 /*
40 * All present pages with !NX bit are kernel-executable:
41 */
42 static inline int pte_exec_kernel(pte_t pte)
43 {
44 return pte_x(pte);
45 }
47 /* Rules for using set_pte: the pte being assigned *must* be
48 * either not present or in a state where the hardware will
49 * not attempt to update the pte. In places where this is
50 * not possible, use pte_get_and_clear to obtain the old pte
51 * value and then use set_pte to update it. -ben
52 */
53 static inline void set_pte(pte_t *ptep, pte_t pte)
54 {
55 ptep->pte_high = pte.pte_high;
56 smp_wmb();
57 ptep->pte_low = pte.pte_low;
58 }
59 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
61 #define __HAVE_ARCH_SET_PTE_ATOMIC
62 #define set_pte_atomic(pteptr,pteval) \
63 set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
64 #define set_pmd(pmdptr,pmdval) \
65 set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
66 #define set_pud(pudptr,pudval) \
67 (*(pudptr) = (pudval))
69 /*
70 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
71 * the TLB via cr3 if the top-level pgd is changed...
72 * We do not let the generic code free and clear pgd entries due to
73 * this erratum.
74 */
75 static inline void pud_clear (pud_t * pud) { }
77 #define pud_page(pud) \
78 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
80 #define pud_page_kernel(pud) \
81 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
84 /* Find an entry in the second-level page table.. */
85 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
86 pmd_index(address))
88 /*
89 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
90 * entry, so clear the bottom half first and enforce ordering with a compiler
91 * barrier.
92 */
93 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
94 {
95 ptep->pte_low = 0;
96 smp_wmb();
97 ptep->pte_high = 0;
98 }
100 static inline void pmd_clear(pmd_t *pmd)
101 {
102 u32 *tmp = (u32 *)pmd;
103 *tmp = 0;
104 smp_wmb();
105 *(tmp + 1) = 0;
106 }
108 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
109 {
110 pte_t res;
112 /* xchg acts as a barrier before the setting of the high bits */
113 res.pte_low = xchg(&ptep->pte_low, 0);
114 res.pte_high = ptep->pte_high;
115 ptep->pte_high = 0;
117 return res;
118 }
120 static inline int pte_same(pte_t a, pte_t b)
121 {
122 return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
123 }
125 #define pte_page(x) pfn_to_page(pte_pfn(x))
127 static inline int pte_none(pte_t pte)
128 {
129 return !pte.pte_low && !pte.pte_high;
130 }
132 static inline unsigned long pte_pfn(pte_t pte)
133 {
134 return (pte.pte_low >> PAGE_SHIFT) |
135 (pte.pte_high << (32 - PAGE_SHIFT));
136 }
138 extern unsigned long long __supported_pte_mask;
140 static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
141 {
142 pte_t pte;
144 pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
145 (pgprot_val(pgprot) >> 32);
146 pte.pte_high &= (__supported_pte_mask >> 32);
147 pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
148 __supported_pte_mask;
149 return pte;
150 }
152 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
153 {
154 return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
155 pgprot_val(pgprot)) & __supported_pte_mask);
156 }
158 /*
159 * Bits 0, 6 and 7 are taken in the low part of the pte,
160 * put the 32 bits of offset into the high part.
161 */
162 #define pte_to_pgoff(pte) ((pte).pte_high)
163 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
164 #define PTE_FILE_MAX_BITS 32
166 /* Encode and de-code a swap entry */
167 #define __swp_type(x) (((x).val) & 0x1f)
168 #define __swp_offset(x) ((x).val >> 5)
169 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
170 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
171 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
173 #define __pmd_free_tlb(tlb, x) do { } while (0)
175 #define vmalloc_sync_all() ((void)0)
177 #endif /* _I386_PGTABLE_3LEVEL_H */