ia64/linux-2.6.18-xen.hg

view include/asm-i386/msr.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 /*
5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
8 */
10 #define rdmsr(msr,val1,val2) \
11 __asm__ __volatile__("rdmsr" \
12 : "=a" (val1), "=d" (val2) \
13 : "c" (msr))
15 #define wrmsr(msr,val1,val2) \
16 __asm__ __volatile__("wrmsr" \
17 : /* no outputs */ \
18 : "c" (msr), "a" (val1), "d" (val2))
20 #define rdmsrl(msr,val) do { \
21 unsigned long l__,h__; \
22 rdmsr (msr, l__, h__); \
23 val = l__; \
24 val |= ((u64)h__<<32); \
25 } while(0)
27 static inline void wrmsrl (unsigned long msr, unsigned long long val)
28 {
29 unsigned long lo, hi;
30 lo = (unsigned long) val;
31 hi = val >> 32;
32 wrmsr (msr, lo, hi);
33 }
35 /* wrmsr with exception handling */
36 #define wrmsr_safe(msr,a,b) ({ int ret__; \
37 asm volatile("2: wrmsr ; xorl %0,%0\n" \
38 "1:\n\t" \
39 ".section .fixup,\"ax\"\n\t" \
40 "3: movl %4,%0 ; jmp 1b\n\t" \
41 ".previous\n\t" \
42 ".section __ex_table,\"a\"\n" \
43 " .align 4\n\t" \
44 " .long 2b,3b\n\t" \
45 ".previous" \
46 : "=a" (ret__) \
47 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
48 ret__; })
50 /* rdmsr with exception handling */
51 #define rdmsr_safe(msr,a,b) ({ int ret__; \
52 asm volatile("2: rdmsr ; xorl %0,%0\n" \
53 "1:\n\t" \
54 ".section .fixup,\"ax\"\n\t" \
55 "3: movl %4,%0 ; jmp 1b\n\t" \
56 ".previous\n\t" \
57 ".section __ex_table,\"a\"\n" \
58 " .align 4\n\t" \
59 " .long 2b,3b\n\t" \
60 ".previous" \
61 : "=r" (ret__), "=a" (*(a)), "=d" (*(b)) \
62 : "c" (msr), "i" (-EFAULT));\
63 ret__; })
65 #define rdtsc(low,high) \
66 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
68 #define rdtscl(low) \
69 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
71 #define rdtscll(val) \
72 __asm__ __volatile__("rdtsc" : "=A" (val))
74 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
76 #define rdpmc(counter,low,high) \
77 __asm__ __volatile__("rdpmc" \
78 : "=a" (low), "=d" (high) \
79 : "c" (counter))
81 /* symbolic names for some interesting MSRs */
82 /* Intel defined MSRs. */
83 #define MSR_IA32_P5_MC_ADDR 0
84 #define MSR_IA32_P5_MC_TYPE 1
85 #define MSR_IA32_PLATFORM_ID 0x17
86 #define MSR_IA32_EBL_CR_POWERON 0x2a
88 #define MSR_IA32_APICBASE 0x1b
89 #define MSR_IA32_APICBASE_BSP (1<<8)
90 #define MSR_IA32_APICBASE_ENABLE (1<<11)
91 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
93 #define MSR_IA32_UCODE_WRITE 0x79
94 #define MSR_IA32_UCODE_REV 0x8b
96 #define MSR_P6_PERFCTR0 0xc1
97 #define MSR_P6_PERFCTR1 0xc2
99 #define MSR_IA32_BBL_CR_CTL 0x119
101 #define MSR_IA32_SYSENTER_CS 0x174
102 #define MSR_IA32_SYSENTER_ESP 0x175
103 #define MSR_IA32_SYSENTER_EIP 0x176
105 #define MSR_IA32_MCG_CAP 0x179
106 #define MSR_IA32_MCG_STATUS 0x17a
107 #define MSR_IA32_MCG_CTL 0x17b
109 /* P4/Xeon+ specific */
110 #define MSR_IA32_MCG_EAX 0x180
111 #define MSR_IA32_MCG_EBX 0x181
112 #define MSR_IA32_MCG_ECX 0x182
113 #define MSR_IA32_MCG_EDX 0x183
114 #define MSR_IA32_MCG_ESI 0x184
115 #define MSR_IA32_MCG_EDI 0x185
116 #define MSR_IA32_MCG_EBP 0x186
117 #define MSR_IA32_MCG_ESP 0x187
118 #define MSR_IA32_MCG_EFLAGS 0x188
119 #define MSR_IA32_MCG_EIP 0x189
120 #define MSR_IA32_MCG_RESERVED 0x18A
122 #define MSR_P6_EVNTSEL0 0x186
123 #define MSR_P6_EVNTSEL1 0x187
125 #define MSR_IA32_PERF_STATUS 0x198
126 #define MSR_IA32_PERF_CTL 0x199
128 #define MSR_IA32_THERM_CONTROL 0x19a
129 #define MSR_IA32_THERM_INTERRUPT 0x19b
130 #define MSR_IA32_THERM_STATUS 0x19c
131 #define MSR_IA32_MISC_ENABLE 0x1a0
133 #define MSR_IA32_DEBUGCTLMSR 0x1d9
134 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
135 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
136 #define MSR_IA32_LASTINTFROMIP 0x1dd
137 #define MSR_IA32_LASTINTTOIP 0x1de
139 #define MSR_IA32_MC0_CTL 0x400
140 #define MSR_IA32_MC0_STATUS 0x401
141 #define MSR_IA32_MC0_ADDR 0x402
142 #define MSR_IA32_MC0_MISC 0x403
144 /* Pentium IV performance counter MSRs */
145 #define MSR_P4_BPU_PERFCTR0 0x300
146 #define MSR_P4_BPU_PERFCTR1 0x301
147 #define MSR_P4_BPU_PERFCTR2 0x302
148 #define MSR_P4_BPU_PERFCTR3 0x303
149 #define MSR_P4_MS_PERFCTR0 0x304
150 #define MSR_P4_MS_PERFCTR1 0x305
151 #define MSR_P4_MS_PERFCTR2 0x306
152 #define MSR_P4_MS_PERFCTR3 0x307
153 #define MSR_P4_FLAME_PERFCTR0 0x308
154 #define MSR_P4_FLAME_PERFCTR1 0x309
155 #define MSR_P4_FLAME_PERFCTR2 0x30a
156 #define MSR_P4_FLAME_PERFCTR3 0x30b
157 #define MSR_P4_IQ_PERFCTR0 0x30c
158 #define MSR_P4_IQ_PERFCTR1 0x30d
159 #define MSR_P4_IQ_PERFCTR2 0x30e
160 #define MSR_P4_IQ_PERFCTR3 0x30f
161 #define MSR_P4_IQ_PERFCTR4 0x310
162 #define MSR_P4_IQ_PERFCTR5 0x311
163 #define MSR_P4_BPU_CCCR0 0x360
164 #define MSR_P4_BPU_CCCR1 0x361
165 #define MSR_P4_BPU_CCCR2 0x362
166 #define MSR_P4_BPU_CCCR3 0x363
167 #define MSR_P4_MS_CCCR0 0x364
168 #define MSR_P4_MS_CCCR1 0x365
169 #define MSR_P4_MS_CCCR2 0x366
170 #define MSR_P4_MS_CCCR3 0x367
171 #define MSR_P4_FLAME_CCCR0 0x368
172 #define MSR_P4_FLAME_CCCR1 0x369
173 #define MSR_P4_FLAME_CCCR2 0x36a
174 #define MSR_P4_FLAME_CCCR3 0x36b
175 #define MSR_P4_IQ_CCCR0 0x36c
176 #define MSR_P4_IQ_CCCR1 0x36d
177 #define MSR_P4_IQ_CCCR2 0x36e
178 #define MSR_P4_IQ_CCCR3 0x36f
179 #define MSR_P4_IQ_CCCR4 0x370
180 #define MSR_P4_IQ_CCCR5 0x371
181 #define MSR_P4_ALF_ESCR0 0x3ca
182 #define MSR_P4_ALF_ESCR1 0x3cb
183 #define MSR_P4_BPU_ESCR0 0x3b2
184 #define MSR_P4_BPU_ESCR1 0x3b3
185 #define MSR_P4_BSU_ESCR0 0x3a0
186 #define MSR_P4_BSU_ESCR1 0x3a1
187 #define MSR_P4_CRU_ESCR0 0x3b8
188 #define MSR_P4_CRU_ESCR1 0x3b9
189 #define MSR_P4_CRU_ESCR2 0x3cc
190 #define MSR_P4_CRU_ESCR3 0x3cd
191 #define MSR_P4_CRU_ESCR4 0x3e0
192 #define MSR_P4_CRU_ESCR5 0x3e1
193 #define MSR_P4_DAC_ESCR0 0x3a8
194 #define MSR_P4_DAC_ESCR1 0x3a9
195 #define MSR_P4_FIRM_ESCR0 0x3a4
196 #define MSR_P4_FIRM_ESCR1 0x3a5
197 #define MSR_P4_FLAME_ESCR0 0x3a6
198 #define MSR_P4_FLAME_ESCR1 0x3a7
199 #define MSR_P4_FSB_ESCR0 0x3a2
200 #define MSR_P4_FSB_ESCR1 0x3a3
201 #define MSR_P4_IQ_ESCR0 0x3ba
202 #define MSR_P4_IQ_ESCR1 0x3bb
203 #define MSR_P4_IS_ESCR0 0x3b4
204 #define MSR_P4_IS_ESCR1 0x3b5
205 #define MSR_P4_ITLB_ESCR0 0x3b6
206 #define MSR_P4_ITLB_ESCR1 0x3b7
207 #define MSR_P4_IX_ESCR0 0x3c8
208 #define MSR_P4_IX_ESCR1 0x3c9
209 #define MSR_P4_MOB_ESCR0 0x3aa
210 #define MSR_P4_MOB_ESCR1 0x3ab
211 #define MSR_P4_MS_ESCR0 0x3c0
212 #define MSR_P4_MS_ESCR1 0x3c1
213 #define MSR_P4_PMH_ESCR0 0x3ac
214 #define MSR_P4_PMH_ESCR1 0x3ad
215 #define MSR_P4_RAT_ESCR0 0x3bc
216 #define MSR_P4_RAT_ESCR1 0x3bd
217 #define MSR_P4_SAAT_ESCR0 0x3ae
218 #define MSR_P4_SAAT_ESCR1 0x3af
219 #define MSR_P4_SSU_ESCR0 0x3be
220 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
221 #define MSR_P4_TBPU_ESCR0 0x3c2
222 #define MSR_P4_TBPU_ESCR1 0x3c3
223 #define MSR_P4_TC_ESCR0 0x3c4
224 #define MSR_P4_TC_ESCR1 0x3c5
225 #define MSR_P4_U2L_ESCR0 0x3b0
226 #define MSR_P4_U2L_ESCR1 0x3b1
228 /* AMD Defined MSRs */
229 #define MSR_K6_EFER 0xC0000080
230 #define MSR_K6_STAR 0xC0000081
231 #define MSR_K6_WHCR 0xC0000082
232 #define MSR_K6_UWCCR 0xC0000085
233 #define MSR_K6_EPMR 0xC0000086
234 #define MSR_K6_PSOR 0xC0000087
235 #define MSR_K6_PFIR 0xC0000088
237 #define MSR_K7_EVNTSEL0 0xC0010000
238 #define MSR_K7_EVNTSEL1 0xC0010001
239 #define MSR_K7_EVNTSEL2 0xC0010002
240 #define MSR_K7_EVNTSEL3 0xC0010003
241 #define MSR_K7_PERFCTR0 0xC0010004
242 #define MSR_K7_PERFCTR1 0xC0010005
243 #define MSR_K7_PERFCTR2 0xC0010006
244 #define MSR_K7_PERFCTR3 0xC0010007
245 #define MSR_K7_HWCR 0xC0010015
246 #define MSR_K7_CLK_CTL 0xC001001b
247 #define MSR_K7_FID_VID_CTL 0xC0010041
248 #define MSR_K7_FID_VID_STATUS 0xC0010042
250 /* extended feature register */
251 #define MSR_EFER 0xc0000080
253 /* EFER bits: */
255 /* Execute Disable enable */
256 #define _EFER_NX 11
257 #define EFER_NX (1<<_EFER_NX)
259 /* Centaur-Hauls/IDT defined MSRs. */
260 #define MSR_IDT_FCR1 0x107
261 #define MSR_IDT_FCR2 0x108
262 #define MSR_IDT_FCR3 0x109
263 #define MSR_IDT_FCR4 0x10a
265 #define MSR_IDT_MCR0 0x110
266 #define MSR_IDT_MCR1 0x111
267 #define MSR_IDT_MCR2 0x112
268 #define MSR_IDT_MCR3 0x113
269 #define MSR_IDT_MCR4 0x114
270 #define MSR_IDT_MCR5 0x115
271 #define MSR_IDT_MCR6 0x116
272 #define MSR_IDT_MCR7 0x117
273 #define MSR_IDT_MCR_CTRL 0x120
275 /* VIA Cyrix defined MSRs*/
276 #define MSR_VIA_FCR 0x1107
277 #define MSR_VIA_LONGHAUL 0x110a
278 #define MSR_VIA_RNG 0x110b
279 #define MSR_VIA_BCR2 0x1147
281 /* Transmeta defined MSRs */
282 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
283 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
284 #define MSR_TMTA_LRTI_READOUT 0x80868018
285 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
287 #endif /* __ASM_MSR_H */