ia64/linux-2.6.18-xen.hg

view include/asm-i386/io_apic.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children 9f9b4214bec8
line source
1 #ifndef __ASM_IO_APIC_H
2 #define __ASM_IO_APIC_H
4 #include <asm/types.h>
5 #include <asm/mpspec.h>
7 /*
8 * Intel IO-APIC support for SMP and UP systems.
9 *
10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
11 */
13 #ifdef CONFIG_X86_IO_APIC
15 #ifdef CONFIG_PCI_MSI
16 static inline int use_pci_vector(void) {return 1;}
17 static inline void disable_edge_ioapic_vector(unsigned int vector) { }
18 static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
19 static inline void end_edge_ioapic_vector (unsigned int vector) { }
20 #define startup_level_ioapic startup_level_ioapic_vector
21 #define shutdown_level_ioapic mask_IO_APIC_vector
22 #define enable_level_ioapic unmask_IO_APIC_vector
23 #define disable_level_ioapic mask_IO_APIC_vector
24 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
25 #define end_level_ioapic end_level_ioapic_vector
26 #define set_ioapic_affinity set_ioapic_affinity_vector
28 #define startup_edge_ioapic startup_edge_ioapic_vector
29 #define shutdown_edge_ioapic disable_edge_ioapic_vector
30 #define enable_edge_ioapic unmask_IO_APIC_vector
31 #define disable_edge_ioapic disable_edge_ioapic_vector
32 #define ack_edge_ioapic ack_edge_ioapic_vector
33 #define end_edge_ioapic end_edge_ioapic_vector
34 #else
35 static inline int use_pci_vector(void) {return 0;}
36 static inline void disable_edge_ioapic_irq(unsigned int irq) { }
37 static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
38 static inline void end_edge_ioapic_irq (unsigned int irq) { }
39 #define startup_level_ioapic startup_level_ioapic_irq
40 #define shutdown_level_ioapic mask_IO_APIC_irq
41 #define enable_level_ioapic unmask_IO_APIC_irq
42 #define disable_level_ioapic mask_IO_APIC_irq
43 #define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
44 #define end_level_ioapic end_level_ioapic_irq
45 #define set_ioapic_affinity set_ioapic_affinity_irq
47 #define startup_edge_ioapic startup_edge_ioapic_irq
48 #define shutdown_edge_ioapic disable_edge_ioapic_irq
49 #define enable_edge_ioapic unmask_IO_APIC_irq
50 #define disable_edge_ioapic disable_edge_ioapic_irq
51 #define ack_edge_ioapic ack_edge_ioapic_irq
52 #define end_edge_ioapic end_edge_ioapic_irq
53 #endif
55 #define IO_APIC_BASE(idx) \
56 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
57 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
59 /*
60 * The structure of the IO-APIC:
61 */
62 union IO_APIC_reg_00 {
63 u32 raw;
64 struct {
65 u32 __reserved_2 : 14,
66 LTS : 1,
67 delivery_type : 1,
68 __reserved_1 : 8,
69 ID : 8;
70 } __attribute__ ((packed)) bits;
71 };
73 union IO_APIC_reg_01 {
74 u32 raw;
75 struct {
76 u32 version : 8,
77 __reserved_2 : 7,
78 PRQ : 1,
79 entries : 8,
80 __reserved_1 : 8;
81 } __attribute__ ((packed)) bits;
82 };
84 union IO_APIC_reg_02 {
85 u32 raw;
86 struct {
87 u32 __reserved_2 : 24,
88 arbitration : 4,
89 __reserved_1 : 4;
90 } __attribute__ ((packed)) bits;
91 };
93 union IO_APIC_reg_03 {
94 u32 raw;
95 struct {
96 u32 boot_DT : 1,
97 __reserved_1 : 31;
98 } __attribute__ ((packed)) bits;
99 };
101 /*
102 * # of IO-APICs and # of IRQ routing registers
103 */
104 extern int nr_ioapics;
105 extern int nr_ioapic_registers[MAX_IO_APICS];
107 enum ioapic_irq_destination_types {
108 dest_Fixed = 0,
109 dest_LowestPrio = 1,
110 dest_SMI = 2,
111 dest__reserved_1 = 3,
112 dest_NMI = 4,
113 dest_INIT = 5,
114 dest__reserved_2 = 6,
115 dest_ExtINT = 7
116 };
118 struct IO_APIC_route_entry {
119 __u32 vector : 8,
120 delivery_mode : 3, /* 000: FIXED
121 * 001: lowest prio
122 * 111: ExtINT
123 */
124 dest_mode : 1, /* 0: physical, 1: logical */
125 delivery_status : 1,
126 polarity : 1,
127 irr : 1,
128 trigger : 1, /* 0: edge, 1: level */
129 mask : 1, /* 0: enabled, 1: disabled */
130 __reserved_2 : 15;
132 union { struct { __u32
133 __reserved_1 : 24,
134 physical_dest : 4,
135 __reserved_2 : 4;
136 } physical;
138 struct { __u32
139 __reserved_1 : 24,
140 logical_dest : 8;
141 } logical;
142 } dest;
144 } __attribute__ ((packed));
146 /*
147 * MP-BIOS irq configuration table structures:
148 */
150 /* I/O APIC entries */
151 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
153 /* # of MP IRQ source entries */
154 extern int mp_irq_entries;
156 /* MP IRQ source entries */
157 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
159 /* non-0 if default (table-less) MP configuration */
160 extern int mpc_default_type;
162 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
163 {
164 *IO_APIC_BASE(apic) = reg;
165 return *(IO_APIC_BASE(apic)+4);
166 }
168 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
169 {
170 *IO_APIC_BASE(apic) = reg;
171 *(IO_APIC_BASE(apic)+4) = value;
172 }
174 /*
175 * Re-write a value: to be used for read-modify-write
176 * cycles where the read already set up the index register.
177 *
178 * Older SiS APIC requires we rewrite the index regiser
179 */
180 extern int sis_apic_bug;
181 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
182 {
183 if (sis_apic_bug)
184 *IO_APIC_BASE(apic) = reg;
185 *(IO_APIC_BASE(apic)+4) = value;
186 }
188 /* 1 if "noapic" boot option passed */
189 extern int skip_ioapic_setup;
191 /*
192 * If we use the IO-APIC for IRQ routing, disable automatic
193 * assignment of PCI IRQ's.
194 */
195 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
197 #ifdef CONFIG_ACPI
198 extern int io_apic_get_unique_id (int ioapic, int apic_id);
199 extern int io_apic_get_version (int ioapic);
200 extern int io_apic_get_redir_entries (int ioapic);
201 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
202 extern int timer_uses_ioapic_pin_0;
203 #endif /* CONFIG_ACPI */
205 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
207 #else /* !CONFIG_X86_IO_APIC */
208 #define io_apic_assign_pci_irqs 0
209 #endif
211 extern int assign_irq_vector(int irq);
213 #endif