ia64/linux-2.6.18-xen.hg

view include/asm-arm/io.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm-arm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21 #ifndef __ASM_ARM_IO_H
22 #define __ASM_ARM_IO_H
24 #ifdef __KERNEL__
26 #include <linux/types.h>
27 #include <asm/byteorder.h>
28 #include <asm/memory.h>
30 /*
31 * ISA I/O bus memory addresses are 1:1 with the physical address.
32 */
33 #define isa_virt_to_bus virt_to_phys
34 #define isa_page_to_bus page_to_phys
35 #define isa_bus_to_virt phys_to_virt
37 /*
38 * Generic IO read/write. These perform native-endian accesses. Note
39 * that some architectures will want to re-define __raw_{read,write}w.
40 */
41 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
42 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
43 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
45 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
46 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
47 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
49 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
50 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
51 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
53 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
54 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
55 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
57 /*
58 * Architecture ioremap implementation.
59 *
60 * __ioremap takes CPU physical address.
61 *
62 * __ioremap_pfn takes a Page Frame Number and an offset into that page
63 */
64 extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
65 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
66 extern void __iounmap(void __iomem *addr);
68 /*
69 * Bad read/write accesses...
70 */
71 extern void __readwrite_bug(const char *fn);
73 /*
74 * Now, pick up the machine-defined IO definitions
75 */
76 #include <asm/arch/io.h>
78 #ifdef __io_pci
79 #warning machine class uses buggy __io_pci
80 #endif
81 #if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
82 defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
83 #warning machine class uses old __arch_putw or __arch_getw
84 #endif
86 /*
87 * IO port access primitives
88 * -------------------------
89 *
90 * The ARM doesn't have special IO access instructions; all IO is memory
91 * mapped. Note that these are defined to perform little endian accesses
92 * only. Their primary purpose is to access PCI and ISA peripherals.
93 *
94 * Note that for a big endian machine, this implies that the following
95 * big endian mode connectivity is in place, as described by numerous
96 * ARM documents:
97 *
98 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
99 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
100 *
101 * The machine specific io.h include defines __io to translate an "IO"
102 * address to a memory address.
103 *
104 * Note that we prevent GCC re-ordering or caching values in expressions
105 * by introducing sequence points into the in*() definitions. Note that
106 * __raw_* do not guarantee this behaviour.
107 *
108 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
109 */
110 #ifdef __io
111 #define outb(v,p) __raw_writeb(v,__io(p))
112 #define outw(v,p) __raw_writew((__force __u16) \
113 cpu_to_le16(v),__io(p))
114 #define outl(v,p) __raw_writel((__force __u32) \
115 cpu_to_le32(v),__io(p))
117 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; })
118 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
119 __raw_readw(__io(p))); __v; })
120 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
121 __raw_readl(__io(p))); __v; })
123 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
124 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
125 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
127 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
128 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
129 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
130 #endif
132 #define outb_p(val,port) outb((val),(port))
133 #define outw_p(val,port) outw((val),(port))
134 #define outl_p(val,port) outl((val),(port))
135 #define inb_p(port) inb((port))
136 #define inw_p(port) inw((port))
137 #define inl_p(port) inl((port))
139 #define outsb_p(port,from,len) outsb(port,from,len)
140 #define outsw_p(port,from,len) outsw(port,from,len)
141 #define outsl_p(port,from,len) outsl(port,from,len)
142 #define insb_p(port,to,len) insb(port,to,len)
143 #define insw_p(port,to,len) insw(port,to,len)
144 #define insl_p(port,to,len) insl(port,to,len)
146 /*
147 * String version of IO memory access ops:
148 */
149 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
150 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
151 extern void _memset_io(volatile void __iomem *, int, size_t);
153 #define mmiowb()
155 /*
156 * Memory access primitives
157 * ------------------------
158 *
159 * These perform PCI memory accesses via an ioremap region. They don't
160 * take an address as such, but a cookie.
161 *
162 * Again, this are defined to perform little endian accesses. See the
163 * IO port primitives for more information.
164 */
165 #ifdef __mem_pci
166 #define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; })
167 #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
168 __raw_readw(__mem_pci(c))); __v; })
169 #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
170 __raw_readl(__mem_pci(c))); __v; })
171 #define readb_relaxed(addr) readb(addr)
172 #define readw_relaxed(addr) readw(addr)
173 #define readl_relaxed(addr) readl(addr)
175 #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
176 #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
177 #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
179 #define writeb(v,c) __raw_writeb(v,__mem_pci(c))
180 #define writew(v,c) __raw_writew((__force __u16) \
181 cpu_to_le16(v),__mem_pci(c))
182 #define writel(v,c) __raw_writel((__force __u32) \
183 cpu_to_le32(v),__mem_pci(c))
185 #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
186 #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
187 #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
189 #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
190 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
191 #define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
193 #define eth_io_copy_and_sum(s,c,l,b) \
194 eth_copy_and_sum((s),__mem_pci(c),(l),(b))
196 static inline int
197 check_signature(void __iomem *io_addr, const unsigned char *signature,
198 int length)
199 {
200 int retval = 0;
201 do {
202 if (readb(io_addr) != *signature)
203 goto out;
204 io_addr++;
205 signature++;
206 length--;
207 } while (length);
208 retval = 1;
209 out:
210 return retval;
211 }
213 #elif !defined(readb)
215 #define readb(c) (__readwrite_bug("readb"),0)
216 #define readw(c) (__readwrite_bug("readw"),0)
217 #define readl(c) (__readwrite_bug("readl"),0)
218 #define writeb(v,c) __readwrite_bug("writeb")
219 #define writew(v,c) __readwrite_bug("writew")
220 #define writel(v,c) __readwrite_bug("writel")
222 #define eth_io_copy_and_sum(s,c,l,b) __readwrite_bug("eth_io_copy_and_sum")
224 #define check_signature(io,sig,len) (0)
226 #endif /* __mem_pci */
228 /*
229 * ioremap and friends.
230 *
231 * ioremap takes a PCI memory address, as specified in
232 * Documentation/IO-mapping.txt.
233 *
234 */
235 #ifndef __arch_ioremap
236 #define ioremap(cookie,size) __ioremap(cookie,size,0)
237 #define ioremap_nocache(cookie,size) __ioremap(cookie,size,0)
238 #define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE)
239 #define iounmap(cookie) __iounmap(cookie)
240 #else
241 #define ioremap(cookie,size) __arch_ioremap((cookie),(size),0)
242 #define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0)
243 #define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
244 #define iounmap(cookie) __arch_iounmap(cookie)
245 #endif
247 /*
248 * io{read,write}{8,16,32} macros
249 */
250 #ifndef ioread8
251 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
252 #define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
253 #define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
255 #define iowrite8(v,p) __raw_writeb(v, p)
256 #define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
257 #define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
259 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
260 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
261 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
263 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
264 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
265 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
267 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
268 extern void ioport_unmap(void __iomem *addr);
269 #endif
271 struct pci_dev;
273 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
274 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
276 /*
277 * can the hardware map this into one segment or not, given no other
278 * constraints.
279 */
280 #define BIOVEC_MERGEABLE(vec1, vec2) \
281 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
283 /*
284 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
285 * access
286 */
287 #define xlate_dev_mem_ptr(p) __va(p)
289 /*
290 * Convert a virtual cached pointer to an uncached pointer
291 */
292 #define xlate_dev_kmem_ptr(p) p
294 /*
295 * Register ISA memory and port locations for glibc iopl/inb/outb
296 * emulation.
297 */
298 extern void register_isa_ports(unsigned int mmio, unsigned int io,
299 unsigned int io_shift);
301 #endif /* __KERNEL__ */
302 #endif /* __ASM_ARM_IO_H */