ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-omap/mux.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * NOTE: Please use the following naming style for new pin entries.
26 * For example, W8_1610_MMC2_DAT0, where:
27 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */
40 #ifndef __ASM_ARCH_MUX_H
41 #define __ASM_ARCH_MUX_H
43 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
44 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
46 #ifdef CONFIG_OMAP_MUX_DEBUG
47 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
48 .mux_reg = FUNC_MUX_CTRL_##reg, \
49 .mask_offset = mode_offset, \
50 .mask = mode,
52 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
53 .pull_reg = PULL_DWN_CTRL_##reg, \
54 .pull_bit = bit, \
55 .pull_val = status,
57 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status,
61 #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
62 .mux_reg = OMAP730_IO_CONF_##reg, \
63 .mask_offset = mode_offset, \
64 .mask = mode,
66 #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
67 .pull_reg = OMAP730_IO_CONF_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
71 #else
73 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
74 .mask_offset = mode_offset, \
75 .mask = mode,
77 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
78 .pull_bit = bit, \
79 .pull_val = status,
81 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
82 .pu_pd_val = status,
84 #define MUX_REG_730(reg, mode_offset, mode) \
85 .mux_reg = OMAP730_IO_CONF_##reg, \
86 .mask_offset = mode_offset, \
87 .mask = mode,
89 #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
90 .pull_bit = bit, \
91 .pull_val = status,
93 #endif /* CONFIG_OMAP_MUX_DEBUG */
95 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
96 pull_reg, pull_bit, pull_status, \
97 pu_pd_reg, pu_pd_status, debug_status) \
98 { \
99 .name = desc, \
100 .debug = debug_status, \
101 MUX_REG(mux_reg, mode_offset, mode) \
102 PULL_REG(pull_reg, pull_bit, pull_status) \
103 PU_PD_REG(pu_pd_reg, pu_pd_status) \
104 },
107 /*
108 * OMAP730 has a slightly different config for the pin mux.
109 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
110 * not the FUNC_MUX_CTRL_x regs from hardware.h
111 * - for pull-up/down, only has one enable bit which is is in the same register
112 * as mux config
113 */
114 #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
115 pull_bit, pull_status, debug_status)\
116 { \
117 .name = desc, \
118 .debug = debug_status, \
119 MUX_REG_730(mux_reg, mode_offset, mode) \
120 PULL_REG_730(mux_reg, pull_bit, pull_status) \
121 PU_PD_REG(NA, 0) \
122 },
124 #define MUX_CFG_24XX(desc, reg_offset, mode, \
125 pull_en, pull_mode, dbg) \
126 { \
127 .name = desc, \
128 .debug = dbg, \
129 .mux_reg = reg_offset, \
130 .mask = mode, \
131 .pull_val = pull_en, \
132 .pu_pd_val = pull_mode, \
133 },
136 #define PULL_DISABLED 0
137 #define PULL_ENABLED 1
139 #define PULL_DOWN 0
140 #define PULL_UP 1
142 struct pin_config {
143 char *name;
144 unsigned char busy;
145 unsigned char debug;
147 const char *mux_reg_name;
148 const unsigned int mux_reg;
149 const unsigned char mask_offset;
150 const unsigned char mask;
152 const char *pull_name;
153 const unsigned int pull_reg;
154 const unsigned char pull_val;
155 const unsigned char pull_bit;
157 const char *pu_pd_name;
158 const unsigned int pu_pd_reg;
159 const unsigned char pu_pd_val;
160 };
162 enum omap730_index {
163 /* OMAP 730 keyboard */
164 E2_730_KBR0,
165 J7_730_KBR1,
166 E1_730_KBR2,
167 F3_730_KBR3,
168 D2_730_KBR4,
169 C2_730_KBC0,
170 D3_730_KBC1,
171 E4_730_KBC2,
172 F4_730_KBC3,
173 E3_730_KBC4,
175 /* USB */
176 AA17_730_USB_DM,
177 W16_730_USB_PU_EN,
178 W17_730_USB_VBUSI,
179 };
181 enum omap1xxx_index {
182 /* UART1 (BT_UART_GATING)*/
183 UART1_TX = 0,
184 UART1_RTS,
186 /* UART2 (COM_UART_GATING)*/
187 UART2_TX,
188 UART2_RX,
189 UART2_CTS,
190 UART2_RTS,
192 /* UART3 (GIGA_UART_GATING) */
193 UART3_TX,
194 UART3_RX,
195 UART3_CTS,
196 UART3_RTS,
197 UART3_CLKREQ,
198 UART3_BCLK, /* 12MHz clock out */
199 Y15_1610_UART3_RTS,
201 /* PWT & PWL */
202 PWT,
203 PWL,
205 /* USB master generic */
206 R18_USB_VBUS,
207 R18_1510_USB_GPIO0,
208 W4_USB_PUEN,
209 W4_USB_CLKO,
210 W4_USB_HIGHZ,
211 W4_GPIO58,
213 /* USB1 master */
214 USB1_SUSP,
215 USB1_SEO,
216 W13_1610_USB1_SE0,
217 USB1_TXEN,
218 USB1_TXD,
219 USB1_VP,
220 USB1_VM,
221 USB1_RCV,
222 USB1_SPEED,
223 R13_1610_USB1_SPEED,
224 R13_1710_USB1_SE0,
226 /* USB2 master */
227 USB2_SUSP,
228 USB2_VP,
229 USB2_TXEN,
230 USB2_VM,
231 USB2_RCV,
232 USB2_SEO,
233 USB2_TXD,
235 /* OMAP-1510 GPIO */
236 R18_1510_GPIO0,
237 R19_1510_GPIO1,
238 M14_1510_GPIO2,
240 /* OMAP1610 GPIO */
241 P18_1610_GPIO3,
242 Y15_1610_GPIO17,
244 /* OMAP-1710 GPIO */
245 R18_1710_GPIO0,
246 V2_1710_GPIO10,
247 N21_1710_GPIO14,
248 W15_1710_GPIO40,
250 /* MPUIO */
251 MPUIO2,
252 N15_1610_MPUIO2,
253 MPUIO4,
254 MPUIO5,
255 T20_1610_MPUIO5,
256 W11_1610_MPUIO6,
257 V10_1610_MPUIO7,
258 W11_1610_MPUIO9,
259 V10_1610_MPUIO10,
260 W10_1610_MPUIO11,
261 E20_1610_MPUIO13,
262 U20_1610_MPUIO14,
263 E19_1610_MPUIO15,
265 /* MCBSP2 */
266 MCBSP2_CLKR,
267 MCBSP2_CLKX,
268 MCBSP2_DR,
269 MCBSP2_DX,
270 MCBSP2_FSR,
271 MCBSP2_FSX,
273 /* MCBSP3 */
274 MCBSP3_CLKX,
276 /* Misc ballouts */
277 BALLOUT_V8_ARMIO3,
278 N20_HDQ,
280 /* OMAP-1610 MMC2 */
281 W8_1610_MMC2_DAT0,
282 V8_1610_MMC2_DAT1,
283 W15_1610_MMC2_DAT2,
284 R10_1610_MMC2_DAT3,
285 Y10_1610_MMC2_CLK,
286 Y8_1610_MMC2_CMD,
287 V9_1610_MMC2_CMDDIR,
288 V5_1610_MMC2_DATDIR0,
289 W19_1610_MMC2_DATDIR1,
290 R18_1610_MMC2_CLKIN,
292 /* OMAP-1610 External Trace Interface */
293 M19_1610_ETM_PSTAT0,
294 L15_1610_ETM_PSTAT1,
295 L18_1610_ETM_PSTAT2,
296 L19_1610_ETM_D0,
297 J19_1610_ETM_D6,
298 J18_1610_ETM_D7,
300 /* OMAP16XX GPIO */
301 P20_1610_GPIO4,
302 V9_1610_GPIO7,
303 W8_1610_GPIO9,
304 N20_1610_GPIO11,
305 N19_1610_GPIO13,
306 P10_1610_GPIO22,
307 V5_1610_GPIO24,
308 AA20_1610_GPIO_41,
309 W19_1610_GPIO48,
310 M7_1610_GPIO62,
311 V14_16XX_GPIO37,
312 R9_16XX_GPIO18,
313 L14_16XX_GPIO49,
315 /* OMAP-1610 uWire */
316 V19_1610_UWIRE_SCLK,
317 U18_1610_UWIRE_SDI,
318 W21_1610_UWIRE_SDO,
319 N14_1610_UWIRE_CS0,
320 P15_1610_UWIRE_CS3,
321 N15_1610_UWIRE_CS1,
323 /* OMAP-1610 Flash */
324 L3_1610_FLASH_CS2B_OE,
325 M8_1610_FLASH_CS2B_WE,
327 /* First MMC */
328 MMC_CMD,
329 MMC_DAT1,
330 MMC_DAT2,
331 MMC_DAT0,
332 MMC_CLK,
333 MMC_DAT3,
335 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
336 M15_1710_MMC_CLKI,
337 P19_1710_MMC_CMDDIR,
338 P20_1710_MMC_DATDIR0,
340 /* OMAP-1610 USB0 alternate pin configuration */
341 W9_USB0_TXEN,
342 AA9_USB0_VP,
343 Y5_USB0_RCV,
344 R9_USB0_VM,
345 V6_USB0_TXD,
346 W5_USB0_SE0,
347 V9_USB0_SPEED,
348 V9_USB0_SUSP,
350 /* USB2 */
351 W9_USB2_TXEN,
352 AA9_USB2_VP,
353 Y5_USB2_RCV,
354 R9_USB2_VM,
355 V6_USB2_TXD,
356 W5_USB2_SE0,
358 /* 16XX UART */
359 R13_1610_UART1_TX,
360 V14_16XX_UART1_RX,
361 R14_1610_UART1_CTS,
362 AA15_1610_UART1_RTS,
363 R9_16XX_UART2_RX,
364 L14_16XX_UART3_RX,
366 /* I2C OMAP-1610 */
367 I2C_SCL,
368 I2C_SDA,
370 /* Keypad */
371 F18_1610_KBC0,
372 D20_1610_KBC1,
373 D19_1610_KBC2,
374 E18_1610_KBC3,
375 C21_1610_KBC4,
376 G18_1610_KBR0,
377 F19_1610_KBR1,
378 H14_1610_KBR2,
379 E20_1610_KBR3,
380 E19_1610_KBR4,
381 N19_1610_KBR5,
383 /* Power management */
384 T20_1610_LOW_PWR,
386 /* MCLK Settings */
387 V5_1710_MCLK_ON,
388 V5_1710_MCLK_OFF,
389 R10_1610_MCLK_ON,
390 R10_1610_MCLK_OFF,
392 /* CompactFlash controller */
393 P11_1610_CF_CD2,
394 R11_1610_CF_IOIS16,
395 V10_1610_CF_IREQ,
396 W10_1610_CF_RESET,
397 W11_1610_CF_CD1,
398 };
400 enum omap24xx_index {
401 /* 24xx I2C */
402 M19_24XX_I2C1_SCL,
403 L15_24XX_I2C1_SDA,
404 J15_24XX_I2C2_SCL,
405 H19_24XX_I2C2_SDA,
407 /* 24xx Menelaus interrupt */
408 W19_24XX_SYS_NIRQ,
410 /* 24xx clock */
411 W14_24XX_SYS_CLKOUT,
413 /* 24xx GPMC wait pin monitoring */
414 L3_GPMC_WAIT0,
415 N7_GPMC_WAIT1,
416 M1_GPMC_WAIT2,
417 P1_GPMC_WAIT3,
419 /* 242X McBSP */
420 Y15_24XX_MCBSP2_CLKX,
421 R14_24XX_MCBSP2_FSX,
422 W15_24XX_MCBSP2_DR,
423 V15_24XX_MCBSP2_DX,
425 /* 24xx GPIO */
426 M21_242X_GPIO11,
427 AA10_242X_GPIO13,
428 AA6_242X_GPIO14,
429 AA4_242X_GPIO15,
430 Y11_242X_GPIO16,
431 AA12_242X_GPIO17,
432 AA8_242X_GPIO58,
433 Y20_24XX_GPIO60,
434 W4__24XX_GPIO74,
435 M15_24XX_GPIO92,
436 V14_24XX_GPIO117,
438 /* 242x DBG GPIO */
439 V4_242X_GPIO49,
440 W2_242X_GPIO50,
441 U4_242X_GPIO51,
442 V3_242X_GPIO52,
443 V2_242X_GPIO53,
444 V6_242X_GPIO53,
445 T4_242X_GPIO54,
446 Y4_242X_GPIO54,
447 T3_242X_GPIO55,
448 U2_242X_GPIO56,
450 /* 24xx external DMA requests */
451 AA10_242X_DMAREQ0,
452 AA6_242X_DMAREQ1,
453 E4_242X_DMAREQ2,
454 G4_242X_DMAREQ3,
455 D3_242X_DMAREQ4,
456 E3_242X_DMAREQ5,
458 P20_24XX_TSC_IRQ,
460 /* UART3 */
461 K15_24XX_UART3_TX,
462 K14_24XX_UART3_RX,
464 /* Keypad GPIO*/
465 T19_24XX_KBR0,
466 R19_24XX_KBR1,
467 V18_24XX_KBR2,
468 M21_24XX_KBR3,
469 E5__24XX_KBR4,
470 M18_24XX_KBR5,
471 R20_24XX_KBC0,
472 M14_24XX_KBC1,
473 H19_24XX_KBC2,
474 V17_24XX_KBC3,
475 P21_24XX_KBC4,
476 L14_24XX_KBC5,
477 N19_24XX_KBC6,
479 /* 24xx Menelaus Keypad GPIO */
480 B3__24XX_KBR5,
481 AA4_24XX_KBC2,
482 B13_24XX_KBC6,
483 };
485 #ifdef CONFIG_OMAP_MUX
486 /* setup pin muxing in Linux */
487 extern int omap1_mux_init(void);
488 extern int omap2_mux_init(void);
489 extern int omap_mux_register(struct pin_config * pins, unsigned long size);
490 extern int omap_cfg_reg(unsigned long reg_cfg);
491 #else
492 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
493 static inline int omap1_mux_init(void) { return 0; }
494 static inline int omap2_mux_init(void) { return 0; }
495 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
496 #endif
498 #endif