ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-omap/mcbsp.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm-arm/arch-omap/gpio.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
27 #include <asm/hardware.h>
29 #define OMAP730_MCBSP1_BASE 0xfffb1000
30 #define OMAP730_MCBSP2_BASE 0xfffb1800
32 #define OMAP1510_MCBSP1_BASE 0xe1011800
33 #define OMAP1510_MCBSP2_BASE 0xfffb1000
34 #define OMAP1510_MCBSP3_BASE 0xe1017000
36 #define OMAP1610_MCBSP1_BASE 0xe1011800
37 #define OMAP1610_MCBSP2_BASE 0xfffb1000
38 #define OMAP1610_MCBSP3_BASE 0xe1017000
40 #define OMAP24XX_MCBSP1_BASE 0x48074000
41 #define OMAP24XX_MCBSP2_BASE 0x48076000
43 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
45 #define OMAP_MCBSP_REG_DRR2 0x00
46 #define OMAP_MCBSP_REG_DRR1 0x02
47 #define OMAP_MCBSP_REG_DXR2 0x04
48 #define OMAP_MCBSP_REG_DXR1 0x06
49 #define OMAP_MCBSP_REG_SPCR2 0x08
50 #define OMAP_MCBSP_REG_SPCR1 0x0a
51 #define OMAP_MCBSP_REG_RCR2 0x0c
52 #define OMAP_MCBSP_REG_RCR1 0x0e
53 #define OMAP_MCBSP_REG_XCR2 0x10
54 #define OMAP_MCBSP_REG_XCR1 0x12
55 #define OMAP_MCBSP_REG_SRGR2 0x14
56 #define OMAP_MCBSP_REG_SRGR1 0x16
57 #define OMAP_MCBSP_REG_MCR2 0x18
58 #define OMAP_MCBSP_REG_MCR1 0x1a
59 #define OMAP_MCBSP_REG_RCERA 0x1c
60 #define OMAP_MCBSP_REG_RCERB 0x1e
61 #define OMAP_MCBSP_REG_XCERA 0x20
62 #define OMAP_MCBSP_REG_XCERB 0x22
63 #define OMAP_MCBSP_REG_PCR0 0x24
64 #define OMAP_MCBSP_REG_RCERC 0x26
65 #define OMAP_MCBSP_REG_RCERD 0x28
66 #define OMAP_MCBSP_REG_XCERC 0x2A
67 #define OMAP_MCBSP_REG_XCERD 0x2C
68 #define OMAP_MCBSP_REG_RCERE 0x2E
69 #define OMAP_MCBSP_REG_RCERF 0x30
70 #define OMAP_MCBSP_REG_XCERE 0x32
71 #define OMAP_MCBSP_REG_XCERF 0x34
72 #define OMAP_MCBSP_REG_RCERG 0x36
73 #define OMAP_MCBSP_REG_RCERH 0x38
74 #define OMAP_MCBSP_REG_XCERG 0x3A
75 #define OMAP_MCBSP_REG_XCERH 0x3C
77 #define OMAP_MAX_MCBSP_COUNT 3
79 #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
80 #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
82 #define AUDIO_MCBSP OMAP_MCBSP1
83 #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
84 #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
86 #elif defined(CONFIG_ARCH_OMAP24XX)
88 #define OMAP_MCBSP_REG_DRR2 0x00
89 #define OMAP_MCBSP_REG_DRR1 0x04
90 #define OMAP_MCBSP_REG_DXR2 0x08
91 #define OMAP_MCBSP_REG_DXR1 0x0C
92 #define OMAP_MCBSP_REG_SPCR2 0x10
93 #define OMAP_MCBSP_REG_SPCR1 0x14
94 #define OMAP_MCBSP_REG_RCR2 0x18
95 #define OMAP_MCBSP_REG_RCR1 0x1C
96 #define OMAP_MCBSP_REG_XCR2 0x20
97 #define OMAP_MCBSP_REG_XCR1 0x24
98 #define OMAP_MCBSP_REG_SRGR2 0x28
99 #define OMAP_MCBSP_REG_SRGR1 0x2C
100 #define OMAP_MCBSP_REG_MCR2 0x30
101 #define OMAP_MCBSP_REG_MCR1 0x34
102 #define OMAP_MCBSP_REG_RCERA 0x38
103 #define OMAP_MCBSP_REG_RCERB 0x3C
104 #define OMAP_MCBSP_REG_XCERA 0x40
105 #define OMAP_MCBSP_REG_XCERB 0x44
106 #define OMAP_MCBSP_REG_PCR0 0x48
107 #define OMAP_MCBSP_REG_RCERC 0x4C
108 #define OMAP_MCBSP_REG_RCERD 0x50
109 #define OMAP_MCBSP_REG_XCERC 0x54
110 #define OMAP_MCBSP_REG_XCERD 0x58
111 #define OMAP_MCBSP_REG_RCERE 0x5C
112 #define OMAP_MCBSP_REG_RCERF 0x60
113 #define OMAP_MCBSP_REG_XCERE 0x64
114 #define OMAP_MCBSP_REG_XCERF 0x68
115 #define OMAP_MCBSP_REG_RCERG 0x6C
116 #define OMAP_MCBSP_REG_RCERH 0x70
117 #define OMAP_MCBSP_REG_XCERG 0x74
118 #define OMAP_MCBSP_REG_XCERH 0x78
120 #define OMAP_MAX_MCBSP_COUNT 2
122 #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
123 #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
125 #define AUDIO_MCBSP OMAP_MCBSP2
126 #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
127 #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
129 #endif
131 #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
132 #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
135 /************************** McBSP SPCR1 bit definitions ***********************/
136 #define RRST 0x0001
137 #define RRDY 0x0002
138 #define RFULL 0x0004
139 #define RSYNC_ERR 0x0008
140 #define RINTM(value) ((value)<<4) /* bits 4:5 */
141 #define ABIS 0x0040
142 #define DXENA 0x0080
143 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
144 #define RJUST(value) ((value)<<13) /* bits 13:14 */
145 #define DLB 0x8000
147 /************************** McBSP SPCR2 bit definitions ***********************/
148 #define XRST 0x0001
149 #define XRDY 0x0002
150 #define XEMPTY 0x0004
151 #define XSYNC_ERR 0x0008
152 #define XINTM(value) ((value)<<4) /* bits 4:5 */
153 #define GRST 0x0040
154 #define FRST 0x0080
155 #define SOFT 0x0100
156 #define FREE 0x0200
158 /************************** McBSP PCR bit definitions *************************/
159 #define CLKRP 0x0001
160 #define CLKXP 0x0002
161 #define FSRP 0x0004
162 #define FSXP 0x0008
163 #define DR_STAT 0x0010
164 #define DX_STAT 0x0020
165 #define CLKS_STAT 0x0040
166 #define SCLKME 0x0080
167 #define CLKRM 0x0100
168 #define CLKXM 0x0200
169 #define FSRM 0x0400
170 #define FSXM 0x0800
171 #define RIOEN 0x1000
172 #define XIOEN 0x2000
173 #define IDLE_EN 0x4000
175 /************************** McBSP RCR1 bit definitions ************************/
176 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
177 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
179 /************************** McBSP XCR1 bit definitions ************************/
180 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
181 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
183 /*************************** McBSP RCR2 bit definitions ***********************/
184 #define RDATDLY(value) (value) /* Bits 0:1 */
185 #define RFIG 0x0004
186 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
187 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
188 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
189 #define RPHASE 0x8000
191 /*************************** McBSP XCR2 bit definitions ***********************/
192 #define XDATDLY(value) (value) /* Bits 0:1 */
193 #define XFIG 0x0004
194 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
195 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
196 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
197 #define XPHASE 0x8000
199 /************************* McBSP SRGR1 bit definitions ************************/
200 #define CLKGDV(value) (value) /* Bits 0:7 */
201 #define FWID(value) ((value)<<8) /* Bits 8:15 */
203 /************************* McBSP SRGR2 bit definitions ************************/
204 #define FPER(value) (value) /* Bits 0:11 */
205 #define FSGM 0x1000
206 #define CLKSM 0x2000
207 #define CLKSP 0x4000
208 #define GSYNC 0x8000
210 /************************* McBSP MCR1 bit definitions *************************/
211 #define RMCM 0x0001
212 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
213 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
214 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
216 /************************* McBSP MCR2 bit definitions *************************/
217 #define XMCM(value) (value) /* Bits 0:1 */
218 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
219 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
220 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
223 /* we don't do multichannel for now */
224 struct omap_mcbsp_reg_cfg {
225 u16 spcr2;
226 u16 spcr1;
227 u16 rcr2;
228 u16 rcr1;
229 u16 xcr2;
230 u16 xcr1;
231 u16 srgr2;
232 u16 srgr1;
233 u16 mcr2;
234 u16 mcr1;
235 u16 pcr0;
236 u16 rcerc;
237 u16 rcerd;
238 u16 xcerc;
239 u16 xcerd;
240 u16 rcere;
241 u16 rcerf;
242 u16 xcere;
243 u16 xcerf;
244 u16 rcerg;
245 u16 rcerh;
246 u16 xcerg;
247 u16 xcerh;
248 };
250 typedef enum {
251 OMAP_MCBSP1 = 0,
252 OMAP_MCBSP2,
253 OMAP_MCBSP3,
254 } omap_mcbsp_id;
256 typedef int __bitwise omap_mcbsp_io_type_t;
257 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
258 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
260 typedef enum {
261 OMAP_MCBSP_WORD_8 = 0,
262 OMAP_MCBSP_WORD_12,
263 OMAP_MCBSP_WORD_16,
264 OMAP_MCBSP_WORD_20,
265 OMAP_MCBSP_WORD_24,
266 OMAP_MCBSP_WORD_32,
267 } omap_mcbsp_word_length;
269 typedef enum {
270 OMAP_MCBSP_CLK_RISING = 0,
271 OMAP_MCBSP_CLK_FALLING,
272 } omap_mcbsp_clk_polarity;
274 typedef enum {
275 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
276 OMAP_MCBSP_FS_ACTIVE_LOW,
277 } omap_mcbsp_fs_polarity;
279 typedef enum {
280 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
281 OMAP_MCBSP_CLK_STP_MODE_DELAY,
282 } omap_mcbsp_clk_stp_mode;
285 /******* SPI specific mode **********/
286 typedef enum {
287 OMAP_MCBSP_SPI_MASTER = 0,
288 OMAP_MCBSP_SPI_SLAVE,
289 } omap_mcbsp_spi_mode;
291 struct omap_mcbsp_spi_cfg {
292 omap_mcbsp_spi_mode spi_mode;
293 omap_mcbsp_clk_polarity rx_clock_polarity;
294 omap_mcbsp_clk_polarity tx_clock_polarity;
295 omap_mcbsp_fs_polarity fsx_polarity;
296 u8 clk_div;
297 omap_mcbsp_clk_stp_mode clk_stp_mode;
298 omap_mcbsp_word_length word_length;
299 };
301 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
302 int omap_mcbsp_request(unsigned int id);
303 void omap_mcbsp_free(unsigned int id);
304 void omap_mcbsp_start(unsigned int id);
305 void omap_mcbsp_stop(unsigned int id);
306 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
307 u32 omap_mcbsp_recv_word(unsigned int id);
309 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
310 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
311 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
312 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
315 /* SPI specific API */
316 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
318 /* Polled read/write functions */
319 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
320 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
322 #endif