ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-omap/dsp.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm-arm/arch-omap/dsp.h
3 *
4 * Header for OMAP DSP driver
5 *
6 * Copyright (C) 2002-2005 Nokia Corporation
7 *
8 * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * 2005/06/01: DSP Gateway version 3.3
25 */
27 #ifndef ASM_ARCH_DSP_H
28 #define ASM_ARCH_DSP_H
31 /*
32 * for /dev/dspctl/ctl
33 */
34 #define OMAP_DSP_IOCTL_RESET 1
35 #define OMAP_DSP_IOCTL_RUN 2
36 #define OMAP_DSP_IOCTL_SETRSTVECT 3
37 #define OMAP_DSP_IOCTL_CPU_IDLE 4
38 #define OMAP_DSP_IOCTL_MPUI_WORDSWAP_ON 5
39 #define OMAP_DSP_IOCTL_MPUI_WORDSWAP_OFF 6
40 #define OMAP_DSP_IOCTL_MPUI_BYTESWAP_ON 7
41 #define OMAP_DSP_IOCTL_MPUI_BYTESWAP_OFF 8
42 #define OMAP_DSP_IOCTL_GBL_IDLE 9
43 #define OMAP_DSP_IOCTL_DSPCFG 10
44 #define OMAP_DSP_IOCTL_DSPUNCFG 11
45 #define OMAP_DSP_IOCTL_TASKCNT 12
46 #define OMAP_DSP_IOCTL_POLL 13
47 #define OMAP_DSP_IOCTL_REGMEMR 40
48 #define OMAP_DSP_IOCTL_REGMEMW 41
49 #define OMAP_DSP_IOCTL_REGIOR 42
50 #define OMAP_DSP_IOCTL_REGIOW 43
51 #define OMAP_DSP_IOCTL_GETVAR 44
52 #define OMAP_DSP_IOCTL_SETVAR 45
53 #define OMAP_DSP_IOCTL_RUNLEVEL 50
54 #define OMAP_DSP_IOCTL_SUSPEND 51
55 #define OMAP_DSP_IOCTL_RESUME 52
56 #define OMAP_DSP_IOCTL_FBEN 53
57 #define OMAP_DSP_IOCTL_FBDIS 54
58 #define OMAP_DSP_IOCTL_MBSEND 99
60 /*
61 * for taskdev
62 * (ioctls below should be >= 0x10000)
63 */
64 #define OMAP_DSP_TASK_IOCTL_BFLSH 0x10000
65 #define OMAP_DSP_TASK_IOCTL_SETBSZ 0x10001
66 #define OMAP_DSP_TASK_IOCTL_LOCK 0x10002
67 #define OMAP_DSP_TASK_IOCTL_UNLOCK 0x10003
68 #define OMAP_DSP_TASK_IOCTL_GETNAME 0x10004
70 /*
71 * for /dev/dspctl/mem
72 */
73 #define OMAP_DSP_MEM_IOCTL_EXMAP 1
74 #define OMAP_DSP_MEM_IOCTL_EXUNMAP 2
75 #define OMAP_DSP_MEM_IOCTL_EXMAP_FLUSH 3
76 #define OMAP_DSP_MEM_IOCTL_FBEXPORT 5
77 #define OMAP_DSP_MEM_IOCTL_MMUITACK 7
78 #define OMAP_DSP_MEM_IOCTL_MMUINIT 9
79 #define OMAP_DSP_MEM_IOCTL_KMEM_RESERVE 11
80 #define OMAP_DSP_MEM_IOCTL_KMEM_RELEASE 12
82 struct omap_dsp_mapinfo {
83 unsigned long dspadr;
84 unsigned long size;
85 };
87 /*
88 * for /dev/dspctl/twch
89 */
90 #define OMAP_DSP_TWCH_IOCTL_MKDEV 1
91 #define OMAP_DSP_TWCH_IOCTL_RMDEV 2
92 #define OMAP_DSP_TWCH_IOCTL_TADD 11
93 #define OMAP_DSP_TWCH_IOCTL_TDEL 12
94 #define OMAP_DSP_TWCH_IOCTL_TKILL 13
96 #define OMAP_DSP_DEVSTATE_NOTASK 0x00000001
97 #define OMAP_DSP_DEVSTATE_ATTACHED 0x00000002
98 #define OMAP_DSP_DEVSTATE_GARBAGE 0x00000004
99 #define OMAP_DSP_DEVSTATE_INVALID 0x00000008
100 #define OMAP_DSP_DEVSTATE_ADDREQ 0x00000100
101 #define OMAP_DSP_DEVSTATE_DELREQ 0x00000200
102 #define OMAP_DSP_DEVSTATE_ADDFAIL 0x00001000
103 #define OMAP_DSP_DEVSTATE_ADDING 0x00010000
104 #define OMAP_DSP_DEVSTATE_DELING 0x00020000
105 #define OMAP_DSP_DEVSTATE_KILLING 0x00040000
106 #define OMAP_DSP_DEVSTATE_STATE_MASK 0x7fffffff
107 #define OMAP_DSP_DEVSTATE_STALE 0x80000000
109 struct omap_dsp_taddinfo {
110 unsigned char minor;
111 unsigned long taskadr;
112 };
113 #define OMAP_DSP_TADD_ABORTADR 0xffffffff
116 /*
117 * error cause definition (for error detection device)
118 */
119 #define OMAP_DSP_ERRDT_WDT 0x00000001
120 #define OMAP_DSP_ERRDT_MMU 0x00000002
123 /*
124 * mailbox protocol definitions
125 */
127 struct omap_dsp_mailbox_cmd {
128 unsigned short cmd;
129 unsigned short data;
130 };
132 struct omap_dsp_reginfo {
133 unsigned short adr;
134 unsigned short val;
135 };
137 struct omap_dsp_varinfo {
138 unsigned char varid;
139 unsigned short val[0];
140 };
142 #define OMAP_DSP_MBPROT_REVISION 0x0019
144 #define OMAP_DSP_MBCMD_WDSND 0x10
145 #define OMAP_DSP_MBCMD_WDREQ 0x11
146 #define OMAP_DSP_MBCMD_BKSND 0x20
147 #define OMAP_DSP_MBCMD_BKREQ 0x21
148 #define OMAP_DSP_MBCMD_BKYLD 0x23
149 #define OMAP_DSP_MBCMD_BKSNDP 0x24
150 #define OMAP_DSP_MBCMD_BKREQP 0x25
151 #define OMAP_DSP_MBCMD_TCTL 0x30
152 #define OMAP_DSP_MBCMD_TCTLDATA 0x31
153 #define OMAP_DSP_MBCMD_POLL 0x32
154 #define OMAP_DSP_MBCMD_WDT 0x50 /* v3.3: obsolete */
155 #define OMAP_DSP_MBCMD_RUNLEVEL 0x51
156 #define OMAP_DSP_MBCMD_PM 0x52
157 #define OMAP_DSP_MBCMD_SUSPEND 0x53
158 #define OMAP_DSP_MBCMD_KFUNC 0x54
159 #define OMAP_DSP_MBCMD_TCFG 0x60
160 #define OMAP_DSP_MBCMD_TADD 0x62
161 #define OMAP_DSP_MBCMD_TDEL 0x63
162 #define OMAP_DSP_MBCMD_TSTOP 0x65
163 #define OMAP_DSP_MBCMD_DSPCFG 0x70
164 #define OMAP_DSP_MBCMD_REGRW 0x72
165 #define OMAP_DSP_MBCMD_GETVAR 0x74
166 #define OMAP_DSP_MBCMD_SETVAR 0x75
167 #define OMAP_DSP_MBCMD_ERR 0x78
168 #define OMAP_DSP_MBCMD_DBG 0x79
170 #define OMAP_DSP_MBCMD_TCTL_TINIT 0x0000
171 #define OMAP_DSP_MBCMD_TCTL_TEN 0x0001
172 #define OMAP_DSP_MBCMD_TCTL_TDIS 0x0002
173 #define OMAP_DSP_MBCMD_TCTL_TCLR 0x0003
174 #define OMAP_DSP_MBCMD_TCTL_TCLR_FORCE 0x0004
176 #define OMAP_DSP_MBCMD_RUNLEVEL_USER 0x01
177 #define OMAP_DSP_MBCMD_RUNLEVEL_SUPER 0x0e
178 #define OMAP_DSP_MBCMD_RUNLEVEL_RECOVERY 0x10
180 #define OMAP_DSP_MBCMD_PM_DISABLE 0x00
181 #define OMAP_DSP_MBCMD_PM_ENABLE 0x01
183 #define OMAP_DSP_MBCMD_KFUNC_FBCTL 0x00
184 #define OMAP_DSP_MBCMD_KFUNC_AUDIO_PWR 0x01
186 #define OMAP_DSP_MBCMD_FBCTL_UPD 0x0000
187 #define OMAP_DSP_MBCMD_FBCTL_ENABLE 0x0002
188 #define OMAP_DSP_MBCMD_FBCTL_DISABLE 0x0003
190 #define OMAP_DSP_MBCMD_AUDIO_PWR_UP 0x0000
191 #define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN1 0x0001
192 #define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN2 0x0002
194 #define OMAP_DSP_MBCMD_TDEL_SAFE 0x0000
195 #define OMAP_DSP_MBCMD_TDEL_KILL 0x0001
197 #define OMAP_DSP_MBCMD_DSPCFG_REQ 0x00
198 #define OMAP_DSP_MBCMD_DSPCFG_SYSADRH 0x28
199 #define OMAP_DSP_MBCMD_DSPCFG_SYSADRL 0x29
200 #define OMAP_DSP_MBCMD_DSPCFG_PROTREV 0x70
201 #define OMAP_DSP_MBCMD_DSPCFG_ABORT 0x78
202 #define OMAP_DSP_MBCMD_DSPCFG_LAST 0x80
204 #define OMAP_DSP_MBCMD_REGRW_MEMR 0x00
205 #define OMAP_DSP_MBCMD_REGRW_MEMW 0x01
206 #define OMAP_DSP_MBCMD_REGRW_IOR 0x02
207 #define OMAP_DSP_MBCMD_REGRW_IOW 0x03
208 #define OMAP_DSP_MBCMD_REGRW_DATA 0x04
210 #define OMAP_DSP_MBCMD_VARID_ICRMASK 0x00
211 #define OMAP_DSP_MBCMD_VARID_LOADINFO 0x01
213 #define OMAP_DSP_TTYP_ARCV 0x0001
214 #define OMAP_DSP_TTYP_ASND 0x0002
215 #define OMAP_DSP_TTYP_BKMD 0x0004
216 #define OMAP_DSP_TTYP_BKDM 0x0008
217 #define OMAP_DSP_TTYP_PVMD 0x0010
218 #define OMAP_DSP_TTYP_PVDM 0x0020
220 #define OMAP_DSP_EID_BADTID 0x10
221 #define OMAP_DSP_EID_BADTCN 0x11
222 #define OMAP_DSP_EID_BADBID 0x20
223 #define OMAP_DSP_EID_BADCNT 0x21
224 #define OMAP_DSP_EID_NOTLOCKED 0x22
225 #define OMAP_DSP_EID_STVBUF 0x23
226 #define OMAP_DSP_EID_BADADR 0x24
227 #define OMAP_DSP_EID_BADTCTL 0x30
228 #define OMAP_DSP_EID_BADPARAM 0x50
229 #define OMAP_DSP_EID_FATAL 0x58
230 #define OMAP_DSP_EID_NOMEM 0xc0
231 #define OMAP_DSP_EID_NORES 0xc1
232 #define OMAP_DSP_EID_IPBFULL 0xc2
233 #define OMAP_DSP_EID_WDT 0xd0
234 #define OMAP_DSP_EID_TASKNOTRDY 0xe0
235 #define OMAP_DSP_EID_TASKBSY 0xe1
236 #define OMAP_DSP_EID_TASKERR 0xef
237 #define OMAP_DSP_EID_BADCFGTYP 0xf0
238 #define OMAP_DSP_EID_DEBUG 0xf8
239 #define OMAP_DSP_EID_BADSEQ 0xfe
240 #define OMAP_DSP_EID_BADCMD 0xff
242 #define OMAP_DSP_TNM_LEN 16
244 #define OMAP_DSP_TID_FREE 0xff
245 #define OMAP_DSP_TID_ANON 0xfe
247 #define OMAP_DSP_BID_NULL 0xffff
248 #define OMAP_DSP_BID_PVT 0xfffe
250 #endif /* ASM_ARCH_DSP_H */