ia64/linux-2.6.18-xen.hg

view include/asm-arm/arch-omap/board-fsample.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/include/asm-arm/arch-omap/board-fsample.h
3 *
4 * Board-specific goodies for TI F-Sample.
5 *
6 * Copyright (C) 2006 Google, Inc.
7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
14 #ifndef __ASM_ARCH_OMAP_FSAMPLE_H
15 #define __ASM_ARCH_OMAP_FSAMPLE_H
17 /* fsample is pretty close to p2-sample */
18 #include <asm/arch/board-perseus2.h>
20 #define fsample_cpld_read(reg) __raw_readb(reg)
21 #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
23 #define FSAMPLE_CPLD_BASE 0xE8100000
24 #define FSAMPLE_CPLD_SIZE SZ_4K
25 #define FSAMPLE_CPLD_START 0x05080000
27 #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
28 #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
29 #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
30 #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
31 #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
32 #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
34 #define FSAMPLE_CPLD_BIT_BT_RESET 0
35 #define FSAMPLE_CPLD_BIT_LCD_RESET 1
36 #define FSAMPLE_CPLD_BIT_CAM_PWDN 2
37 #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
38 #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
39 #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
40 #define FSAMPLE_CPLD_BIT_BACKLIGHT 6
41 #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
42 #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
43 #define FSAMPLE_CPLD_BIT_OTG_RESET 9
45 #define fsample_cpld_set(bit) \
46 fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
48 #define fsample_cpld_clear(bit) \
49 fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
51 #endif