ia64/linux-2.6.18-xen.hg

view arch/mips/kernel/proc.c @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * linux/arch/mips/kernel/proc.c
3 *
4 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
5 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
6 * Copyright (C) 2004 Maciej W. Rozycki
7 */
8 #include <linux/delay.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/seq_file.h>
12 #include <asm/bootinfo.h>
13 #include <asm/cpu.h>
14 #include <asm/cpu-features.h>
15 #include <asm/mipsregs.h>
16 #include <asm/processor.h>
17 #include <asm/watch.h>
19 unsigned int vced_count, vcei_count;
21 static const char *cpu_name[] = {
22 [CPU_UNKNOWN] = "unknown",
23 [CPU_R2000] = "R2000",
24 [CPU_R3000] = "R3000",
25 [CPU_R3000A] = "R3000A",
26 [CPU_R3041] = "R3041",
27 [CPU_R3051] = "R3051",
28 [CPU_R3052] = "R3052",
29 [CPU_R3081] = "R3081",
30 [CPU_R3081E] = "R3081E",
31 [CPU_R4000PC] = "R4000PC",
32 [CPU_R4000SC] = "R4000SC",
33 [CPU_R4000MC] = "R4000MC",
34 [CPU_R4200] = "R4200",
35 [CPU_R4400PC] = "R4400PC",
36 [CPU_R4400SC] = "R4400SC",
37 [CPU_R4400MC] = "R4400MC",
38 [CPU_R4600] = "R4600",
39 [CPU_R6000] = "R6000",
40 [CPU_R6000A] = "R6000A",
41 [CPU_R8000] = "R8000",
42 [CPU_R10000] = "R10000",
43 [CPU_R12000] = "R12000",
44 [CPU_R14000] = "R14000",
45 [CPU_R4300] = "R4300",
46 [CPU_R4650] = "R4650",
47 [CPU_R4700] = "R4700",
48 [CPU_R5000] = "R5000",
49 [CPU_R5000A] = "R5000A",
50 [CPU_R4640] = "R4640",
51 [CPU_NEVADA] = "Nevada",
52 [CPU_RM7000] = "RM7000",
53 [CPU_RM9000] = "RM9000",
54 [CPU_R5432] = "R5432",
55 [CPU_4KC] = "MIPS 4Kc",
56 [CPU_5KC] = "MIPS 5Kc",
57 [CPU_R4310] = "R4310",
58 [CPU_SB1] = "SiByte SB1",
59 [CPU_SB1A] = "SiByte SB1A",
60 [CPU_TX3912] = "TX3912",
61 [CPU_TX3922] = "TX3922",
62 [CPU_TX3927] = "TX3927",
63 [CPU_AU1000] = "Au1000",
64 [CPU_AU1500] = "Au1500",
65 [CPU_AU1100] = "Au1100",
66 [CPU_AU1550] = "Au1550",
67 [CPU_AU1200] = "Au1200",
68 [CPU_4KEC] = "MIPS 4KEc",
69 [CPU_4KSC] = "MIPS 4KSc",
70 [CPU_VR41XX] = "NEC Vr41xx",
71 [CPU_R5500] = "R5500",
72 [CPU_TX49XX] = "TX49xx",
73 [CPU_20KC] = "MIPS 20Kc",
74 [CPU_24K] = "MIPS 24K",
75 [CPU_25KF] = "MIPS 25Kf",
76 [CPU_34K] = "MIPS 34K",
77 [CPU_74K] = "MIPS 74K",
78 [CPU_VR4111] = "NEC VR4111",
79 [CPU_VR4121] = "NEC VR4121",
80 [CPU_VR4122] = "NEC VR4122",
81 [CPU_VR4131] = "NEC VR4131",
82 [CPU_VR4133] = "NEC VR4133",
83 [CPU_VR4181] = "NEC VR4181",
84 [CPU_VR4181A] = "NEC VR4181A",
85 [CPU_SR71000] = "Sandcraft SR71000",
86 [CPU_PR4450] = "Philips PR4450",
87 };
90 static int show_cpuinfo(struct seq_file *m, void *v)
91 {
92 unsigned int version = current_cpu_data.processor_id;
93 unsigned int fp_vers = current_cpu_data.fpu_id;
94 unsigned long n = (unsigned long) v - 1;
95 char fmt [64];
97 #ifdef CONFIG_SMP
98 if (!cpu_isset(n, cpu_online_map))
99 return 0;
100 #endif
102 /*
103 * For the first processor also print the system type
104 */
105 if (n == 0)
106 seq_printf(m, "system type\t\t: %s\n", get_system_type());
108 seq_printf(m, "processor\t\t: %ld\n", n);
109 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
110 cpu_has_fpu ? " FPU V%d.%d" : "");
111 seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ?
112 current_cpu_data.cputype : CPU_UNKNOWN],
113 (version >> 4) & 0x0f, version & 0x0f,
114 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
115 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
116 cpu_data[n].udelay_val / (500000/HZ),
117 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
118 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
119 seq_printf(m, "microsecond timers\t: %s\n",
120 cpu_has_counter ? "yes" : "no");
121 seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize);
122 seq_printf(m, "extra interrupt vector\t: %s\n",
123 cpu_has_divec ? "yes" : "no");
124 seq_printf(m, "hardware watchpoint\t: %s\n",
125 cpu_has_watch ? "yes" : "no");
126 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
127 cpu_has_mips16 ? " mips16" : "",
128 cpu_has_mdmx ? " mdmx" : "",
129 cpu_has_mips3d ? " mips3d" : "",
130 cpu_has_smartmips ? " smartmips" : "",
131 cpu_has_dsp ? " dsp" : "",
132 cpu_has_mipsmt ? " mt" : ""
133 );
135 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
136 cpu_has_vce ? "%u" : "not available");
137 seq_printf(m, fmt, 'D', vced_count);
138 seq_printf(m, fmt, 'I', vcei_count);
139 seq_printf(m, "\n");
141 return 0;
142 }
144 static void *c_start(struct seq_file *m, loff_t *pos)
145 {
146 unsigned long i = *pos;
148 return i < NR_CPUS ? (void *) (i + 1) : NULL;
149 }
151 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
152 {
153 ++*pos;
154 return c_start(m, pos);
155 }
157 static void c_stop(struct seq_file *m, void *v)
158 {
159 }
161 struct seq_operations cpuinfo_op = {
162 .start = c_start,
163 .next = c_next,
164 .stop = c_stop,
165 .show = show_cpuinfo,
166 };