ia64/linux-2.6.18-xen.hg

view arch/mips/kernel/i8259.c @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
7 *
8 * Copyright (C) 1992 Linus Torvalds
9 * Copyright (C) 1994 - 2000 Ralf Baechle
10 */
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/sysdev.h>
19 #include <asm/i8259.h>
20 #include <asm/io.h>
22 void enable_8259A_irq(unsigned int irq);
23 void disable_8259A_irq(unsigned int irq);
25 /*
26 * This is the 'legacy' 8259A Programmable Interrupt Controller,
27 * present in the majority of PC/AT boxes.
28 * plus some generic x86 specific things if generic specifics makes
29 * any sense at all.
30 * this file should become arch/i386/kernel/irq.c when the old irq.c
31 * moves to arch independent land
32 */
34 DEFINE_SPINLOCK(i8259A_lock);
36 static void end_8259A_irq (unsigned int irq)
37 {
38 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
39 irq_desc[irq].action)
40 enable_8259A_irq(irq);
41 }
43 #define shutdown_8259A_irq disable_8259A_irq
45 void mask_and_ack_8259A(unsigned int);
47 static unsigned int startup_8259A_irq(unsigned int irq)
48 {
49 enable_8259A_irq(irq);
51 return 0; /* never anything pending */
52 }
54 static struct irq_chip i8259A_irq_type = {
55 .typename = "XT-PIC",
56 .startup = startup_8259A_irq,
57 .shutdown = shutdown_8259A_irq,
58 .enable = enable_8259A_irq,
59 .disable = disable_8259A_irq,
60 .ack = mask_and_ack_8259A,
61 .end = end_8259A_irq,
62 };
64 /*
65 * 8259A PIC functions to handle ISA devices:
66 */
68 /*
69 * This contains the irq mask for both 8259A irq controllers,
70 */
71 static unsigned int cached_irq_mask = 0xffff;
73 #define cached_21 (cached_irq_mask)
74 #define cached_A1 (cached_irq_mask >> 8)
76 void disable_8259A_irq(unsigned int irq)
77 {
78 unsigned int mask = 1 << irq;
79 unsigned long flags;
81 spin_lock_irqsave(&i8259A_lock, flags);
82 cached_irq_mask |= mask;
83 if (irq & 8)
84 outb(cached_A1,0xA1);
85 else
86 outb(cached_21,0x21);
87 spin_unlock_irqrestore(&i8259A_lock, flags);
88 }
90 void enable_8259A_irq(unsigned int irq)
91 {
92 unsigned int mask = ~(1 << irq);
93 unsigned long flags;
95 spin_lock_irqsave(&i8259A_lock, flags);
96 cached_irq_mask &= mask;
97 if (irq & 8)
98 outb(cached_A1,0xA1);
99 else
100 outb(cached_21,0x21);
101 spin_unlock_irqrestore(&i8259A_lock, flags);
102 }
104 int i8259A_irq_pending(unsigned int irq)
105 {
106 unsigned int mask = 1 << irq;
107 unsigned long flags;
108 int ret;
110 spin_lock_irqsave(&i8259A_lock, flags);
111 if (irq < 8)
112 ret = inb(0x20) & mask;
113 else
114 ret = inb(0xA0) & (mask >> 8);
115 spin_unlock_irqrestore(&i8259A_lock, flags);
117 return ret;
118 }
120 void make_8259A_irq(unsigned int irq)
121 {
122 disable_irq_nosync(irq);
123 irq_desc[irq].chip = &i8259A_irq_type;
124 enable_irq(irq);
125 }
127 /*
128 * This function assumes to be called rarely. Switching between
129 * 8259A registers is slow.
130 * This has to be protected by the irq controller spinlock
131 * before being called.
132 */
133 static inline int i8259A_irq_real(unsigned int irq)
134 {
135 int value;
136 int irqmask = 1 << irq;
138 if (irq < 8) {
139 outb(0x0B,0x20); /* ISR register */
140 value = inb(0x20) & irqmask;
141 outb(0x0A,0x20); /* back to the IRR register */
142 return value;
143 }
144 outb(0x0B,0xA0); /* ISR register */
145 value = inb(0xA0) & (irqmask >> 8);
146 outb(0x0A,0xA0); /* back to the IRR register */
147 return value;
148 }
150 /*
151 * Careful! The 8259A is a fragile beast, it pretty
152 * much _has_ to be done exactly like this (mask it
153 * first, _then_ send the EOI, and the order of EOI
154 * to the two 8259s is important!
155 */
156 void mask_and_ack_8259A(unsigned int irq)
157 {
158 unsigned int irqmask = 1 << irq;
159 unsigned long flags;
161 spin_lock_irqsave(&i8259A_lock, flags);
162 /*
163 * Lightweight spurious IRQ detection. We do not want to overdo
164 * spurious IRQ handling - it's usually a sign of hardware problems, so
165 * we only do the checks we can do without slowing down good hardware
166 * nnecesserily.
167 *
168 * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting
169 * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A.
170 * Thus we can check spurious 8259A IRQs without doing the quite slow
171 * i8259A_irq_real() call for every IRQ. This does not cover 100% of
172 * spurious interrupts, but should be enough to warn the user that
173 * there is something bad going on ...
174 */
175 if (cached_irq_mask & irqmask)
176 goto spurious_8259A_irq;
177 cached_irq_mask |= irqmask;
179 handle_real_irq:
180 if (irq & 8) {
181 inb(0xA1); /* DUMMY - (do we need this?) */
182 outb(cached_A1,0xA1);
183 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
184 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
185 } else {
186 inb(0x21); /* DUMMY - (do we need this?) */
187 outb(cached_21,0x21);
188 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
189 }
190 #ifdef CONFIG_MIPS_MT_SMTC
191 if (irq_hwmask[irq] & ST0_IM)
192 set_c0_status(irq_hwmask[irq] & ST0_IM);
193 #endif /* CONFIG_MIPS_MT_SMTC */
194 spin_unlock_irqrestore(&i8259A_lock, flags);
195 return;
197 spurious_8259A_irq:
198 /*
199 * this is the slow path - should happen rarely.
200 */
201 if (i8259A_irq_real(irq))
202 /*
203 * oops, the IRQ _is_ in service according to the
204 * 8259A - not spurious, go handle it.
205 */
206 goto handle_real_irq;
208 {
209 static int spurious_irq_mask = 0;
210 /*
211 * At this point we can be sure the IRQ is spurious,
212 * lets ACK and report it. [once per IRQ]
213 */
214 if (!(spurious_irq_mask & irqmask)) {
215 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
216 spurious_irq_mask |= irqmask;
217 }
218 atomic_inc(&irq_err_count);
219 /*
220 * Theoretically we do not have to handle this IRQ,
221 * but in Linux this does not cause problems and is
222 * simpler for us.
223 */
224 goto handle_real_irq;
225 }
226 }
228 static int i8259A_resume(struct sys_device *dev)
229 {
230 init_8259A(0);
231 return 0;
232 }
234 static struct sysdev_class i8259_sysdev_class = {
235 set_kset_name("i8259"),
236 .resume = i8259A_resume,
237 };
239 static struct sys_device device_i8259A = {
240 .id = 0,
241 .cls = &i8259_sysdev_class,
242 };
244 static int __init i8259A_init_sysfs(void)
245 {
246 int error = sysdev_class_register(&i8259_sysdev_class);
247 if (!error)
248 error = sysdev_register(&device_i8259A);
249 return error;
250 }
252 device_initcall(i8259A_init_sysfs);
254 void __init init_8259A(int auto_eoi)
255 {
256 unsigned long flags;
258 spin_lock_irqsave(&i8259A_lock, flags);
260 outb(0xff, 0x21); /* mask all of 8259A-1 */
261 outb(0xff, 0xA1); /* mask all of 8259A-2 */
263 /*
264 * outb_p - this has to work on a wide range of PC hardware.
265 */
266 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
267 outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */
268 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
269 if (auto_eoi)
270 outb_p(0x03, 0x21); /* master does Auto EOI */
271 else
272 outb_p(0x01, 0x21); /* master expects normal EOI */
274 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
275 outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */
276 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
277 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
278 is to be investigated) */
280 if (auto_eoi)
281 /*
282 * in AEOI mode we just have to mask the interrupt
283 * when acking.
284 */
285 i8259A_irq_type.ack = disable_8259A_irq;
286 else
287 i8259A_irq_type.ack = mask_and_ack_8259A;
289 udelay(100); /* wait for 8259A to initialize */
291 outb(cached_21, 0x21); /* restore master IRQ mask */
292 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
294 spin_unlock_irqrestore(&i8259A_lock, flags);
295 }
297 /*
298 * IRQ2 is cascade interrupt to second interrupt controller
299 */
300 static struct irqaction irq2 = {
301 no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
302 };
304 static struct resource pic1_io_resource = {
305 .name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY
306 };
308 static struct resource pic2_io_resource = {
309 .name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY
310 };
312 /*
313 * On systems with i8259-style interrupt controllers we assume for
314 * driver compatibility reasons interrupts 0 - 15 to be the i8259
315 * interrupts even if the hardware uses a different interrupt numbering.
316 */
317 void __init init_i8259_irqs (void)
318 {
319 int i;
321 request_resource(&ioport_resource, &pic1_io_resource);
322 request_resource(&ioport_resource, &pic2_io_resource);
324 init_8259A(0);
326 for (i = 0; i < 16; i++) {
327 irq_desc[i].status = IRQ_DISABLED;
328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1;
330 irq_desc[i].chip = &i8259A_irq_type;
331 }
333 setup_irq(2, &irq2);
334 }