ia64/linux-2.6.18-xen.hg

view arch/mips/kernel/cpu-bugs64.c @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) 2003, 2004 Maciej W. Rozycki
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/ptrace.h>
12 #include <linux/stddef.h>
14 #include <asm/bugs.h>
15 #include <asm/compiler.h>
16 #include <asm/cpu.h>
17 #include <asm/fpu.h>
18 #include <asm/mipsregs.h>
19 #include <asm/system.h>
21 static inline void align_mod(const int align, const int mod)
22 {
23 asm volatile(
24 ".set push\n\t"
25 ".set noreorder\n\t"
26 ".balign %0\n\t"
27 ".rept %1\n\t"
28 "nop\n\t"
29 ".endr\n\t"
30 ".set pop"
31 :
32 : "n" (align), "n" (mod));
33 }
35 static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
36 const int align, const int mod)
37 {
38 unsigned long flags;
39 int m1, m2;
40 long p, s, lv1, lv2, lw;
42 /*
43 * We want the multiply and the shift to be isolated from the
44 * rest of the code to disable gcc optimizations. Hence the
45 * asm statements that execute nothing, but make gcc not know
46 * what the values of m1, m2 and s are and what lv2 and p are
47 * used for.
48 */
50 local_irq_save(flags);
51 /*
52 * The following code leads to a wrong result of the first
53 * dsll32 when executed on R4000 rev. 2.2 or 3.0 (PRId
54 * 00000422 or 00000430, respectively).
55 *
56 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
57 * 3.0" by MIPS Technologies, Inc., errata #16 and #28 for
58 * details. I got no permission to duplicate them here,
59 * sigh... --macro
60 */
61 asm volatile(
62 ""
63 : "=r" (m1), "=r" (m2), "=r" (s)
64 : "0" (5), "1" (8), "2" (5));
65 align_mod(align, mod);
66 /*
67 * The trailing nop is needed to fullfill the two-instruction
68 * requirement between reading hi/lo and staring a mult/div.
69 * Leaving it out may cause gas insert a nop itself breaking
70 * the desired alignment of the next chunk.
71 */
72 asm volatile(
73 ".set push\n\t"
74 ".set noat\n\t"
75 ".set noreorder\n\t"
76 ".set nomacro\n\t"
77 "mult %2, %3\n\t"
78 "dsll32 %0, %4, %5\n\t"
79 "mflo $0\n\t"
80 "dsll32 %1, %4, %5\n\t"
81 "nop\n\t"
82 ".set pop"
83 : "=&r" (lv1), "=r" (lw)
84 : "r" (m1), "r" (m2), "r" (s), "I" (0)
85 : "hi", "lo", GCC_REG_ACCUM);
86 /* We have to use single integers for m1 and m2 and a double
87 * one for p to be sure the mulsidi3 gcc's RTL multiplication
88 * instruction has the workaround applied. Older versions of
89 * gcc have correct umulsi3 and mulsi3, but other
90 * multiplication variants lack the workaround.
91 */
92 asm volatile(
93 ""
94 : "=r" (m1), "=r" (m2), "=r" (s)
95 : "0" (m1), "1" (m2), "2" (s));
96 align_mod(align, mod);
97 p = m1 * m2;
98 lv2 = s << 32;
99 asm volatile(
100 ""
101 : "=r" (lv2)
102 : "0" (lv2), "r" (p));
103 local_irq_restore(flags);
105 *v1 = lv1;
106 *v2 = lv2;
107 *w = lw;
108 }
110 static inline void check_mult_sh(void)
111 {
112 long v1[8], v2[8], w[8];
113 int bug, fix, i;
115 printk("Checking for the multiply/shift bug... ");
117 /*
118 * Testing discovered false negatives for certain code offsets
119 * into cache lines. Hence we test all possible offsets for
120 * the worst assumption of an R4000 I-cache line width of 32
121 * bytes.
122 *
123 * We can't use a loop as alignment directives need to be
124 * immediates.
125 */
126 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0);
127 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1);
128 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2);
129 mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3);
130 mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4);
131 mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5);
132 mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6);
133 mult_sh_align_mod(&v1[7], &v2[7], &w[7], 32, 7);
135 bug = 0;
136 for (i = 0; i < 8; i++)
137 if (v1[i] != w[i])
138 bug = 1;
140 if (bug == 0) {
141 printk("no.\n");
142 return;
143 }
145 printk("yes, workaround... ");
147 fix = 1;
148 for (i = 0; i < 8; i++)
149 if (v2[i] != w[i])
150 fix = 0;
152 if (fix == 1) {
153 printk("yes.\n");
154 return;
155 }
157 printk("no.\n");
158 panic("Reliable operation impossible!\n"
159 #ifndef CONFIG_CPU_R4000
160 "Configure for R4000 to enable the workaround."
161 #else
162 "Please report to <linux-mips@linux-mips.org>."
163 #endif
164 );
165 }
167 static volatile int daddi_ov __initdata = 0;
169 asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
170 {
171 daddi_ov = 1;
172 regs->cp0_epc += 4;
173 }
175 static inline void check_daddi(void)
176 {
177 extern asmlinkage void handle_daddi_ov(void);
178 unsigned long flags;
179 void *handler;
180 long v, tmp;
182 printk("Checking for the daddi bug... ");
184 local_irq_save(flags);
185 handler = set_except_vector(12, handle_daddi_ov);
186 /*
187 * The following code fails to trigger an overflow exception
188 * when executed on R4000 rev. 2.2 or 3.0 (PRId 00000422 or
189 * 00000430, respectively).
190 *
191 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
192 * 3.0" by MIPS Technologies, Inc., erratum #23 for details.
193 * I got no permission to duplicate it here, sigh... --macro
194 */
195 asm volatile(
196 ".set push\n\t"
197 ".set noat\n\t"
198 ".set noreorder\n\t"
199 ".set nomacro\n\t"
200 "addiu %1, $0, %2\n\t"
201 "dsrl %1, %1, 1\n\t"
202 #ifdef HAVE_AS_SET_DADDI
203 ".set daddi\n\t"
204 #endif
205 "daddi %0, %1, %3\n\t"
206 ".set pop"
207 : "=r" (v), "=&r" (tmp)
208 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
209 set_except_vector(12, handler);
210 local_irq_restore(flags);
212 if (daddi_ov) {
213 printk("no.\n");
214 return;
215 }
217 printk("yes, workaround... ");
219 local_irq_save(flags);
220 handler = set_except_vector(12, handle_daddi_ov);
221 asm volatile(
222 "addiu %1, $0, %2\n\t"
223 "dsrl %1, %1, 1\n\t"
224 "daddi %0, %1, %3"
225 : "=r" (v), "=&r" (tmp)
226 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
227 set_except_vector(12, handler);
228 local_irq_restore(flags);
230 if (daddi_ov) {
231 printk("yes.\n");
232 return;
233 }
235 printk("no.\n");
236 panic("Reliable operation impossible!\n"
237 #if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
238 "Configure for R4000 or R4400 to enable the workaround."
239 #else
240 "Please report to <linux-mips@linux-mips.org>."
241 #endif
242 );
243 }
245 static inline void check_daddiu(void)
246 {
247 long v, w, tmp;
249 printk("Checking for the daddiu bug... ");
251 /*
252 * The following code leads to a wrong result of daddiu when
253 * executed on R4400 rev. 1.0 (PRId 00000440).
254 *
255 * See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by
256 * MIPS Technologies, Inc., erratum #7 for details.
257 *
258 * According to "MIPS R4000PC/SC Errata, Processor Revision
259 * 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this
260 * problem affects R4000 rev. 2.2 and 3.0 (PRId 00000422 and
261 * 00000430, respectively), too. Testing failed to trigger it
262 * so far.
263 *
264 * I got no permission to duplicate the errata here, sigh...
265 * --macro
266 */
267 asm volatile(
268 ".set push\n\t"
269 ".set noat\n\t"
270 ".set noreorder\n\t"
271 ".set nomacro\n\t"
272 "addiu %2, $0, %3\n\t"
273 "dsrl %2, %2, 1\n\t"
274 #ifdef HAVE_AS_SET_DADDI
275 ".set daddi\n\t"
276 #endif
277 "daddiu %0, %2, %4\n\t"
278 "addiu %1, $0, %4\n\t"
279 "daddu %1, %2\n\t"
280 ".set pop"
281 : "=&r" (v), "=&r" (w), "=&r" (tmp)
282 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
284 if (v == w) {
285 printk("no.\n");
286 return;
287 }
289 printk("yes, workaround... ");
291 asm volatile(
292 "addiu %2, $0, %3\n\t"
293 "dsrl %2, %2, 1\n\t"
294 "daddiu %0, %2, %4\n\t"
295 "addiu %1, $0, %4\n\t"
296 "daddu %1, %2"
297 : "=&r" (v), "=&r" (w), "=&r" (tmp)
298 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
300 if (v == w) {
301 printk("yes.\n");
302 return;
303 }
305 printk("no.\n");
306 panic("Reliable operation impossible!\n"
307 #if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
308 "Configure for R4000 or R4400 to enable the workaround."
309 #else
310 "Please report to <linux-mips@linux-mips.org>."
311 #endif
312 );
313 }
315 void __init check_bugs64(void)
316 {
317 check_mult_sh();
318 check_daddi();
319 check_daddiu();
320 }