ia64/linux-2.6.18-xen.hg

view arch/mips/cobalt/irq.c @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
line source
1 /*
2 * IRQ vector handles
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
9 */
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
16 #include <asm/i8259.h>
17 #include <asm/irq_cpu.h>
18 #include <asm/gt64120.h>
19 #include <asm/ptrace.h>
21 #include <asm/mach-cobalt/cobalt.h>
23 /*
24 * We have two types of interrupts that we handle, ones that come in through
25 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
26 * mappings are:
27 *
28 * 16 - Software interrupt 0 (unused) IE_SW0
29 * 17 - Software interrupt 1 (unused) IE_SW1
30 * 18 - Galileo chip (timer) IE_IRQ0
31 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
32 * 20 - Tulip 1 IE_IRQ2
33 * 21 - 16550 UART IE_IRQ3
34 * 22 - VIA southbridge PIC IE_IRQ4
35 * 23 - unused IE_IRQ5
36 *
37 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
38 *
39 * 8 - RTC
40 * 9 - PCI
41 * 14 - IDE0
42 * 15 - IDE1
43 */
45 static inline void galileo_irq(struct pt_regs *regs)
46 {
47 unsigned int mask, pending, devfn;
49 mask = GALILEO_INL(GT_INTRMASK_OFS);
50 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
52 if (pending & GALILEO_INTR_T0EXP) {
54 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
55 do_IRQ(COBALT_GALILEO_IRQ, regs);
57 } else if (pending & GALILEO_INTR_RETRY_CTR) {
59 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
60 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
61 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
62 PCI_SLOT(devfn), PCI_FUNC(devfn));
64 } else {
66 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
67 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
68 }
69 }
71 static inline void via_pic_irq(struct pt_regs *regs)
72 {
73 int irq;
75 irq = i8259_irq();
76 if (irq >= 0)
77 do_IRQ(irq, regs);
78 }
80 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
81 {
82 unsigned pending;
84 pending = read_c0_status() & read_c0_cause();
86 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
88 galileo_irq(regs);
90 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
92 via_pic_irq(regs);
94 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
96 do_IRQ(COBALT_CPU_IRQ + 3, regs);
98 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
100 do_IRQ(COBALT_CPU_IRQ + 4, regs);
102 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
104 do_IRQ(COBALT_CPU_IRQ + 5, regs);
106 else if (pending & CAUSEF_IP7) /* IRQ 23 */
108 do_IRQ(COBALT_CPU_IRQ + 7, regs);
109 }
111 static struct irqaction irq_via = {
112 no_action, 0, { { 0, } }, "cascade", NULL, NULL
113 };
115 void __init arch_init_irq(void)
116 {
117 /*
118 * Mask all Galileo interrupts. The Galileo
119 * handler is set in cobalt_timer_setup()
120 */
121 GALILEO_OUTL(0, GT_INTRMASK_OFS);
123 init_i8259_irqs(); /* 0 ... 15 */
124 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
126 /*
127 * Mask all cpu interrupts
128 * (except IE4, we already masked those at VIA level)
129 */
130 change_c0_status(ST0_IM, IE_IRQ4);
132 setup_irq(COBALT_VIA_IRQ, &irq_via);
133 }