ia64/linux-2.6.18-xen.hg

view drivers/pci/probe.c @ 807:bca9d4cfbca2

Backport: PCI: rewrite PCI BAR reading code

commit 6ac665c63dcac8fcec534a1d224ecbb8b867ad59
Author: Matthew Wilcox <matthew@wil.cx>
Date: Mon Jul 28 13:38:59 2008 -0400

PCI: rewrite PCI BAR reading code

Factor out the code to read one BAR from the loop in
pci_read_bases into
a new function, __pci_read_base. The new code is slightly more
readable, better commented and removes the ifdef.

Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Signed-off-by: Yu Zhao <yu.zhao@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Mar 13 07:39:48 2009 +0000 (2009-03-13)
parents 831230e53067
children 31f138db8eef
line source
1 /*
2 * probe.c - PCI detection and setup code
3 */
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
23 LIST_HEAD(pci_devices);
25 #ifdef HAVE_PCI_LEGACY
26 /**
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
29 *
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
33 */
34 static void pci_create_legacy_files(struct pci_bus *b)
35 {
36 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
37 GFP_ATOMIC);
38 if (b->legacy_io) {
39 b->legacy_io->attr.name = "legacy_io";
40 b->legacy_io->size = 0xffff;
41 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
42 b->legacy_io->attr.owner = THIS_MODULE;
43 b->legacy_io->read = pci_read_legacy_io;
44 b->legacy_io->write = pci_write_legacy_io;
45 class_device_create_bin_file(&b->class_dev, b->legacy_io);
47 /* Allocated above after the legacy_io struct */
48 b->legacy_mem = b->legacy_io + 1;
49 b->legacy_mem->attr.name = "legacy_mem";
50 b->legacy_mem->size = 1024*1024;
51 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
52 b->legacy_mem->attr.owner = THIS_MODULE;
53 b->legacy_mem->mmap = pci_mmap_legacy_mem;
54 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
55 }
56 }
58 void pci_remove_legacy_files(struct pci_bus *b)
59 {
60 if (b->legacy_io) {
61 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
62 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
63 kfree(b->legacy_io); /* both are allocated here */
64 }
65 }
66 #else /* !HAVE_PCI_LEGACY */
67 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
68 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
69 #endif /* HAVE_PCI_LEGACY */
71 /*
72 * PCI Bus Class Devices
73 */
74 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
75 char *buf)
76 {
77 int ret;
78 cpumask_t cpumask;
80 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
81 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
82 if (ret < PAGE_SIZE)
83 buf[ret++] = '\n';
84 return ret;
85 }
86 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
88 /*
89 * PCI Bus Class
90 */
91 static void release_pcibus_dev(struct class_device *class_dev)
92 {
93 struct pci_bus *pci_bus = to_pci_bus(class_dev);
95 if (pci_bus->bridge)
96 put_device(pci_bus->bridge);
97 kfree(pci_bus);
98 }
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .release = &release_pcibus_dev,
103 };
105 static int __init pcibus_class_init(void)
106 {
107 return class_register(&pcibus_class);
108 }
109 postcore_initcall(pcibus_class_init);
111 /*
112 * Translate the low bits of the PCI base
113 * to the resource type
114 */
115 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
116 {
117 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
118 return IORESOURCE_IO;
120 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
121 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
123 return IORESOURCE_MEM;
124 }
126 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
127 {
128 u64 size = mask & maxbase; /* Find the significant bits */
129 if (!size)
130 return 0;
132 /* Get the lowest of them to find the decode size, and
133 from that the extent. */
134 size = (size & ~(size-1)) - 1;
136 /* base == maxbase can be valid only if the BAR has
137 already been programmed with all 1s. */
138 if (base == maxbase && ((base | size) & mask) != mask)
139 return 0;
141 return size;
142 }
144 enum pci_bar_type {
145 pci_bar_unknown, /* Standard PCI BAR probe */
146 pci_bar_io, /* An io port BAR */
147 pci_bar_mem32, /* A 32-bit memory BAR */
148 pci_bar_mem64, /* A 64-bit memory BAR */
149 };
151 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
152 {
153 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
154 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
155 return pci_bar_io;
156 }
158 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
160 if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64)
161 return pci_bar_mem64;
162 return pci_bar_mem32;
163 }
165 /*
166 * If the type is not unknown, we assume that the lowest bit is 'enable'.
167 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
168 */
169 static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
170 struct resource *res, unsigned int pos)
171 {
172 u32 l, sz, mask;
174 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
176 res->name = pci_name(dev);
178 pci_read_config_dword(dev, pos, &l);
179 pci_write_config_dword(dev, pos, mask);
180 pci_read_config_dword(dev, pos, &sz);
181 pci_write_config_dword(dev, pos, l);
183 /*
184 * All bits set in sz means the device isn't working properly.
185 * If the BAR isn't implemented, all bits must be 0. If it's a
186 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
187 * 1 must be clear.
188 */
189 if (!sz || sz == 0xffffffff)
190 goto fail;
192 /*
193 * I don't know how l can have all bits set. Copied from old code.
194 * Maybe it fixes a bug on some ancient platform.
195 */
196 if (l == 0xffffffff)
197 l = 0;
199 if (type == pci_bar_unknown) {
200 type = decode_bar(res, l);
201 res->flags |= pci_calc_resource_flags(l);
202 if (type == pci_bar_io) {
203 l &= PCI_BASE_ADDRESS_IO_MASK;
204 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
205 } else {
206 l &= PCI_BASE_ADDRESS_MEM_MASK;
207 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
208 }
209 } else {
210 res->flags |= (l & IORESOURCE_ROM_ENABLE);
211 l &= PCI_ROM_ADDRESS_MASK;
212 mask = (u32)PCI_ROM_ADDRESS_MASK;
213 }
215 if (type == pci_bar_mem64) {
216 u64 l64 = l;
217 u64 sz64 = sz;
218 u64 mask64 = mask | (u64)~0 << 32;
220 pci_read_config_dword(dev, pos + 4, &l);
221 pci_write_config_dword(dev, pos + 4, ~0);
222 pci_read_config_dword(dev, pos + 4, &sz);
223 pci_write_config_dword(dev, pos + 4, l);
225 l64 |= ((u64)l << 32);
226 sz64 |= ((u64)sz << 32);
228 sz64 = pci_size(l64, sz64, mask64);
230 if (!sz64)
231 goto fail;
233 if ((BITS_PER_LONG < 64) && (sz64 > 0x100000000ULL)) {
234 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
235 goto fail;
236 } else if ((BITS_PER_LONG < 64) && l) {
237 /* Address above 32-bit boundary; disable the BAR */
238 pci_write_config_dword(dev, pos, 0);
239 pci_write_config_dword(dev, pos + 4, 0);
240 res->start = 0;
241 res->end = sz64;
242 } else {
243 res->start = l64;
244 res->end = l64 + sz64;
245 }
246 } else {
247 sz = pci_size(l, sz, mask);
249 if (!sz)
250 goto fail;
252 res->start = l;
253 res->end = l + sz;
254 }
256 out:
257 return (type == pci_bar_mem64) ? 1 : 0;
258 fail:
259 res->flags = 0;
260 goto out;
261 }
263 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
264 {
265 unsigned int pos, reg;
267 for (pos = 0; pos < howmany; pos++) {
268 struct resource *res = &dev->resource[pos];
269 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
270 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
271 }
273 if (rom) {
274 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
275 dev->rom_base_reg = rom;
276 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
277 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
278 __pci_read_base(dev, pci_bar_mem32, res, rom);
279 }
280 }
282 void __devinit pci_read_bridge_bases(struct pci_bus *child)
283 {
284 struct pci_dev *dev = child->self;
285 u8 io_base_lo, io_limit_lo;
286 u16 mem_base_lo, mem_limit_lo;
287 unsigned long base, limit;
288 struct resource *res;
289 int i;
291 if (!dev) /* It's a host bus, nothing to read */
292 return;
294 if (dev->transparent) {
295 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
296 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
297 child->resource[i] = child->parent->resource[i - 3];
298 }
300 for(i=0; i<3; i++)
301 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
303 res = child->resource[0];
304 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
305 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
306 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
307 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
309 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
310 u16 io_base_hi, io_limit_hi;
311 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
312 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
313 base |= (io_base_hi << 16);
314 limit |= (io_limit_hi << 16);
315 }
317 if (base <= limit) {
318 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
319 if (!res->start)
320 res->start = base;
321 if (!res->end)
322 res->end = limit + 0xfff;
323 }
325 res = child->resource[1];
326 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
327 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
328 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
329 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
330 if (base <= limit) {
331 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
332 res->start = base;
333 res->end = limit + 0xfffff;
334 }
336 res = child->resource[2];
337 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
338 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
339 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
340 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
342 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
343 u32 mem_base_hi, mem_limit_hi;
344 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
345 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
347 /*
348 * Some bridges set the base > limit by default, and some
349 * (broken) BIOSes do not initialize them. If we find
350 * this, just assume they are not being used.
351 */
352 if (mem_base_hi <= mem_limit_hi) {
353 #if BITS_PER_LONG == 64
354 base |= ((long) mem_base_hi) << 32;
355 limit |= ((long) mem_limit_hi) << 32;
356 #else
357 if (mem_base_hi || mem_limit_hi) {
358 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
359 return;
360 }
361 #endif
362 }
363 }
364 if (base <= limit) {
365 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 res->start = base;
367 res->end = limit + 0xfffff;
368 }
369 }
371 static struct pci_bus * __devinit pci_alloc_bus(void)
372 {
373 struct pci_bus *b;
375 b = kzalloc(sizeof(*b), GFP_KERNEL);
376 if (b) {
377 INIT_LIST_HEAD(&b->node);
378 INIT_LIST_HEAD(&b->children);
379 INIT_LIST_HEAD(&b->devices);
380 }
381 return b;
382 }
384 static struct pci_bus * __devinit
385 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
386 {
387 struct pci_bus *child;
388 int i;
390 /*
391 * Allocate a new bus, and inherit stuff from the parent..
392 */
393 child = pci_alloc_bus();
394 if (!child)
395 return NULL;
397 child->self = bridge;
398 child->parent = parent;
399 child->ops = parent->ops;
400 child->sysdata = parent->sysdata;
401 child->bus_flags = parent->bus_flags;
402 child->bridge = get_device(&bridge->dev);
404 child->class_dev.class = &pcibus_class;
405 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
406 class_device_register(&child->class_dev);
407 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
409 /*
410 * Set up the primary, secondary and subordinate
411 * bus numbers.
412 */
413 child->number = child->secondary = busnr;
414 child->primary = parent->secondary;
415 child->subordinate = 0xff;
417 /* Set up default resource pointers and names.. */
418 for (i = 0; i < 4; i++) {
419 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
420 child->resource[i]->name = child->name;
421 }
422 bridge->subordinate = child;
424 return child;
425 }
427 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
428 {
429 struct pci_bus *child;
431 child = pci_alloc_child_bus(parent, dev, busnr);
432 if (child) {
433 down_write(&pci_bus_sem);
434 list_add_tail(&child->node, &parent->children);
435 up_write(&pci_bus_sem);
436 }
437 return child;
438 }
440 static void pci_enable_crs(struct pci_dev *dev)
441 {
442 u16 cap, rpctl;
443 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
444 if (!rpcap)
445 return;
447 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
448 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
449 return;
451 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
452 rpctl |= PCI_EXP_RTCTL_CRSSVE;
453 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
454 }
456 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
457 {
458 struct pci_bus *parent = child->parent;
460 /* Attempts to fix that up are really dangerous unless
461 we're going to re-assign all bus numbers. */
462 if (!pcibios_assign_all_busses())
463 return;
465 while (parent->parent && parent->subordinate < max) {
466 parent->subordinate = max;
467 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
468 parent = parent->parent;
469 }
470 }
472 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
474 /*
475 * If it's a bridge, configure it and scan the bus behind it.
476 * For CardBus bridges, we don't scan behind as the devices will
477 * be handled by the bridge driver itself.
478 *
479 * We need to process bridges in two passes -- first we scan those
480 * already configured by the BIOS and after we are done with all of
481 * them, we proceed to assigning numbers to the remaining buses in
482 * order to avoid overlaps between old and new bus numbers.
483 */
484 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
485 {
486 struct pci_bus *child;
487 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
488 u32 buses, i, j = 0;
489 u16 bctl;
491 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
493 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
494 pci_name(dev), buses & 0xffffff, pass);
496 /* Disable MasterAbortMode during probing to avoid reporting
497 of bus errors (in some architectures) */
498 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
499 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
500 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
502 pci_enable_crs(dev);
504 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
505 unsigned int cmax, busnr;
506 /*
507 * Bus already configured by firmware, process it in the first
508 * pass and just note the configuration.
509 */
510 if (pass)
511 goto out;
512 busnr = (buses >> 8) & 0xFF;
514 /*
515 * If we already got to this bus through a different bridge,
516 * ignore it. This can happen with the i450NX chipset.
517 */
518 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
519 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
520 pci_domain_nr(bus), busnr);
521 goto out;
522 }
524 child = pci_add_new_bus(bus, dev, busnr);
525 if (!child)
526 goto out;
527 child->primary = buses & 0xFF;
528 child->subordinate = (buses >> 16) & 0xFF;
529 child->bridge_ctl = bctl;
531 cmax = pci_scan_child_bus(child);
532 if (cmax > max)
533 max = cmax;
534 if (child->subordinate > max)
535 max = child->subordinate;
536 } else {
537 /*
538 * We need to assign a number to this bus which we always
539 * do in the second pass.
540 */
541 if (!pass) {
542 if (pcibios_assign_all_busses())
543 /* Temporarily disable forwarding of the
544 configuration cycles on all bridges in
545 this bus segment to avoid possible
546 conflicts in the second pass between two
547 bridges programmed with overlapping
548 bus ranges. */
549 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
550 buses & ~0xffffff);
551 goto out;
552 }
554 /* Clear errors */
555 pci_write_config_word(dev, PCI_STATUS, 0xffff);
557 /* Prevent assigning a bus number that already exists.
558 * This can happen when a bridge is hot-plugged */
559 if (pci_find_bus(pci_domain_nr(bus), max+1))
560 goto out;
561 child = pci_add_new_bus(bus, dev, ++max);
562 buses = (buses & 0xff000000)
563 | ((unsigned int)(child->primary) << 0)
564 | ((unsigned int)(child->secondary) << 8)
565 | ((unsigned int)(child->subordinate) << 16);
567 /*
568 * yenta.c forces a secondary latency timer of 176.
569 * Copy that behaviour here.
570 */
571 if (is_cardbus) {
572 buses &= ~0xff000000;
573 buses |= CARDBUS_LATENCY_TIMER << 24;
574 }
576 /*
577 * We need to blast all three values with a single write.
578 */
579 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
581 if (!is_cardbus) {
582 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
583 /*
584 * Adjust subordinate busnr in parent buses.
585 * We do this before scanning for children because
586 * some devices may not be detected if the bios
587 * was lazy.
588 */
589 pci_fixup_parent_subordinate_busnr(child, max);
590 /* Now we can scan all subordinate buses... */
591 max = pci_scan_child_bus(child);
592 /*
593 * now fix it up again since we have found
594 * the real value of max.
595 */
596 pci_fixup_parent_subordinate_busnr(child, max);
597 } else {
598 /*
599 * For CardBus bridges, we leave 4 bus numbers
600 * as cards with a PCI-to-PCI bridge can be
601 * inserted later.
602 */
603 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
604 struct pci_bus *parent = bus;
605 if (pci_find_bus(pci_domain_nr(bus),
606 max+i+1))
607 break;
608 while (parent->parent) {
609 if ((!pcibios_assign_all_busses()) &&
610 (parent->subordinate > max) &&
611 (parent->subordinate <= max+i)) {
612 j = 1;
613 }
614 parent = parent->parent;
615 }
616 if (j) {
617 /*
618 * Often, there are two cardbus bridges
619 * -- try to leave one valid bus number
620 * for each one.
621 */
622 i /= 2;
623 break;
624 }
625 }
626 max += i;
627 pci_fixup_parent_subordinate_busnr(child, max);
628 }
629 /*
630 * Set the subordinate bus number to its real value.
631 */
632 child->subordinate = max;
633 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
634 }
636 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
638 while (bus->parent) {
639 if ((child->subordinate > bus->subordinate) ||
640 (child->number > bus->subordinate) ||
641 (child->number < bus->number) ||
642 (child->subordinate < bus->number)) {
643 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) is "
644 "hidden behind%s bridge #%02x (-#%02x)%s\n",
645 child->number, child->subordinate,
646 bus->self->transparent ? " transparent" : " ",
647 bus->number, bus->subordinate,
648 pcibios_assign_all_busses() ? " " :
649 " (try 'pci=assign-busses')");
650 printk(KERN_WARNING "Please report the result to "
651 "linux-kernel to fix this permanently\n");
652 }
653 bus = bus->parent;
654 }
656 out:
657 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
659 return max;
660 }
662 /*
663 * Read interrupt line and base address registers.
664 * The architecture-dependent code can tweak these, of course.
665 */
666 static void pci_read_irq(struct pci_dev *dev)
667 {
668 unsigned char irq;
670 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
671 dev->pin = irq;
672 if (irq)
673 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
674 dev->irq = irq;
675 }
677 /**
678 * pci_setup_device - fill in class and map information of a device
679 * @dev: the device structure to fill
680 *
681 * Initialize the device structure with information about the device's
682 * vendor,class,memory and IO-space addresses,IRQ lines etc.
683 * Called at initialisation of the PCI subsystem and by CardBus services.
684 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
685 * or CardBus).
686 */
687 static int pci_setup_device(struct pci_dev * dev)
688 {
689 u32 class;
691 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
692 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
694 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
695 class >>= 8; /* upper 3 bytes */
696 dev->class = class;
697 class >>= 8;
699 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
700 dev->vendor, dev->device, class, dev->hdr_type);
702 /* "Unknown power state" */
703 dev->current_state = PCI_UNKNOWN;
705 /* Early fixups, before probing the BARs */
706 pci_fixup_device(pci_fixup_early, dev);
707 class = dev->class >> 8;
709 switch (dev->hdr_type) { /* header type */
710 case PCI_HEADER_TYPE_NORMAL: /* standard header */
711 if (class == PCI_CLASS_BRIDGE_PCI)
712 goto bad;
713 pci_read_irq(dev);
714 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
715 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
716 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
717 break;
719 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
720 if (class != PCI_CLASS_BRIDGE_PCI)
721 goto bad;
722 /* The PCI-to-PCI bridge spec requires that subtractive
723 decoding (i.e. transparent) bridge must have programming
724 interface code of 0x01. */
725 pci_read_irq(dev);
726 dev->transparent = ((dev->class & 0xff) == 1);
727 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
728 break;
730 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
731 if (class != PCI_CLASS_BRIDGE_CARDBUS)
732 goto bad;
733 pci_read_irq(dev);
734 pci_read_bases(dev, 1, 0);
735 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
736 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
737 break;
739 default: /* unknown header */
740 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
741 pci_name(dev), dev->hdr_type);
742 return -1;
744 bad:
745 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
746 pci_name(dev), class, dev->hdr_type);
747 dev->class = PCI_CLASS_NOT_DEFINED;
748 }
750 /* We found a fine healthy device, go go go... */
751 return 0;
752 }
754 /**
755 * pci_release_dev - free a pci device structure when all users of it are finished.
756 * @dev: device that's been disconnected
757 *
758 * Will be called only by the device core when all users of this pci device are
759 * done.
760 */
761 static void pci_release_dev(struct device *dev)
762 {
763 struct pci_dev *pci_dev;
765 pci_dev = to_pci_dev(dev);
766 kfree(pci_dev);
767 }
769 /**
770 * pci_cfg_space_size - get the configuration space size of the PCI device.
771 * @dev: PCI device
772 *
773 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
774 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
775 * access it. Maybe we don't have a way to generate extended config space
776 * accesses, or the device is behind a reverse Express bridge. So we try
777 * reading the dword at 0x100 which must either be 0 or a valid extended
778 * capability header.
779 */
780 int pci_cfg_space_size(struct pci_dev *dev)
781 {
782 int pos;
783 u32 status;
785 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
786 if (!pos) {
787 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
788 if (!pos)
789 goto fail;
791 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
792 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
793 goto fail;
794 }
796 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
797 goto fail;
798 if (status == 0xffffffff)
799 goto fail;
801 return PCI_CFG_SPACE_EXP_SIZE;
803 fail:
804 return PCI_CFG_SPACE_SIZE;
805 }
807 static void pci_release_bus_bridge_dev(struct device *dev)
808 {
809 kfree(dev);
810 }
812 /*
813 * Read the config data for a PCI device, sanity-check it
814 * and fill in the dev structure...
815 */
816 static struct pci_dev * __devinit
817 pci_scan_device(struct pci_bus *bus, int devfn)
818 {
819 struct pci_dev *dev;
820 u32 l;
821 u8 hdr_type;
822 int delay = 1;
824 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
825 return NULL;
827 /* some broken boards return 0 or ~0 if a slot is empty: */
828 if (l == 0xffffffff || l == 0x00000000 ||
829 l == 0x0000ffff || l == 0xffff0000)
830 return NULL;
832 /* Configuration request Retry Status */
833 while (l == 0xffff0001) {
834 msleep(delay);
835 delay *= 2;
836 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
837 return NULL;
838 /* Card hasn't responded in 60 seconds? Must be stuck. */
839 if (delay > 60 * 1000) {
840 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
841 "responding\n", pci_domain_nr(bus),
842 bus->number, PCI_SLOT(devfn),
843 PCI_FUNC(devfn));
844 return NULL;
845 }
846 }
848 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
849 return NULL;
851 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
852 if (!dev)
853 return NULL;
855 dev->bus = bus;
856 dev->sysdata = bus->sysdata;
857 dev->dev.parent = bus->bridge;
858 dev->dev.bus = &pci_bus_type;
859 dev->devfn = devfn;
860 dev->hdr_type = hdr_type & 0x7f;
861 dev->multifunction = !!(hdr_type & 0x80);
862 dev->vendor = l & 0xffff;
863 dev->device = (l >> 16) & 0xffff;
864 dev->cfg_size = pci_cfg_space_size(dev);
865 dev->error_state = pci_channel_io_normal;
867 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
868 set this higher, assuming the system even supports it. */
869 dev->dma_mask = 0xffffffff;
870 if (pci_setup_device(dev) < 0) {
871 kfree(dev);
872 return NULL;
873 }
875 return dev;
876 }
878 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
879 {
880 device_initialize(&dev->dev);
881 dev->dev.release = pci_release_dev;
882 pci_dev_get(dev);
884 dev->dev.dma_mask = &dev->dma_mask;
885 dev->dev.coherent_dma_mask = 0xffffffffull;
887 /* Fix up broken headers */
888 pci_fixup_device(pci_fixup_header, dev);
890 /*
891 * Add the device to our list of discovered devices
892 * and the bus list for fixup functions, etc.
893 */
894 INIT_LIST_HEAD(&dev->global_list);
895 down_write(&pci_bus_sem);
896 list_add_tail(&dev->bus_list, &bus->devices);
897 up_write(&pci_bus_sem);
898 }
900 struct pci_dev * __devinit
901 pci_scan_single_device(struct pci_bus *bus, int devfn)
902 {
903 struct pci_dev *dev;
905 dev = pci_scan_device(bus, devfn);
906 if (!dev)
907 return NULL;
909 pci_device_add(dev, bus);
910 pci_scan_msi_device(dev);
912 return dev;
913 }
915 /**
916 * pci_scan_slot - scan a PCI slot on a bus for devices.
917 * @bus: PCI bus to scan
918 * @devfn: slot number to scan (must have zero function.)
919 *
920 * Scan a PCI slot on the specified PCI bus for devices, adding
921 * discovered devices to the @bus->devices list. New devices
922 * will have an empty dev->global_list head.
923 */
924 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
925 {
926 int func, nr = 0;
927 int scan_all_fns;
929 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
931 for (func = 0; func < 8; func++, devfn++) {
932 struct pci_dev *dev;
934 dev = pci_scan_single_device(bus, devfn);
935 if (dev) {
936 nr++;
938 /*
939 * If this is a single function device,
940 * don't scan past the first function.
941 */
942 if (!dev->multifunction) {
943 if (func > 0) {
944 dev->multifunction = 1;
945 } else {
946 break;
947 }
948 }
949 } else {
950 if (func == 0 && !scan_all_fns)
951 break;
952 }
953 }
954 return nr;
955 }
957 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
958 {
959 unsigned int devfn, pass, max = bus->secondary;
960 struct pci_dev *dev;
962 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
964 /* Go find them, Rover! */
965 for (devfn = 0; devfn < 0x100; devfn += 8)
966 pci_scan_slot(bus, devfn);
968 /*
969 * After performing arch-dependent fixup of the bus, look behind
970 * all PCI-to-PCI bridges on this bus.
971 */
972 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
973 pcibios_fixup_bus(bus);
974 for (pass=0; pass < 2; pass++)
975 list_for_each_entry(dev, &bus->devices, bus_list) {
976 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
977 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
978 max = pci_scan_bridge(bus, dev, max, pass);
979 }
981 /*
982 * We've scanned the bus and so we know all about what's on
983 * the other side of any bridges that may be on this bus plus
984 * any devices.
985 *
986 * Return how far we've got finding sub-buses.
987 */
988 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
989 pci_domain_nr(bus), bus->number, max);
990 return max;
991 }
993 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
994 {
995 unsigned int max;
997 max = pci_scan_child_bus(bus);
999 /*
1000 * Make the discovered devices available.
1001 */
1002 pci_bus_add_devices(bus);
1004 return max;
1007 struct pci_bus * __devinit pci_create_bus(struct device *parent,
1008 int bus, struct pci_ops *ops, void *sysdata)
1010 int error;
1011 struct pci_bus *b;
1012 struct device *dev;
1014 b = pci_alloc_bus();
1015 if (!b)
1016 return NULL;
1018 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1019 if (!dev){
1020 kfree(b);
1021 return NULL;
1024 b->sysdata = sysdata;
1025 b->ops = ops;
1027 if (pci_find_bus(pci_domain_nr(b), bus)) {
1028 /* If we already got to this bus through a different bridge, ignore it */
1029 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1030 goto err_out;
1033 down_write(&pci_bus_sem);
1034 list_add_tail(&b->node, &pci_root_buses);
1035 up_write(&pci_bus_sem);
1037 memset(dev, 0, sizeof(*dev));
1038 dev->parent = parent;
1039 dev->release = pci_release_bus_bridge_dev;
1040 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1041 error = device_register(dev);
1042 if (error)
1043 goto dev_reg_err;
1044 b->bridge = get_device(dev);
1046 b->class_dev.class = &pcibus_class;
1047 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1048 error = class_device_register(&b->class_dev);
1049 if (error)
1050 goto class_dev_reg_err;
1051 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1052 if (error)
1053 goto class_dev_create_file_err;
1055 /* Create legacy_io and legacy_mem files for this bus */
1056 pci_create_legacy_files(b);
1058 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1059 if (error)
1060 goto sys_create_link_err;
1062 b->number = b->secondary = bus;
1063 b->resource[0] = &ioport_resource;
1064 b->resource[1] = &iomem_resource;
1066 return b;
1068 sys_create_link_err:
1069 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1070 class_dev_create_file_err:
1071 class_device_unregister(&b->class_dev);
1072 class_dev_reg_err:
1073 device_unregister(dev);
1074 dev_reg_err:
1075 down_write(&pci_bus_sem);
1076 list_del(&b->node);
1077 up_write(&pci_bus_sem);
1078 err_out:
1079 kfree(dev);
1080 kfree(b);
1081 return NULL;
1083 EXPORT_SYMBOL_GPL(pci_create_bus);
1085 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1086 int bus, struct pci_ops *ops, void *sysdata)
1088 struct pci_bus *b;
1090 b = pci_create_bus(parent, bus, ops, sysdata);
1091 if (b)
1092 b->subordinate = pci_scan_child_bus(b);
1093 return b;
1095 EXPORT_SYMBOL(pci_scan_bus_parented);
1097 #ifdef CONFIG_HOTPLUG
1098 EXPORT_SYMBOL(pci_add_new_bus);
1099 EXPORT_SYMBOL(pci_do_scan_bus);
1100 EXPORT_SYMBOL(pci_scan_slot);
1101 EXPORT_SYMBOL(pci_scan_bridge);
1102 EXPORT_SYMBOL(pci_scan_single_device);
1103 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1104 #endif