ia64/linux-2.6.18-xen.hg

view drivers/net/sfc/tenxpress.c @ 847:ad4d307bf9ce

net sfc: Update sfc and sfc_resource driver to latest release

...and update sfc_netfront, sfc_netback, sfc_netutil for any API changes

sfc_netback: Fix asymmetric use of SFC buffer table alloc and free
sfc_netback: Clean up if no SFC accel device found
sfc_netback: Gracefully handle case where page grant fails
sfc_netback: Disable net acceleration if the physical link goes down
sfc_netfront: Less verbose error messages, more verbose counters for
rx discard errors
sfc_netfront: Gracefully handle case where SFC netfront fails during
initialisation

Signed-off-by: Kieran Mansley <kmansley@solarflare.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Mar 31 11:59:10 2009 +0100 (2009-03-31)
parents 8c8a097cae69
children
line source
1 /****************************************************************************
2 * Driver for Solarflare 802.3an compliant PHY
3 * (including support for SFE4001 10GBT NIC)
4 *
5 * Copyright 2007: Solarflare Communications Inc,
6 * 9501 Jeronimo Road, Suite 250,
7 * Irvine, CA 92618, USA
8 *
9 * Developed by Solarflare Communications <linux-net-drivers@solarflare.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation, incorporated herein by reference.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ****************************************************************************/
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include "efx.h"
28 #include "debugfs.h"
29 #include "gmii.h"
30 #include "mdio_10g.h"
31 #include "falcon.h"
32 #include "phy.h"
33 #include "falcon_hwdefs.h"
34 #include "boards.h"
36 /* We expect these MMDs to be in the package */
37 /* AN not here as mdio_check_mmds() requires STAT2 support */
38 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
39 MDIO_MMDREG_DEVS0_PCS | \
40 MDIO_MMDREG_DEVS0_PHYXS)
42 #define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
43 (1 << LOOPBACK_PCS) | \
44 (1 << LOOPBACK_PMAPMD) | \
45 (1 << LOOPBACK_NETWORK))
47 /* We complain if we fail to see the link partner as 10G capable this many
48 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
49 */
50 #define MAX_BAD_LP_TRIES (5)
52 /* SNR operating margin register */
53 #define PMA_PMD_SNR_MARGIN_0 (133)
54 #define PMA_PMD_SNR_MARGIN_1 (134)
55 #define PMA_PMD_SNR_MARGIN_2 (135)
56 #define PMA_PMD_SNR_MARGIN_3 (136)
58 /* Extended control register */
59 #define PMA_PMD_XCONTROL_REG 0xc000
60 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8
61 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
62 #define PMA_PMD_AFE_POWERDOWN_LBN 9
63 #define PMA_PMD_AFE_POWERDOWN_WIDTH 1
64 #define PMA_PMD_DSP_POWERDOWN_LBN 10
65 #define PMA_PMD_DSP_POWERDOWN_WIDTH 1
66 #define PMA_PMD_PHY_POWERDOWN_LBN 11
67 #define PMA_PMD_PHY_POWERDOWN_WI
69 /* extended status register */
70 #define PMA_PMD_XSTATUS_REG 0xc001
71 #define PMA_PMD_XSTAT_FLP_LBN (12)
74 /* LED control register */
75 #define PMA_PMD_LED_CTRL_REG (0xc007)
76 #define PMA_PMA_LED_ACTIVITY_LBN (3)
78 /* LED function override register */
79 #define PMA_PMD_LED_OVERR_REG (0xc009)
80 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
81 #define PMA_PMD_LED_LINK_LBN (0)
82 #define PMA_PMD_LED_SPEED_LBN (2)
83 #define PMA_PMD_LED_TX_LBN (4)
84 #define PMA_PMD_LED_RX_LBN (6)
85 /* Override settings */
86 #define PMA_PMD_LED_AUTO (0) /* H/W control */
87 #define PMA_PMD_LED_ON (1)
88 #define PMA_PMD_LED_OFF (2)
89 #define PMA_PMD_LED_FLASH (3)
90 /* All LEDs under hardware control */
91 #define PMA_PMD_LED_FULL_AUTO (0)
92 /* Green and Amber under hardware control, Red off */
93 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
96 /* Self test (BIST) control register */
97 #define PMA_PMD_BIST_CTRL_REG (0xc014)
98 #define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */
99 #define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */
100 #define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */
101 /* Self test status register */
102 #define PMA_PMD_BIST_STAT_REG (0xc015)
103 #define PMA_PMD_BIST_ENX_LBN (3)
104 #define PMA_PMD_BIST_PMA_LBN (2)
105 #define PMA_PMD_BIST_RXD_LBN (1)
106 #define PMA_PMD_BIST_AFE_LBN (0)
108 /* Special Software reset register */
109 #define PMA_PMD_EXT_CTRL_REG 49152
110 #define PMA_PMD_EXT_SSR_LBN 15
112 #define BIST_MAX_DELAY (1000)
113 #define BIST_POLL_DELAY (10)
115 static const char *bist_names[] = {
116 [PMA_PMD_BIST_AFE_LBN] = "AFE communication",
117 [PMA_PMD_BIST_RXD_LBN] = "RX data path",
118 [PMA_PMD_BIST_PMA_LBN] = "PMA loopback",
119 [PMA_PMD_BIST_ENX_LBN] = "ENX"
120 };
122 /* Identifier registers: each identifier has 4 part number and 2 revision
123 * registers starting at one of these addresses */
124 #define PMA_PMD_AFE_ID_REG 49174
125 #define PMA_PMD_DSP_ID_REG 49180
126 #define PMA_PMD_FIRMWARE_ID_REG 49186
128 /* Misc register defines */
129 #define PCS_CLOCK_CTRL_REG 0xd801
130 #define PLL312_RST_N_LBN 2
132 #define PCS_SOFT_RST2_REG 0xd806
133 #define SERDES_RST_N_LBN 13
134 #define XGXS_RST_N_LBN 12
136 #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
137 #define CLK312_EN_LBN 3
139 /* PHYXS registers */
140 #define PHYXS_TEST1 (49162)
141 #define LOOPBACK_NEAR_LBN (8)
142 #define LOOPBACK_NEAR_WIDTH (1)
144 /* Boot status register */
145 #define PCS_BOOT_STATUS_REG (0xd000)
146 #define PCS_BOOT_FATAL_ERR_LBN (0)
147 #define PCS_BOOT_PROGRESS_LBN (1)
148 #define PCS_BOOT_PROGRESS_WIDTH (2)
149 #define PCS_BOOT_COMPLETE_LBN (3)
151 #define PCS_BOOT_MAX_DELAY (100)
152 #define PCS_BOOT_POLL_DELAY (10)
154 #define TENXPRESS_ID_PN_LEN (8)
155 #define TENXPRESS_ID_REV_LEN (4)
156 #define TENXPRESS_ID_LEN (TENXPRESS_ID_PN_LEN+1+TENXPRESS_ID_REV_LEN)
158 static const int bist_max = ARRAY_SIZE(bist_names);
160 /* Time to wait between powering down the LNPGA and turning off the power
161 * rails */
162 #define LNPGA_PDOWN_WAIT (HZ / 5)
165 static int crc_error_reset_threshold = 100;
166 module_param(crc_error_reset_threshold, int, 0644);
167 MODULE_PARM_DESC(crc_error_reset_threshold,
168 "Max number of CRC errors before XAUI reset");
170 struct tenxpress_phy_data {
171 #ifdef CONFIG_SFC_DEBUGFS
172 char phy_snr[4];
173 char phy_afe_id[TENXPRESS_ID_LEN + 1];
174 char phy_dsp_id[TENXPRESS_ID_LEN + 1];
175 char phy_firmware_id[TENXPRESS_ID_LEN + 1];
176 struct efx_nic *efx;
177 #endif
178 enum tenxpress_state state;
179 enum efx_loopback_mode loopback_mode;
180 atomic_t bad_crc_count;
181 int phy_powered;
182 int tx_disabled;
183 int bad_lp_tries;
184 };
186 static int tenxpress_state_is(struct efx_nic *efx, int state)
187 {
188 struct tenxpress_phy_data *phy_data = efx->phy_data;
189 return (phy_data != NULL) && (state == phy_data->state);
190 }
192 void tenxpress_set_state(struct efx_nic *efx,
193 enum tenxpress_state state)
194 {
195 struct tenxpress_phy_data *phy_data = efx->phy_data;
196 if (phy_data != NULL)
197 phy_data->state = state;
198 }
200 void tenxpress_crc_err(struct efx_nic *efx)
201 {
202 struct tenxpress_phy_data *phy_data = efx->phy_data;
203 if (phy_data != NULL)
204 atomic_inc(&phy_data->bad_crc_count);
205 }
207 #ifdef CONFIG_SFC_DEBUGFS
209 /* debugfs entries for this PHY */
210 static int tenxpress_ber_read(struct seq_file *file, void *data)
211 {
212 struct efx_nic *efx = *(struct efx_nic **)data;
213 int reg, ber;
215 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PCS,
216 MDIO_PCS_10GBT_STATUS2);
218 /* Extract the BER */
219 ber = (reg >> MDIO_PCS_10GBT_STATUS2_BER_LBN) &
220 ((1 << MDIO_PCS_10GBT_STATUS2_BER_WIDTH) - 1);
222 return seq_printf(file, "%d", ber);
223 }
226 static int tenxpress_snr_read(struct seq_file *file, void *data)
227 {
228 struct tenxpress_phy_data *phy_data = NULL;
229 struct efx_nic *efx;
230 int lane = *(char *) data;
231 int reg, snr;
233 EFX_BUG_ON_PARANOID(lane < 0 || lane >= 4);
234 phy_data = container_of(data, struct tenxpress_phy_data, phy_snr[lane]);
235 efx = phy_data->efx;
237 reg = mdio_clause45_read(efx, efx->mii.phy_id,
238 MDIO_MMD_PMAPMD, PMA_PMD_SNR_MARGIN_0 + lane);
240 /* Convert from SNR margin to SNR to match phychk output */
241 snr = (reg - 0x8000 + 238);
243 return seq_printf(file, "%d.%d", snr / 10, snr % 10);
244 }
247 static struct efx_debugfs_parameter debug_entries[] = {
248 EFX_PER_LANE_PARAMETER("phy_lane", "_snr",
249 struct tenxpress_phy_data, phy_snr, char,
250 tenxpress_snr_read),
251 EFX_NAMED_PARAMETER(phy_ber, struct tenxpress_phy_data, efx,
252 struct efx_nic *, tenxpress_ber_read),
253 EFX_STRING_PARAMETER(struct tenxpress_phy_data, phy_afe_id),
254 EFX_STRING_PARAMETER(struct tenxpress_phy_data, phy_dsp_id),
255 EFX_STRING_PARAMETER(struct tenxpress_phy_data, phy_firmware_id),
256 {NULL}
257 };
259 static void tenxpress_phy_get_id(struct efx_nic *efx,
260 char *id_buf, int id_addr)
261 {
262 int i, reg;
263 char ch;
265 for (i = TENXPRESS_ID_PN_LEN / 2 - 1; i >= 0; --i) {
266 reg = mdio_clause45_read(efx, efx->mii.phy_id,
267 MDIO_MMD_PMAPMD, id_addr + i);
268 ch = reg & 0xFF;
269 *id_buf++ = ch ? ch : ' ';
270 ch = (reg & 0xFF00) >> 8;
271 *id_buf++ = ch ? ch : ' ';
272 }
273 *id_buf++ = ' ';
274 for (i = TENXPRESS_ID_REV_LEN / 2 - 1; i >= 0; --i) {
275 reg = mdio_clause45_read(efx, efx->mii.phy_id,
276 MDIO_MMD_PMAPMD,
277 id_addr + TENXPRESS_ID_PN_LEN / 2 + i);
278 ch = reg & 0xFF;
279 *id_buf++ = ch ? ch : ' ';
280 ch = (reg & 0xFF00) >> 8;
281 *id_buf++ = ch ? ch : ' ';
282 }
283 }
285 static int tenxpress_debugfs_init(struct efx_nic *efx)
286 {
287 struct tenxpress_phy_data *phy_data = efx->phy_data;
288 int lane, rc;
290 for (lane = 0; lane < 4; lane++)
291 phy_data->phy_snr[lane] = lane;
293 phy_data->efx = efx;
294 rc = efx_extend_debugfs_port(efx, efx->phy_data,
295 debug_entries);
296 if (rc < 0)
297 return rc;
299 tenxpress_phy_get_id(efx, phy_data->phy_afe_id,
300 PMA_PMD_AFE_ID_REG);
301 tenxpress_phy_get_id(efx, phy_data->phy_dsp_id,
302 PMA_PMD_DSP_ID_REG);
303 tenxpress_phy_get_id(efx, phy_data->phy_firmware_id,
304 PMA_PMD_FIRMWARE_ID_REG);
306 return 0;
307 }
309 #endif /* CONFIG_SFC_DEBUGFS */
311 /* Check that the C166 has booted successfully */
312 static int tenxpress_phy_check(struct efx_nic *efx)
313 {
314 int phy_id = efx->mii.phy_id;
315 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
316 int boot_stat;
318 /* Wait for the boot to complete (or not) */
319 while (count) {
320 boot_stat = mdio_clause45_read(efx, phy_id,
321 MDIO_MMD_PCS,
322 PCS_BOOT_STATUS_REG);
323 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
324 break;
325 count--;
326 udelay(PCS_BOOT_POLL_DELAY);
327 }
329 if (!count) {
330 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
331 "%x\n", __func__,
332 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
333 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
334 return -ETIMEDOUT;
335 }
337 return 0;
338 }
340 static void tenxpress_reset_xaui(struct efx_nic *efx);
342 /* Initialise the part post power on reset or software special reset */
343 static int tenxpress_init(struct efx_nic *efx)
344 {
345 int rc, reg;
347 /* Turn on the clock */
348 reg = (1 << CLK312_EN_LBN);
349 mdio_clause45_write(efx, efx->mii.phy_id,
350 MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
352 rc = tenxpress_phy_check(efx);
353 if (rc < 0)
354 return rc;
356 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
357 reg = mdio_clause45_read(efx, efx->mii.phy_id,
358 MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
359 reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN);
360 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
361 PMA_PMD_LED_CTRL_REG, reg);
363 reg = PMA_PMD_LED_DEFAULT;
364 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
365 PMA_PMD_LED_OVERR_REG, reg);
367 return rc;
368 }
370 static int tenxpress_phy_init(struct efx_nic *efx)
371 {
372 struct tenxpress_phy_data *phy_data;
373 int rc = 0;
375 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
376 efx->phy_data = phy_data;
377 phy_data->phy_powered = efx->phy_powered;
379 tenxpress_set_state(efx, TENXPRESS_STATUS_NORMAL);
381 rc = mdio_clause45_wait_reset_mmds(efx,
382 TENXPRESS_REQUIRED_DEVS);
383 if (rc < 0)
384 goto fail;
386 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
387 if (rc < 0)
388 goto fail;
390 rc = tenxpress_init(efx);
391 if (rc < 0)
392 goto fail;
394 #ifdef CONFIG_SFC_DEBUGFS
395 rc = tenxpress_debugfs_init(efx);
396 if (rc < 0)
397 goto fail;
398 #endif
400 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
402 /* Let XGXS and SerDes out of reset and resets 10XPress */
403 falcon_reset_xaui(efx);
405 return 0;
407 fail:
408 kfree(efx->phy_data);
409 efx->phy_data = NULL;
410 return rc;
411 }
413 static int tenxpress_special_reset(struct efx_nic *efx)
414 {
415 int rc, reg;
417 EFX_TRACE(efx, "%s\n", __func__);
419 /* Initiate reset */
420 reg = mdio_clause45_read(efx, efx->mii.phy_id,
421 MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
422 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
423 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
424 PMA_PMD_EXT_CTRL_REG, reg);
426 msleep(200);
428 /* Wait for the blocks to come out of reset */
429 rc = mdio_clause45_wait_reset_mmds(efx,
430 TENXPRESS_REQUIRED_DEVS);
431 if (rc < 0)
432 return rc;
434 /* Try and reconfigure the device */
435 rc = tenxpress_init(efx);
436 if (rc < 0)
437 return rc;
439 return 0;
440 }
442 static void tenxpress_set_bad_lp(struct efx_nic *efx, int bad_lp)
443 {
444 struct tenxpress_phy_data *pd = efx->phy_data;
445 int reg;
447 /* Nothing to do if all is well and was previously so. */
448 if (!(bad_lp || pd->bad_lp_tries))
449 return;
451 reg = mdio_clause45_read(efx, efx->mii.phy_id,
452 MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);
454 if (bad_lp)
455 pd->bad_lp_tries++;
456 else
457 pd->bad_lp_tries = 0;
459 if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
460 pd->bad_lp_tries = 0; /* Restart count */
461 reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
462 reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
463 EFX_ERR(efx, "This NIC appears to be plugged into"
464 " a port that is not 10GBASE-T capable.\n"
465 " This PHY is 10GBASE-T ONLY, so no link can"
466 " be established.\n");
467 } else {
468 reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
469 }
470 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
471 PMA_PMD_LED_OVERR_REG, reg);
472 }
474 /* Check link status and return a boolean OK value. If the link is NOT
475 * OK we have a quick rummage round to see if we appear to be plugged
476 * into a non-10GBT port and if so warn the user that they won't get
477 * link any time soon as we are 10GBT only, unless caller specified
478 * not to do this check (it isn't useful in loopback) */
479 static int tenxpress_link_ok(struct efx_nic *efx, int check_lp)
480 {
481 int ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);
483 if (ok) {
484 tenxpress_set_bad_lp(efx, 0);
485 } else if (check_lp) {
486 /* Are we plugged into the wrong sort of link? */
487 int bad_lp = 0;
488 int phy_id = efx->mii.phy_id;
489 int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
490 MDIO_AN_STATUS);
491 int xphy_stat = mdio_clause45_read(efx, phy_id,
492 MDIO_MMD_PMAPMD,
493 PMA_PMD_XSTATUS_REG);
494 /* Are we plugged into anything that sends FLPs? If
495 * not we can't distinguish between not being plugged
496 * in and being plugged into a non-AN antique. The FLP
497 * bit has the advantage of not clearing when autoneg
498 * restarts. */
499 if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
500 tenxpress_set_bad_lp(efx, 0);
501 return ok;
502 }
504 /* If it can do 10GBT it must be XNP capable */
505 bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
506 if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
507 bad_lp = !(mdio_clause45_read(efx, phy_id,
508 MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
509 (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
510 }
511 tenxpress_set_bad_lp(efx, bad_lp);
512 }
513 return ok;
514 }
516 static void tenxpress_phyxs_loopback(struct efx_nic *efx)
517 {
518 int phy_id = efx->mii.phy_id;
519 int ctrl1, ctrl2;
521 ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
522 PHYXS_TEST1);
523 if (efx->loopback_mode == LOOPBACK_PHYXS)
524 ctrl2 |= (1 << LOOPBACK_NEAR_LBN);
525 else
526 ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
527 if (ctrl1 != ctrl2)
528 mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
529 PHYXS_TEST1, ctrl2);
530 }
532 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
533 {
534 struct tenxpress_phy_data *phy_data = efx->phy_data;
535 int loop_change = LOOPBACK_OUT_OF(phy_data, efx,
536 TENXPRESS_LOOPBACKS);
538 if (!tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL))
539 return;
541 /* When coming out of transmit disable, coming out of low power
542 * mode, or moving out of any PHY internal loopback mode,
543 * perform a special software reset */
544 if (((efx->phy_powered && !efx->tx_disabled) &&
545 (!phy_data->phy_powered || phy_data->tx_disabled)) ||
546 loop_change) {
547 (void) tenxpress_special_reset(efx);
548 falcon_reset_xaui(efx);
549 }
551 mdio_clause45_transmit_disable(efx, efx->tx_disabled);
552 mdio_clause45_phy_reconfigure(efx);
553 tenxpress_phyxs_loopback(efx);
555 phy_data->tx_disabled = efx->tx_disabled;
556 phy_data->loopback_mode = efx->loopback_mode;
557 phy_data->phy_powered = efx->phy_powered;
558 efx->link_up = tenxpress_link_ok(efx, 0);
559 efx->link_options = GM_LPA_10000FULL;
560 }
562 static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
563 {
564 /* Nothing done here - LASI interrupts aren't reliable so poll */
565 }
568 /* Poll PHY for interrupt */
569 static int tenxpress_phy_check_hw(struct efx_nic *efx)
570 {
571 struct tenxpress_phy_data *phy_data = efx->phy_data;
572 int phy_up = tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL);
573 int link_ok, rc = 0;
575 link_ok = phy_up && tenxpress_link_ok(efx, 1);
577 if (link_ok != efx->link_up)
578 efx->mac_op->fake_phy_event(efx);
580 /* Nothing to check if we've already shut down the PHY */
581 if (!phy_up)
582 return 0;
584 if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
585 EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
586 falcon_reset_xaui(efx);
587 atomic_set(&phy_data->bad_crc_count, 0);
588 }
590 rc = efx->board_info.monitor(efx);
591 if (rc)
592 efx->link_up = 0;
594 return rc;
595 }
597 static void tenxpress_phy_fini(struct efx_nic *efx)
598 {
599 int reg;
601 #ifdef CONFIG_SFC_DEBUGFS
602 efx_trim_debugfs_port(efx, debug_entries);
603 #endif
604 /* Power down the LNPGA */
605 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
606 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
607 PMA_PMD_XCONTROL_REG, reg);
609 /* Waiting here ensures that the board fini, which can turn off the
610 * power to the PHY, won't get run until the LNPGA powerdown has been
611 * given long enough to complete. */
612 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
614 kfree(efx->phy_data);
615 efx->phy_data = NULL;
616 }
619 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
620 * (which probably aren't wired anyway) are left in AUTO mode */
621 void tenxpress_phy_blink(struct efx_nic *efx, int blink)
622 {
623 int reg;
625 if (blink)
626 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
627 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
628 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
629 else
630 reg = PMA_PMD_LED_DEFAULT;
632 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
633 PMA_PMD_LED_OVERR_REG, reg);
634 }
636 static void tenxpress_reset_xaui(struct efx_nic *efx)
637 {
638 int phy = efx->mii.phy_id;
639 int clk_ctrl, test_select, soft_rst2;
641 /* Real work is done on clock_ctrl other resets are thought to be
642 * optional but make the reset more reliable
643 */
645 /* Read */
646 clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
647 PCS_CLOCK_CTRL_REG);
648 test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
649 PCS_TEST_SELECT_REG);
650 soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
651 PCS_SOFT_RST2_REG);
653 /* Put in reset */
654 test_select &= ~(1 << CLK312_EN_LBN);
655 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
656 PCS_TEST_SELECT_REG, test_select);
658 soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
659 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
660 PCS_SOFT_RST2_REG, soft_rst2);
662 clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
663 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
664 PCS_CLOCK_CTRL_REG, clk_ctrl);
665 udelay(10);
667 /* Remove reset */
668 clk_ctrl |= (1 << PLL312_RST_N_LBN);
669 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
670 PCS_CLOCK_CTRL_REG, clk_ctrl);
671 udelay(10);
673 soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
674 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
675 PCS_SOFT_RST2_REG, soft_rst2);
676 udelay(10);
678 test_select |= (1 << CLK312_EN_LBN);
679 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
680 PCS_TEST_SELECT_REG, test_select);
681 udelay(10);
682 }
685 struct efx_phy_operations falcon_tenxpress_phy_ops = {
686 .init = tenxpress_phy_init,
687 .reconfigure = tenxpress_phy_reconfigure,
688 .check_hw = tenxpress_phy_check_hw,
689 .fini = tenxpress_phy_fini,
690 .clear_interrupt = tenxpress_phy_clear_interrupt,
691 .reset_xaui = tenxpress_reset_xaui,
692 .mmds = TENXPRESS_REQUIRED_DEVS,
693 .loopbacks = TENXPRESS_LOOPBACKS,
694 .startup_loopback = LOOPBACK_PCS,
695 };