ia64/linux-2.6.18-xen.hg

view arch/x86_64/kernel/io_apic-xen.c @ 659:ad374a7a9f3e

Revert 654:8925ce7552528 (linux/pci-msi: translate Xen-provided PIRQs)

Breaks the -xenU configuration ("MAX_IO_APICS undefined")

Also implicated in kernel crash during save/restore in our automated
tests.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Sep 05 12:39:29 2008 +0100 (2008-09-05)
parents 8925ce755252
children 7886619f623e
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #ifdef CONFIG_ACPI
33 #include <acpi/acpi_bus.h>
34 #endif
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/proto.h>
40 #include <asm/mach_apic.h>
41 #include <asm/acpi.h>
42 #include <asm/dma.h>
43 #include <asm/nmi.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 int disable_timer_pin_1 __initdata;
53 #ifndef CONFIG_XEN
54 int timer_over_8254 __initdata = 0;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 #endif
60 static DEFINE_SPINLOCK(ioapic_lock);
61 static DEFINE_SPINLOCK(vector_lock);
63 /*
64 * # of IRQ routing registers
65 */
66 int nr_ioapic_registers[MAX_IO_APICS];
68 /*
69 * Rough estimation of how many shared IRQs there are, can
70 * be changed anytime.
71 */
72 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
73 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75 /*
76 * This is performance-critical, we want to do it O(1)
77 *
78 * the indexing order of this array favors 1:1 mappings
79 * between pins and IRQs.
80 */
82 static struct irq_pin_list {
83 short apic, pin, next;
84 } irq_2_pin[PIN_MAP_SIZE];
86 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
87 #ifdef CONFIG_PCI_MSI
88 #define vector_to_irq(vector) \
89 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #else
91 #define vector_to_irq(vector) (vector)
92 #endif
94 #ifdef CONFIG_XEN
96 #include <xen/interface/xen.h>
97 #include <xen/interface/physdev.h>
99 /* Fake i8259 */
100 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
101 #define disable_8259A_irq(_irq) ((void)0)
102 #define i8259A_irq_pending(_irq) (0)
104 unsigned long io_apic_irqs;
106 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
107 {
108 struct physdev_apic apic_op;
109 int ret;
111 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
112 apic_op.reg = reg;
113 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
114 if (ret)
115 return ret;
116 return apic_op.value;
117 }
119 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
120 {
121 struct physdev_apic apic_op;
123 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
124 apic_op.reg = reg;
125 apic_op.value = value;
126 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
127 }
129 #define io_apic_read(a,r) xen_io_apic_read(a,r)
130 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
132 #define clear_IO_APIC() ((void)0)
134 #else
136 #ifdef CONFIG_SMP
137 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
138 {
139 unsigned long flags;
140 unsigned int dest;
141 cpumask_t tmp;
143 cpus_and(tmp, mask, cpu_online_map);
144 if (cpus_empty(tmp))
145 tmp = TARGET_CPUS;
147 cpus_and(mask, tmp, CPU_MASK_ALL);
149 dest = cpu_mask_to_apicid(mask);
151 /*
152 * Only the high 8 bits are valid.
153 */
154 dest = SET_APIC_LOGICAL_ID(dest);
156 spin_lock_irqsave(&ioapic_lock, flags);
157 __DO_ACTION(1, = dest, )
158 set_irq_info(irq, mask);
159 spin_unlock_irqrestore(&ioapic_lock, flags);
160 }
161 #endif
163 #endif /* !CONFIG_XEN */
165 /*
166 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
167 * shared ISA-space IRQs, so we have to support them. We are super
168 * fast in the common case, and fast for shared ISA-space IRQs.
169 */
170 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
171 {
172 static int first_free_entry = NR_IRQS;
173 struct irq_pin_list *entry = irq_2_pin + irq;
175 BUG_ON(irq >= NR_IRQS);
176 while (entry->next)
177 entry = irq_2_pin + entry->next;
179 if (entry->pin != -1) {
180 entry->next = first_free_entry;
181 entry = irq_2_pin + entry->next;
182 if (++first_free_entry >= PIN_MAP_SIZE)
183 panic("io_apic.c: ran out of irq_2_pin entries!");
184 }
185 entry->apic = apic;
186 entry->pin = pin;
187 }
189 #ifndef CONFIG_XEN
190 #define __DO_ACTION(R, ACTION, FINAL) \
191 \
192 { \
193 int pin; \
194 struct irq_pin_list *entry = irq_2_pin + irq; \
195 \
196 BUG_ON(irq >= NR_IRQS); \
197 for (;;) { \
198 unsigned int reg; \
199 pin = entry->pin; \
200 if (pin == -1) \
201 break; \
202 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
203 reg ACTION; \
204 io_apic_modify(entry->apic, reg); \
205 if (!entry->next) \
206 break; \
207 entry = irq_2_pin + entry->next; \
208 } \
209 FINAL; \
210 }
212 #define DO_ACTION(name,R,ACTION, FINAL) \
213 \
214 static void name##_IO_APIC_irq (unsigned int irq) \
215 __DO_ACTION(R, ACTION, FINAL)
217 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
218 /* mask = 1 */
219 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
220 /* mask = 0 */
222 static void mask_IO_APIC_irq (unsigned int irq)
223 {
224 unsigned long flags;
226 spin_lock_irqsave(&ioapic_lock, flags);
227 __mask_IO_APIC_irq(irq);
228 spin_unlock_irqrestore(&ioapic_lock, flags);
229 }
231 static void unmask_IO_APIC_irq (unsigned int irq)
232 {
233 unsigned long flags;
235 spin_lock_irqsave(&ioapic_lock, flags);
236 __unmask_IO_APIC_irq(irq);
237 spin_unlock_irqrestore(&ioapic_lock, flags);
238 }
240 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
241 {
242 struct IO_APIC_route_entry entry;
243 unsigned long flags;
245 /* Check delivery_mode to be sure we're not clearing an SMI pin */
246 spin_lock_irqsave(&ioapic_lock, flags);
247 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
248 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
249 spin_unlock_irqrestore(&ioapic_lock, flags);
250 if (entry.delivery_mode == dest_SMI)
251 return;
252 /*
253 * Disable it in the IO-APIC irq-routing table:
254 */
255 memset(&entry, 0, sizeof(entry));
256 entry.mask = 1;
257 spin_lock_irqsave(&ioapic_lock, flags);
258 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
259 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
260 spin_unlock_irqrestore(&ioapic_lock, flags);
261 }
263 static void clear_IO_APIC (void)
264 {
265 int apic, pin;
267 for (apic = 0; apic < nr_ioapics; apic++)
268 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
269 clear_IO_APIC_pin(apic, pin);
270 }
272 #endif /* !CONFIG_XEN */
274 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
276 /*
277 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
278 * specific CPU-side IRQs.
279 */
281 #define MAX_PIRQS 8
282 static int pirq_entries [MAX_PIRQS];
283 static int pirqs_enabled;
284 int skip_ioapic_setup;
285 int ioapic_force;
287 /* dummy parsing: see setup.c */
289 static int __init disable_ioapic_setup(char *str)
290 {
291 skip_ioapic_setup = 1;
292 return 1;
293 }
295 static int __init enable_ioapic_setup(char *str)
296 {
297 ioapic_force = 1;
298 skip_ioapic_setup = 0;
299 return 1;
300 }
302 __setup("noapic", disable_ioapic_setup);
303 __setup("apic", enable_ioapic_setup);
305 #ifndef CONFIG_XEN
306 static int __init setup_disable_8254_timer(char *s)
307 {
308 timer_over_8254 = -1;
309 return 1;
310 }
311 static int __init setup_enable_8254_timer(char *s)
312 {
313 timer_over_8254 = 2;
314 return 1;
315 }
317 __setup("disable_8254_timer", setup_disable_8254_timer);
318 __setup("enable_8254_timer", setup_enable_8254_timer);
319 #endif /* !CONFIG_XEN */
321 #include <asm/pci-direct.h>
322 #include <linux/pci_ids.h>
323 #include <linux/pci.h>
326 #ifdef CONFIG_ACPI
328 static int nvidia_hpet_detected __initdata;
330 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
331 {
332 nvidia_hpet_detected = 1;
333 return 0;
334 }
335 #endif
337 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
338 off. Check for an Nvidia or VIA PCI bridge and turn it off.
339 Use pci direct infrastructure because this runs before the PCI subsystem.
341 Can be overwritten with "apic"
343 And another hack to disable the IOMMU on VIA chipsets.
345 ... and others. Really should move this somewhere else.
347 Kludge-O-Rama. */
348 void __init check_ioapic(void)
349 {
350 int num,slot,func;
351 /* Poor man's PCI discovery */
352 for (num = 0; num < 32; num++) {
353 for (slot = 0; slot < 32; slot++) {
354 for (func = 0; func < 8; func++) {
355 u32 class;
356 u32 vendor;
357 u8 type;
358 class = read_pci_config(num,slot,func,
359 PCI_CLASS_REVISION);
360 if (class == 0xffffffff)
361 break;
363 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
364 continue;
366 vendor = read_pci_config(num, slot, func,
367 PCI_VENDOR_ID);
368 vendor &= 0xffff;
369 switch (vendor) {
370 case PCI_VENDOR_ID_VIA:
371 #ifdef CONFIG_IOMMU
372 if ((end_pfn > MAX_DMA32_PFN ||
373 force_iommu) &&
374 !iommu_aperture_allowed) {
375 printk(KERN_INFO
376 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
377 iommu_aperture_disabled = 1;
378 }
379 #endif
380 return;
381 case PCI_VENDOR_ID_NVIDIA:
382 #ifdef CONFIG_ACPI
383 /*
384 * All timer overrides on Nvidia are
385 * wrong unless HPET is enabled.
386 */
387 nvidia_hpet_detected = 0;
388 acpi_table_parse(ACPI_HPET,
389 nvidia_hpet_check);
390 if (nvidia_hpet_detected == 0) {
391 acpi_skip_timer_override = 1;
392 printk(KERN_INFO "Nvidia board "
393 "detected. Ignoring ACPI "
394 "timer override.\n");
395 }
396 #endif
397 /* RED-PEN skip them on mptables too? */
398 return;
399 case PCI_VENDOR_ID_ATI:
401 /* This should be actually default, but
402 for 2.6.16 let's do it for ATI only where
403 it's really needed. */
404 #ifndef CONFIG_XEN
405 if (timer_over_8254 == 1) {
406 timer_over_8254 = 0;
407 printk(KERN_INFO
408 "ATI board detected. Disabling timer routing over 8254.\n");
409 }
410 #endif
411 return;
412 }
415 /* No multi-function device? */
416 type = read_pci_config_byte(num,slot,func,
417 PCI_HEADER_TYPE);
418 if (!(type & 0x80))
419 break;
420 }
421 }
422 }
423 }
425 static int __init ioapic_pirq_setup(char *str)
426 {
427 int i, max;
428 int ints[MAX_PIRQS+1];
430 get_options(str, ARRAY_SIZE(ints), ints);
432 for (i = 0; i < MAX_PIRQS; i++)
433 pirq_entries[i] = -1;
435 pirqs_enabled = 1;
436 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
437 max = MAX_PIRQS;
438 if (ints[0] < MAX_PIRQS)
439 max = ints[0];
441 for (i = 0; i < max; i++) {
442 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
443 /*
444 * PIRQs are mapped upside down, usually.
445 */
446 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
447 }
448 return 1;
449 }
451 __setup("pirq=", ioapic_pirq_setup);
453 /*
454 * Find the IRQ entry number of a certain pin.
455 */
456 static int find_irq_entry(int apic, int pin, int type)
457 {
458 int i;
460 for (i = 0; i < mp_irq_entries; i++)
461 if (mp_irqs[i].mpc_irqtype == type &&
462 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
463 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
464 mp_irqs[i].mpc_dstirq == pin)
465 return i;
467 return -1;
468 }
470 #ifndef CONFIG_XEN
471 /*
472 * Find the pin to which IRQ[irq] (ISA) is connected
473 */
474 static int __init find_isa_irq_pin(int irq, int type)
475 {
476 int i;
478 for (i = 0; i < mp_irq_entries; i++) {
479 int lbus = mp_irqs[i].mpc_srcbus;
481 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
482 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
483 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
484 (mp_irqs[i].mpc_irqtype == type) &&
485 (mp_irqs[i].mpc_srcbusirq == irq))
487 return mp_irqs[i].mpc_dstirq;
488 }
489 return -1;
490 }
492 static int __init find_isa_irq_apic(int irq, int type)
493 {
494 int i;
496 for (i = 0; i < mp_irq_entries; i++) {
497 int lbus = mp_irqs[i].mpc_srcbus;
499 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
500 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
501 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
502 (mp_irqs[i].mpc_irqtype == type) &&
503 (mp_irqs[i].mpc_srcbusirq == irq))
504 break;
505 }
506 if (i < mp_irq_entries) {
507 int apic;
508 for(apic = 0; apic < nr_ioapics; apic++) {
509 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
510 return apic;
511 }
512 }
514 return -1;
515 }
516 #endif
518 /*
519 * Find a specific PCI IRQ entry.
520 * Not an __init, possibly needed by modules
521 */
522 static int pin_2_irq(int idx, int apic, int pin);
524 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
525 {
526 int apic, i, best_guess = -1;
528 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
529 bus, slot, pin);
530 if (mp_bus_id_to_pci_bus[bus] == -1) {
531 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
532 return -1;
533 }
534 for (i = 0; i < mp_irq_entries; i++) {
535 int lbus = mp_irqs[i].mpc_srcbus;
537 for (apic = 0; apic < nr_ioapics; apic++)
538 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
539 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
540 break;
542 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
543 !mp_irqs[i].mpc_irqtype &&
544 (bus == lbus) &&
545 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
546 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
548 if (!(apic || IO_APIC_IRQ(irq)))
549 continue;
551 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
552 return irq;
553 /*
554 * Use the first all-but-pin matching entry as a
555 * best-guess fuzzy result for broken mptables.
556 */
557 if (best_guess < 0)
558 best_guess = irq;
559 }
560 }
561 BUG_ON(best_guess >= NR_IRQS);
562 return best_guess;
563 }
565 /*
566 * EISA Edge/Level control register, ELCR
567 */
568 static int EISA_ELCR(unsigned int irq)
569 {
570 if (irq < 16) {
571 unsigned int port = 0x4d0 + (irq >> 3);
572 return (inb(port) >> (irq & 7)) & 1;
573 }
574 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
575 return 0;
576 }
578 /* EISA interrupts are always polarity zero and can be edge or level
579 * trigger depending on the ELCR value. If an interrupt is listed as
580 * EISA conforming in the MP table, that means its trigger type must
581 * be read in from the ELCR */
583 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
584 #define default_EISA_polarity(idx) (0)
586 /* ISA interrupts are always polarity zero edge triggered,
587 * when listed as conforming in the MP table. */
589 #define default_ISA_trigger(idx) (0)
590 #define default_ISA_polarity(idx) (0)
592 /* PCI interrupts are always polarity one level triggered,
593 * when listed as conforming in the MP table. */
595 #define default_PCI_trigger(idx) (1)
596 #define default_PCI_polarity(idx) (1)
598 /* MCA interrupts are always polarity zero level triggered,
599 * when listed as conforming in the MP table. */
601 #define default_MCA_trigger(idx) (1)
602 #define default_MCA_polarity(idx) (0)
604 static int __init MPBIOS_polarity(int idx)
605 {
606 int bus = mp_irqs[idx].mpc_srcbus;
607 int polarity;
609 /*
610 * Determine IRQ line polarity (high active or low active):
611 */
612 switch (mp_irqs[idx].mpc_irqflag & 3)
613 {
614 case 0: /* conforms, ie. bus-type dependent polarity */
615 {
616 switch (mp_bus_id_to_type[bus])
617 {
618 case MP_BUS_ISA: /* ISA pin */
619 {
620 polarity = default_ISA_polarity(idx);
621 break;
622 }
623 case MP_BUS_EISA: /* EISA pin */
624 {
625 polarity = default_EISA_polarity(idx);
626 break;
627 }
628 case MP_BUS_PCI: /* PCI pin */
629 {
630 polarity = default_PCI_polarity(idx);
631 break;
632 }
633 case MP_BUS_MCA: /* MCA pin */
634 {
635 polarity = default_MCA_polarity(idx);
636 break;
637 }
638 default:
639 {
640 printk(KERN_WARNING "broken BIOS!!\n");
641 polarity = 1;
642 break;
643 }
644 }
645 break;
646 }
647 case 1: /* high active */
648 {
649 polarity = 0;
650 break;
651 }
652 case 2: /* reserved */
653 {
654 printk(KERN_WARNING "broken BIOS!!\n");
655 polarity = 1;
656 break;
657 }
658 case 3: /* low active */
659 {
660 polarity = 1;
661 break;
662 }
663 default: /* invalid */
664 {
665 printk(KERN_WARNING "broken BIOS!!\n");
666 polarity = 1;
667 break;
668 }
669 }
670 return polarity;
671 }
673 static int MPBIOS_trigger(int idx)
674 {
675 int bus = mp_irqs[idx].mpc_srcbus;
676 int trigger;
678 /*
679 * Determine IRQ trigger mode (edge or level sensitive):
680 */
681 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
682 {
683 case 0: /* conforms, ie. bus-type dependent */
684 {
685 switch (mp_bus_id_to_type[bus])
686 {
687 case MP_BUS_ISA: /* ISA pin */
688 {
689 trigger = default_ISA_trigger(idx);
690 break;
691 }
692 case MP_BUS_EISA: /* EISA pin */
693 {
694 trigger = default_EISA_trigger(idx);
695 break;
696 }
697 case MP_BUS_PCI: /* PCI pin */
698 {
699 trigger = default_PCI_trigger(idx);
700 break;
701 }
702 case MP_BUS_MCA: /* MCA pin */
703 {
704 trigger = default_MCA_trigger(idx);
705 break;
706 }
707 default:
708 {
709 printk(KERN_WARNING "broken BIOS!!\n");
710 trigger = 1;
711 break;
712 }
713 }
714 break;
715 }
716 case 1: /* edge */
717 {
718 trigger = 0;
719 break;
720 }
721 case 2: /* reserved */
722 {
723 printk(KERN_WARNING "broken BIOS!!\n");
724 trigger = 1;
725 break;
726 }
727 case 3: /* level */
728 {
729 trigger = 1;
730 break;
731 }
732 default: /* invalid */
733 {
734 printk(KERN_WARNING "broken BIOS!!\n");
735 trigger = 0;
736 break;
737 }
738 }
739 return trigger;
740 }
742 static inline int irq_polarity(int idx)
743 {
744 return MPBIOS_polarity(idx);
745 }
747 static inline int irq_trigger(int idx)
748 {
749 return MPBIOS_trigger(idx);
750 }
752 static int next_irq = 16;
754 /*
755 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
756 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
757 * from ACPI, which can reach 800 in large boxen.
758 *
759 * Compact the sparse GSI space into a sequential IRQ series and reuse
760 * vectors if possible.
761 */
762 int gsi_irq_sharing(int gsi)
763 {
764 int i, tries, vector;
766 BUG_ON(gsi >= NR_IRQ_VECTORS);
768 if (platform_legacy_irq(gsi))
769 return gsi;
771 if (gsi_2_irq[gsi] != 0xFF)
772 return (int)gsi_2_irq[gsi];
774 tries = NR_IRQS;
775 try_again:
776 vector = assign_irq_vector(gsi);
778 /*
779 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
780 * use of vector and if found, return that IRQ. However, we never want
781 * to share legacy IRQs, which usually have a different trigger mode
782 * than PCI.
783 */
784 for (i = 0; i < NR_IRQS; i++)
785 if (IO_APIC_VECTOR(i) == vector)
786 break;
787 if (platform_legacy_irq(i)) {
788 if (--tries >= 0) {
789 IO_APIC_VECTOR(i) = 0;
790 goto try_again;
791 }
792 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
793 }
794 if (i < NR_IRQS) {
795 gsi_2_irq[gsi] = i;
796 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
797 gsi, vector, i);
798 return i;
799 }
801 i = next_irq++;
802 BUG_ON(i >= NR_IRQS);
803 gsi_2_irq[gsi] = i;
804 IO_APIC_VECTOR(i) = vector;
805 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
806 gsi, vector, i);
807 return i;
808 }
810 static int pin_2_irq(int idx, int apic, int pin)
811 {
812 int irq, i;
813 int bus = mp_irqs[idx].mpc_srcbus;
815 /*
816 * Debugging check, we are in big trouble if this message pops up!
817 */
818 if (mp_irqs[idx].mpc_dstirq != pin)
819 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
821 switch (mp_bus_id_to_type[bus])
822 {
823 case MP_BUS_ISA: /* ISA pin */
824 case MP_BUS_EISA:
825 case MP_BUS_MCA:
826 {
827 irq = mp_irqs[idx].mpc_srcbusirq;
828 break;
829 }
830 case MP_BUS_PCI: /* PCI pin */
831 {
832 /*
833 * PCI IRQs are mapped in order
834 */
835 i = irq = 0;
836 while (i < apic)
837 irq += nr_ioapic_registers[i++];
838 irq += pin;
839 irq = gsi_irq_sharing(irq);
840 break;
841 }
842 default:
843 {
844 printk(KERN_ERR "unknown bus type %d.\n",bus);
845 irq = 0;
846 break;
847 }
848 }
849 BUG_ON(irq >= NR_IRQS);
851 /*
852 * PCI IRQ command line redirection. Yes, limits are hardcoded.
853 */
854 if ((pin >= 16) && (pin <= 23)) {
855 if (pirq_entries[pin-16] != -1) {
856 if (!pirq_entries[pin-16]) {
857 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
858 } else {
859 irq = pirq_entries[pin-16];
860 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
861 pin-16, irq);
862 }
863 }
864 }
865 BUG_ON(irq >= NR_IRQS);
866 return irq;
867 }
869 static inline int IO_APIC_irq_trigger(int irq)
870 {
871 int apic, idx, pin;
873 for (apic = 0; apic < nr_ioapics; apic++) {
874 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
875 idx = find_irq_entry(apic,pin,mp_INT);
876 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
877 return irq_trigger(idx);
878 }
879 }
880 /*
881 * nonexistent IRQs are edge default
882 */
883 return 0;
884 }
886 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
887 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
889 int assign_irq_vector(int irq)
890 {
891 unsigned long flags;
892 int vector;
893 struct physdev_irq irq_op;
895 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
897 spin_lock_irqsave(&vector_lock, flags);
899 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
900 spin_unlock_irqrestore(&vector_lock, flags);
901 return IO_APIC_VECTOR(irq);
902 }
904 irq_op.irq = irq;
905 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
906 spin_unlock_irqrestore(&vector_lock, flags);
907 return -ENOSPC;
908 }
910 vector = irq_op.vector;
911 vector_irq[vector] = irq;
912 if (irq != AUTO_ASSIGN)
913 IO_APIC_VECTOR(irq) = vector;
915 spin_unlock_irqrestore(&vector_lock, flags);
917 return vector;
918 }
920 extern void (*interrupt[NR_IRQS])(void);
921 #ifndef CONFIG_XEN
922 static struct hw_interrupt_type ioapic_level_type;
923 static struct hw_interrupt_type ioapic_edge_type;
925 #define IOAPIC_AUTO -1
926 #define IOAPIC_EDGE 0
927 #define IOAPIC_LEVEL 1
929 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
930 {
931 unsigned idx;
933 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
935 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
936 trigger == IOAPIC_LEVEL)
937 irq_desc[idx].chip = &ioapic_level_type;
938 else
939 irq_desc[idx].chip = &ioapic_edge_type;
940 set_intr_gate(vector, interrupt[idx]);
941 }
942 #else
943 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
944 #endif /* !CONFIG_XEN */
946 static void __init setup_IO_APIC_irqs(void)
947 {
948 struct IO_APIC_route_entry entry;
949 int apic, pin, idx, irq, first_notcon = 1, vector;
950 unsigned long flags;
952 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
954 for (apic = 0; apic < nr_ioapics; apic++) {
955 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
957 /*
958 * add it to the IO-APIC irq-routing table:
959 */
960 memset(&entry,0,sizeof(entry));
962 entry.delivery_mode = INT_DELIVERY_MODE;
963 entry.dest_mode = INT_DEST_MODE;
964 entry.mask = 0; /* enable IRQ */
965 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
967 idx = find_irq_entry(apic,pin,mp_INT);
968 if (idx == -1) {
969 if (first_notcon) {
970 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
971 first_notcon = 0;
972 } else
973 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
974 continue;
975 }
977 entry.trigger = irq_trigger(idx);
978 entry.polarity = irq_polarity(idx);
980 if (irq_trigger(idx)) {
981 entry.trigger = 1;
982 entry.mask = 1;
983 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
984 }
986 irq = pin_2_irq(idx, apic, pin);
987 add_pin_to_irq(irq, apic, pin);
989 if (/* !apic && */ !IO_APIC_IRQ(irq))
990 continue;
992 if (IO_APIC_IRQ(irq)) {
993 vector = assign_irq_vector(irq);
994 entry.vector = vector;
996 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
997 if (!apic && (irq < 16))
998 disable_8259A_irq(irq);
999 }
1000 spin_lock_irqsave(&ioapic_lock, flags);
1001 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1002 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1003 set_native_irq_info(irq, TARGET_CPUS);
1004 spin_unlock_irqrestore(&ioapic_lock, flags);
1008 if (!first_notcon)
1009 apic_printk(APIC_VERBOSE," not connected.\n");
1012 #ifndef CONFIG_XEN
1013 /*
1014 * Set up the 8259A-master output pin as broadcast to all
1015 * CPUs.
1016 */
1017 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1019 struct IO_APIC_route_entry entry;
1020 unsigned long flags;
1022 memset(&entry,0,sizeof(entry));
1024 disable_8259A_irq(0);
1026 /* mask LVT0 */
1027 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1029 /*
1030 * We use logical delivery to get the timer IRQ
1031 * to the first CPU.
1032 */
1033 entry.dest_mode = INT_DEST_MODE;
1034 entry.mask = 0; /* unmask IRQ now */
1035 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1036 entry.delivery_mode = INT_DELIVERY_MODE;
1037 entry.polarity = 0;
1038 entry.trigger = 0;
1039 entry.vector = vector;
1041 /*
1042 * The timer IRQ doesn't have to know that behind the
1043 * scene we have a 8259A-master in AEOI mode ...
1044 */
1045 irq_desc[0].chip = &ioapic_edge_type;
1047 /*
1048 * Add it to the IO-APIC irq-routing table:
1049 */
1050 spin_lock_irqsave(&ioapic_lock, flags);
1051 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1052 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1053 spin_unlock_irqrestore(&ioapic_lock, flags);
1055 enable_8259A_irq(0);
1058 void __init UNEXPECTED_IO_APIC(void)
1062 void __apicdebuginit print_IO_APIC(void)
1064 int apic, i;
1065 union IO_APIC_reg_00 reg_00;
1066 union IO_APIC_reg_01 reg_01;
1067 union IO_APIC_reg_02 reg_02;
1068 unsigned long flags;
1070 if (apic_verbosity == APIC_QUIET)
1071 return;
1073 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1074 for (i = 0; i < nr_ioapics; i++)
1075 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1076 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1078 /*
1079 * We are a bit conservative about what we expect. We have to
1080 * know about every hardware change ASAP.
1081 */
1082 printk(KERN_INFO "testing the IO APIC.......................\n");
1084 for (apic = 0; apic < nr_ioapics; apic++) {
1086 spin_lock_irqsave(&ioapic_lock, flags);
1087 reg_00.raw = io_apic_read(apic, 0);
1088 reg_01.raw = io_apic_read(apic, 1);
1089 if (reg_01.bits.version >= 0x10)
1090 reg_02.raw = io_apic_read(apic, 2);
1091 spin_unlock_irqrestore(&ioapic_lock, flags);
1093 printk("\n");
1094 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1095 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1096 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1097 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1098 UNEXPECTED_IO_APIC();
1100 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1101 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1102 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1103 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1104 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1105 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1106 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1107 (reg_01.bits.entries != 0x2E) &&
1108 (reg_01.bits.entries != 0x3F) &&
1109 (reg_01.bits.entries != 0x03)
1111 UNEXPECTED_IO_APIC();
1113 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1114 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1115 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1116 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1117 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1118 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1119 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1120 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1122 UNEXPECTED_IO_APIC();
1123 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1124 UNEXPECTED_IO_APIC();
1126 if (reg_01.bits.version >= 0x10) {
1127 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1128 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1129 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1130 UNEXPECTED_IO_APIC();
1133 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1135 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1136 " Stat Dest Deli Vect: \n");
1138 for (i = 0; i <= reg_01.bits.entries; i++) {
1139 struct IO_APIC_route_entry entry;
1141 spin_lock_irqsave(&ioapic_lock, flags);
1142 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1143 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1144 spin_unlock_irqrestore(&ioapic_lock, flags);
1146 printk(KERN_DEBUG " %02x %03X %02X ",
1147 i,
1148 entry.dest.logical.logical_dest,
1149 entry.dest.physical.physical_dest
1150 );
1152 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1153 entry.mask,
1154 entry.trigger,
1155 entry.irr,
1156 entry.polarity,
1157 entry.delivery_status,
1158 entry.dest_mode,
1159 entry.delivery_mode,
1160 entry.vector
1161 );
1164 if (use_pci_vector())
1165 printk(KERN_INFO "Using vector-based indexing\n");
1166 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1167 for (i = 0; i < NR_IRQS; i++) {
1168 struct irq_pin_list *entry = irq_2_pin + i;
1169 if (entry->pin < 0)
1170 continue;
1171 if (use_pci_vector() && !platform_legacy_irq(i))
1172 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1173 else
1174 printk(KERN_DEBUG "IRQ%d ", i);
1175 for (;;) {
1176 printk("-> %d:%d", entry->apic, entry->pin);
1177 if (!entry->next)
1178 break;
1179 entry = irq_2_pin + entry->next;
1181 printk("\n");
1184 printk(KERN_INFO ".................................... done.\n");
1186 return;
1189 static __apicdebuginit void print_APIC_bitfield (int base)
1191 unsigned int v;
1192 int i, j;
1194 if (apic_verbosity == APIC_QUIET)
1195 return;
1197 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1198 for (i = 0; i < 8; i++) {
1199 v = apic_read(base + i*0x10);
1200 for (j = 0; j < 32; j++) {
1201 if (v & (1<<j))
1202 printk("1");
1203 else
1204 printk("0");
1206 printk("\n");
1210 void __apicdebuginit print_local_APIC(void * dummy)
1212 unsigned int v, ver, maxlvt;
1214 if (apic_verbosity == APIC_QUIET)
1215 return;
1217 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1218 smp_processor_id(), hard_smp_processor_id());
1219 v = apic_read(APIC_ID);
1220 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1221 v = apic_read(APIC_LVR);
1222 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1223 ver = GET_APIC_VERSION(v);
1224 maxlvt = get_maxlvt();
1226 v = apic_read(APIC_TASKPRI);
1227 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1229 v = apic_read(APIC_ARBPRI);
1230 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1231 v & APIC_ARBPRI_MASK);
1232 v = apic_read(APIC_PROCPRI);
1233 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1235 v = apic_read(APIC_EOI);
1236 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1237 v = apic_read(APIC_RRR);
1238 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1239 v = apic_read(APIC_LDR);
1240 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1241 v = apic_read(APIC_DFR);
1242 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1243 v = apic_read(APIC_SPIV);
1244 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1246 printk(KERN_DEBUG "... APIC ISR field:\n");
1247 print_APIC_bitfield(APIC_ISR);
1248 printk(KERN_DEBUG "... APIC TMR field:\n");
1249 print_APIC_bitfield(APIC_TMR);
1250 printk(KERN_DEBUG "... APIC IRR field:\n");
1251 print_APIC_bitfield(APIC_IRR);
1253 v = apic_read(APIC_ESR);
1254 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1256 v = apic_read(APIC_ICR);
1257 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1258 v = apic_read(APIC_ICR2);
1259 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1261 v = apic_read(APIC_LVTT);
1262 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1264 if (maxlvt > 3) { /* PC is LVT#4. */
1265 v = apic_read(APIC_LVTPC);
1266 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1268 v = apic_read(APIC_LVT0);
1269 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1270 v = apic_read(APIC_LVT1);
1271 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1273 if (maxlvt > 2) { /* ERR is LVT#3. */
1274 v = apic_read(APIC_LVTERR);
1275 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1278 v = apic_read(APIC_TMICT);
1279 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1280 v = apic_read(APIC_TMCCT);
1281 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1282 v = apic_read(APIC_TDCR);
1283 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1284 printk("\n");
1287 void print_all_local_APICs (void)
1289 on_each_cpu(print_local_APIC, NULL, 1, 1);
1292 void __apicdebuginit print_PIC(void)
1294 unsigned int v;
1295 unsigned long flags;
1297 if (apic_verbosity == APIC_QUIET)
1298 return;
1300 printk(KERN_DEBUG "\nprinting PIC contents\n");
1302 spin_lock_irqsave(&i8259A_lock, flags);
1304 v = inb(0xa1) << 8 | inb(0x21);
1305 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1307 v = inb(0xa0) << 8 | inb(0x20);
1308 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1310 outb(0x0b,0xa0);
1311 outb(0x0b,0x20);
1312 v = inb(0xa0) << 8 | inb(0x20);
1313 outb(0x0a,0xa0);
1314 outb(0x0a,0x20);
1316 spin_unlock_irqrestore(&i8259A_lock, flags);
1318 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1320 v = inb(0x4d1) << 8 | inb(0x4d0);
1321 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1323 #endif /* !CONFIG_XEN */
1325 static void __init enable_IO_APIC(void)
1327 union IO_APIC_reg_01 reg_01;
1328 #ifndef CONFIG_XEN
1329 int i8259_apic, i8259_pin;
1330 #endif
1331 int i, apic;
1332 unsigned long flags;
1334 for (i = 0; i < PIN_MAP_SIZE; i++) {
1335 irq_2_pin[i].pin = -1;
1336 irq_2_pin[i].next = 0;
1338 if (!pirqs_enabled)
1339 for (i = 0; i < MAX_PIRQS; i++)
1340 pirq_entries[i] = -1;
1342 /*
1343 * The number of IO-APIC IRQ registers (== #pins):
1344 */
1345 for (apic = 0; apic < nr_ioapics; apic++) {
1346 spin_lock_irqsave(&ioapic_lock, flags);
1347 reg_01.raw = io_apic_read(apic, 1);
1348 spin_unlock_irqrestore(&ioapic_lock, flags);
1349 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1351 #ifndef CONFIG_XEN
1352 for(apic = 0; apic < nr_ioapics; apic++) {
1353 int pin;
1354 /* See if any of the pins is in ExtINT mode */
1355 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1356 struct IO_APIC_route_entry entry;
1357 spin_lock_irqsave(&ioapic_lock, flags);
1358 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1359 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1360 spin_unlock_irqrestore(&ioapic_lock, flags);
1363 /* If the interrupt line is enabled and in ExtInt mode
1364 * I have found the pin where the i8259 is connected.
1365 */
1366 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1367 ioapic_i8259.apic = apic;
1368 ioapic_i8259.pin = pin;
1369 goto found_i8259;
1373 found_i8259:
1374 /* Look to see what if the MP table has reported the ExtINT */
1375 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1376 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1377 /* Trust the MP table if nothing is setup in the hardware */
1378 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1379 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1380 ioapic_i8259.pin = i8259_pin;
1381 ioapic_i8259.apic = i8259_apic;
1383 /* Complain if the MP table and the hardware disagree */
1384 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1385 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1387 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1389 #endif
1391 /*
1392 * Do not trust the IO-APIC being empty at bootup
1393 */
1394 clear_IO_APIC();
1397 /*
1398 * Not an __init, needed by the reboot code
1399 */
1400 void disable_IO_APIC(void)
1402 /*
1403 * Clear the IO-APIC before rebooting:
1404 */
1405 clear_IO_APIC();
1407 #ifndef CONFIG_XEN
1408 /*
1409 * If the i8259 is routed through an IOAPIC
1410 * Put that IOAPIC in virtual wire mode
1411 * so legacy interrupts can be delivered.
1412 */
1413 if (ioapic_i8259.pin != -1) {
1414 struct IO_APIC_route_entry entry;
1415 unsigned long flags;
1417 memset(&entry, 0, sizeof(entry));
1418 entry.mask = 0; /* Enabled */
1419 entry.trigger = 0; /* Edge */
1420 entry.irr = 0;
1421 entry.polarity = 0; /* High */
1422 entry.delivery_status = 0;
1423 entry.dest_mode = 0; /* Physical */
1424 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1425 entry.vector = 0;
1426 entry.dest.physical.physical_dest =
1427 GET_APIC_ID(apic_read(APIC_ID));
1429 /*
1430 * Add it to the IO-APIC irq-routing table:
1431 */
1432 spin_lock_irqsave(&ioapic_lock, flags);
1433 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1434 *(((int *)&entry)+1));
1435 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1436 *(((int *)&entry)+0));
1437 spin_unlock_irqrestore(&ioapic_lock, flags);
1440 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1441 #endif
1444 /*
1445 * function to set the IO-APIC physical IDs based on the
1446 * values stored in the MPC table.
1448 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1449 */
1451 #ifndef CONFIG_XEN
1452 static void __init setup_ioapic_ids_from_mpc (void)
1454 union IO_APIC_reg_00 reg_00;
1455 int apic;
1456 int i;
1457 unsigned char old_id;
1458 unsigned long flags;
1460 /*
1461 * Set the IOAPIC ID to the value stored in the MPC table.
1462 */
1463 for (apic = 0; apic < nr_ioapics; apic++) {
1465 /* Read the register 0 value */
1466 spin_lock_irqsave(&ioapic_lock, flags);
1467 reg_00.raw = io_apic_read(apic, 0);
1468 spin_unlock_irqrestore(&ioapic_lock, flags);
1470 old_id = mp_ioapics[apic].mpc_apicid;
1473 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1476 /*
1477 * We need to adjust the IRQ routing table
1478 * if the ID changed.
1479 */
1480 if (old_id != mp_ioapics[apic].mpc_apicid)
1481 for (i = 0; i < mp_irq_entries; i++)
1482 if (mp_irqs[i].mpc_dstapic == old_id)
1483 mp_irqs[i].mpc_dstapic
1484 = mp_ioapics[apic].mpc_apicid;
1486 /*
1487 * Read the right value from the MPC table and
1488 * write it into the ID register.
1489 */
1490 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1491 mp_ioapics[apic].mpc_apicid);
1493 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1494 spin_lock_irqsave(&ioapic_lock, flags);
1495 io_apic_write(apic, 0, reg_00.raw);
1496 spin_unlock_irqrestore(&ioapic_lock, flags);
1498 /*
1499 * Sanity check
1500 */
1501 spin_lock_irqsave(&ioapic_lock, flags);
1502 reg_00.raw = io_apic_read(apic, 0);
1503 spin_unlock_irqrestore(&ioapic_lock, flags);
1504 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1505 printk("could not set ID!\n");
1506 else
1507 apic_printk(APIC_VERBOSE," ok.\n");
1510 #else
1511 static void __init setup_ioapic_ids_from_mpc(void) { }
1512 #endif
1514 /*
1515 * There is a nasty bug in some older SMP boards, their mptable lies
1516 * about the timer IRQ. We do the following to work around the situation:
1518 * - timer IRQ defaults to IO-APIC IRQ
1519 * - if this function detects that timer IRQs are defunct, then we fall
1520 * back to ISA timer IRQs
1521 */
1522 #ifndef CONFIG_XEN
1523 static int __init timer_irq_works(void)
1525 unsigned long t1 = jiffies;
1527 local_irq_enable();
1528 /* Let ten ticks pass... */
1529 mdelay((10 * 1000) / HZ);
1531 /*
1532 * Expect a few ticks at least, to be sure some possible
1533 * glue logic does not lock up after one or two first
1534 * ticks in a non-ExtINT mode. Also the local APIC
1535 * might have cached one ExtINT interrupt. Finally, at
1536 * least one tick may be lost due to delays.
1537 */
1539 /* jiffies wrap? */
1540 if (jiffies - t1 > 4)
1541 return 1;
1542 return 0;
1545 /*
1546 * In the SMP+IOAPIC case it might happen that there are an unspecified
1547 * number of pending IRQ events unhandled. These cases are very rare,
1548 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1549 * better to do it this way as thus we do not have to be aware of
1550 * 'pending' interrupts in the IRQ path, except at this point.
1551 */
1552 /*
1553 * Edge triggered needs to resend any interrupt
1554 * that was delayed but this is now handled in the device
1555 * independent code.
1556 */
1558 /*
1559 * Starting up a edge-triggered IO-APIC interrupt is
1560 * nasty - we need to make sure that we get the edge.
1561 * If it is already asserted for some reason, we need
1562 * return 1 to indicate that is was pending.
1564 * This is not complete - we should be able to fake
1565 * an edge even if it isn't on the 8259A...
1566 */
1568 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1570 int was_pending = 0;
1571 unsigned long flags;
1573 spin_lock_irqsave(&ioapic_lock, flags);
1574 if (irq < 16) {
1575 disable_8259A_irq(irq);
1576 if (i8259A_irq_pending(irq))
1577 was_pending = 1;
1579 __unmask_IO_APIC_irq(irq);
1580 spin_unlock_irqrestore(&ioapic_lock, flags);
1582 return was_pending;
1585 /*
1586 * Once we have recorded IRQ_PENDING already, we can mask the
1587 * interrupt for real. This prevents IRQ storms from unhandled
1588 * devices.
1589 */
1590 static void ack_edge_ioapic_irq(unsigned int irq)
1592 move_irq(irq);
1593 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1594 == (IRQ_PENDING | IRQ_DISABLED))
1595 mask_IO_APIC_irq(irq);
1596 ack_APIC_irq();
1599 /*
1600 * Level triggered interrupts can just be masked,
1601 * and shutting down and starting up the interrupt
1602 * is the same as enabling and disabling them -- except
1603 * with a startup need to return a "was pending" value.
1605 * Level triggered interrupts are special because we
1606 * do not touch any IO-APIC register while handling
1607 * them. We ack the APIC in the end-IRQ handler, not
1608 * in the start-IRQ-handler. Protection against reentrance
1609 * from the same interrupt is still provided, both by the
1610 * generic IRQ layer and by the fact that an unacked local
1611 * APIC does not accept IRQs.
1612 */
1613 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1615 unmask_IO_APIC_irq(irq);
1617 return 0; /* don't check for pending */
1620 static void end_level_ioapic_irq (unsigned int irq)
1622 move_irq(irq);
1623 ack_APIC_irq();
1626 #ifdef CONFIG_PCI_MSI
1627 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1629 int irq = vector_to_irq(vector);
1631 return startup_edge_ioapic_irq(irq);
1634 static void ack_edge_ioapic_vector(unsigned int vector)
1636 int irq = vector_to_irq(vector);
1638 move_native_irq(vector);
1639 ack_edge_ioapic_irq(irq);
1642 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1644 int irq = vector_to_irq(vector);
1646 return startup_level_ioapic_irq (irq);
1649 static void end_level_ioapic_vector (unsigned int vector)
1651 int irq = vector_to_irq(vector);
1653 move_native_irq(vector);
1654 end_level_ioapic_irq(irq);
1657 static void mask_IO_APIC_vector (unsigned int vector)
1659 int irq = vector_to_irq(vector);
1661 mask_IO_APIC_irq(irq);
1664 static void unmask_IO_APIC_vector (unsigned int vector)
1666 int irq = vector_to_irq(vector);
1668 unmask_IO_APIC_irq(irq);
1671 #ifdef CONFIG_SMP
1672 static void set_ioapic_affinity_vector (unsigned int vector,
1673 cpumask_t cpu_mask)
1675 int irq = vector_to_irq(vector);
1677 set_native_irq_info(vector, cpu_mask);
1678 set_ioapic_affinity_irq(irq, cpu_mask);
1680 #endif // CONFIG_SMP
1681 #endif // CONFIG_PCI_MSI
1683 static int ioapic_retrigger(unsigned int irq)
1685 send_IPI_self(IO_APIC_VECTOR(irq));
1687 return 1;
1690 /*
1691 * Level and edge triggered IO-APIC interrupts need different handling,
1692 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1693 * handled with the level-triggered descriptor, but that one has slightly
1694 * more overhead. Level-triggered interrupts cannot be handled with the
1695 * edge-triggered handler, without risking IRQ storms and other ugly
1696 * races.
1697 */
1699 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1700 .typename = "IO-APIC-edge",
1701 .startup = startup_edge_ioapic,
1702 .shutdown = shutdown_edge_ioapic,
1703 .enable = enable_edge_ioapic,
1704 .disable = disable_edge_ioapic,
1705 .ack = ack_edge_ioapic,
1706 .end = end_edge_ioapic,
1707 #ifdef CONFIG_SMP
1708 .set_affinity = set_ioapic_affinity,
1709 #endif
1710 .retrigger = ioapic_retrigger,
1711 };
1713 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1714 .typename = "IO-APIC-level",
1715 .startup = startup_level_ioapic,
1716 .shutdown = shutdown_level_ioapic,
1717 .enable = enable_level_ioapic,
1718 .disable = disable_level_ioapic,
1719 .ack = mask_and_ack_level_ioapic,
1720 .end = end_level_ioapic,
1721 #ifdef CONFIG_SMP
1722 .set_affinity = set_ioapic_affinity,
1723 #endif
1724 .retrigger = ioapic_retrigger,
1725 };
1726 #endif /* !CONFIG_XEN */
1728 static inline void init_IO_APIC_traps(void)
1730 int irq;
1732 /*
1733 * NOTE! The local APIC isn't very good at handling
1734 * multiple interrupts at the same interrupt level.
1735 * As the interrupt level is determined by taking the
1736 * vector number and shifting that right by 4, we
1737 * want to spread these out a bit so that they don't
1738 * all fall in the same interrupt level.
1740 * Also, we've got to be careful not to trash gate
1741 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1742 */
1743 for (irq = 0; irq < NR_IRQS ; irq++) {
1744 int tmp = irq;
1745 if (use_pci_vector()) {
1746 if (!platform_legacy_irq(tmp))
1747 if ((tmp = vector_to_irq(tmp)) == -1)
1748 continue;
1750 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1751 /*
1752 * Hmm.. We don't have an entry for this,
1753 * so default to an old-fashioned 8259
1754 * interrupt if we can..
1755 */
1756 if (irq < 16)
1757 make_8259A_irq(irq);
1758 #ifndef CONFIG_XEN
1759 else
1760 /* Strange. Oh, well.. */
1761 irq_desc[irq].chip = &no_irq_type;
1762 #endif
1767 #ifndef CONFIG_XEN
1768 static void enable_lapic_irq (unsigned int irq)
1770 unsigned long v;
1772 v = apic_read(APIC_LVT0);
1773 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1776 static void disable_lapic_irq (unsigned int irq)
1778 unsigned long v;
1780 v = apic_read(APIC_LVT0);
1781 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1784 static void ack_lapic_irq (unsigned int irq)
1786 ack_APIC_irq();
1789 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1791 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1792 .typename = "local-APIC-edge",
1793 .startup = NULL, /* startup_irq() not used for IRQ0 */
1794 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1795 .enable = enable_lapic_irq,
1796 .disable = disable_lapic_irq,
1797 .ack = ack_lapic_irq,
1798 .end = end_lapic_irq,
1799 };
1801 static void setup_nmi (void)
1803 /*
1804 * Dirty trick to enable the NMI watchdog ...
1805 * We put the 8259A master into AEOI mode and
1806 * unmask on all local APICs LVT0 as NMI.
1808 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1809 * is from Maciej W. Rozycki - so we do not have to EOI from
1810 * the NMI handler or the timer interrupt.
1811 */
1812 printk(KERN_INFO "activating NMI Watchdog ...");
1814 enable_NMI_through_LVT0(NULL);
1816 printk(" done.\n");
1819 /*
1820 * This looks a bit hackish but it's about the only one way of sending
1821 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1822 * not support the ExtINT mode, unfortunately. We need to send these
1823 * cycles as some i82489DX-based boards have glue logic that keeps the
1824 * 8259A interrupt line asserted until INTA. --macro
1825 */
1826 static inline void unlock_ExtINT_logic(void)
1828 int apic, pin, i;
1829 struct IO_APIC_route_entry entry0, entry1;
1830 unsigned char save_control, save_freq_select;
1831 unsigned long flags;
1833 pin = find_isa_irq_pin(8, mp_INT);
1834 apic = find_isa_irq_apic(8, mp_INT);
1835 if (pin == -1)
1836 return;
1838 spin_lock_irqsave(&ioapic_lock, flags);
1839 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1840 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1841 spin_unlock_irqrestore(&ioapic_lock, flags);
1842 clear_IO_APIC_pin(apic, pin);
1844 memset(&entry1, 0, sizeof(entry1));
1846 entry1.dest_mode = 0; /* physical delivery */
1847 entry1.mask = 0; /* unmask IRQ now */
1848 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1849 entry1.delivery_mode = dest_ExtINT;
1850 entry1.polarity = entry0.polarity;
1851 entry1.trigger = 0;
1852 entry1.vector = 0;
1854 spin_lock_irqsave(&ioapic_lock, flags);
1855 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1856 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1857 spin_unlock_irqrestore(&ioapic_lock, flags);
1859 save_control = CMOS_READ(RTC_CONTROL);
1860 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1861 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1862 RTC_FREQ_SELECT);
1863 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1865 i = 100;
1866 while (i-- > 0) {
1867 mdelay(10);
1868 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1869 i -= 10;
1872 CMOS_WRITE(save_control, RTC_CONTROL);
1873 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1874 clear_IO_APIC_pin(apic, pin);
1876 spin_lock_irqsave(&ioapic_lock, flags);
1877 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1878 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1879 spin_unlock_irqrestore(&ioapic_lock, flags);
1882 int timer_uses_ioapic_pin_0;
1884 /*
1885 * This code may look a bit paranoid, but it's supposed to cooperate with
1886 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1887 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1888 * fanatically on his truly buggy board.
1890 * FIXME: really need to revamp this for modern platforms only.
1891 */
1892 static inline void check_timer(void)
1894 int apic1, pin1, apic2, pin2;
1895 int vector;
1897 /*
1898 * get/set the timer IRQ vector:
1899 */
1900 disable_8259A_irq(0);
1901 vector = assign_irq_vector(0);
1902 set_intr_gate(vector, interrupt[0]);
1904 /*
1905 * Subtle, code in do_timer_interrupt() expects an AEOI
1906 * mode for the 8259A whenever interrupts are routed
1907 * through I/O APICs. Also IRQ0 has to be enabled in
1908 * the 8259A which implies the virtual wire has to be
1909 * disabled in the local APIC.
1910 */
1911 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1912 init_8259A(1);
1913 if (timer_over_8254 > 0)
1914 enable_8259A_irq(0);
1916 pin1 = find_isa_irq_pin(0, mp_INT);
1917 apic1 = find_isa_irq_apic(0, mp_INT);
1918 pin2 = ioapic_i8259.pin;
1919 apic2 = ioapic_i8259.apic;
1921 if (pin1 == 0)
1922 timer_uses_ioapic_pin_0 = 1;
1924 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1925 vector, apic1, pin1, apic2, pin2);
1927 if (pin1 != -1) {
1928 /*
1929 * Ok, does IRQ0 through the IOAPIC work?
1930 */
1931 unmask_IO_APIC_irq(0);
1932 if (!no_timer_check && timer_irq_works()) {
1933 nmi_watchdog_default();
1934 if (nmi_watchdog == NMI_IO_APIC) {
1935 disable_8259A_irq(0);
1936 setup_nmi();
1937 enable_8259A_irq(0);
1939 if (disable_timer_pin_1 > 0)
1940 clear_IO_APIC_pin(0, pin1);
1941 return;
1943 clear_IO_APIC_pin(apic1, pin1);
1944 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1945 "connected to IO-APIC\n");
1948 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1949 "through the 8259A ... ");
1950 if (pin2 != -1) {
1951 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1952 apic2, pin2);
1953 /*
1954 * legacy devices should be connected to IO APIC #0
1955 */
1956 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1957 if (timer_irq_works()) {
1958 apic_printk(APIC_VERBOSE," works.\n");
1959 nmi_watchdog_default();
1960 if (nmi_watchdog == NMI_IO_APIC) {
1961 setup_nmi();
1963 return;
1965 /*
1966 * Cleanup, just in case ...
1967 */
1968 clear_IO_APIC_pin(apic2, pin2);
1970 apic_printk(APIC_VERBOSE," failed.\n");
1972 if (nmi_watchdog == NMI_IO_APIC) {
1973 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1974 nmi_watchdog = 0;
1977 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1979 disable_8259A_irq(0);
1980 irq_desc[0].chip = &lapic_irq_type;
1981 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1982 enable_8259A_irq(0);
1984 if (timer_irq_works()) {
1985 apic_printk(APIC_VERBOSE," works.\n");
1986 return;
1988 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1989 apic_printk(APIC_VERBOSE," failed.\n");
1991 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1993 init_8259A(0);
1994 make_8259A_irq(0);
1995 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1997 unlock_ExtINT_logic();
1999 if (timer_irq_works()) {
2000 apic_printk(APIC_VERBOSE," works.\n");
2001 return;
2003 apic_printk(APIC_VERBOSE," failed :(.\n");
2004 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2006 #else
2007 #define check_timer() ((void)0)
2008 int timer_uses_ioapic_pin_0 = 0;
2009 #endif /* !CONFIG_XEN */
2011 static int __init notimercheck(char *s)
2013 no_timer_check = 1;
2014 return 1;
2016 __setup("no_timer_check", notimercheck);
2018 /*
2020 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2021 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2022 * Linux doesn't really care, as it's not actually used
2023 * for any interrupt handling anyway.
2024 */
2025 #define PIC_IRQS (1<<2)
2027 void __init setup_IO_APIC(void)
2029 enable_IO_APIC();
2031 if (acpi_ioapic)
2032 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2033 else
2034 io_apic_irqs = ~PIC_IRQS;
2036 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2038 /*
2039 * Set up the IO-APIC IRQ routing table.
2040 */
2041 if (!acpi_ioapic)
2042 setup_ioapic_ids_from_mpc();
2043 #ifndef CONFIG_XEN
2044 sync_Arb_IDs();
2045 #endif /* !CONFIG_XEN */
2046 setup_IO_APIC_irqs();
2047 init_IO_APIC_traps();
2048 check_timer();
2049 if (!acpi_ioapic)
2050 print_IO_APIC();
2053 struct sysfs_ioapic_data {
2054 struct sys_device dev;
2055 struct IO_APIC_route_entry entry[0];
2056 };
2057 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2059 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2061 struct IO_APIC_route_entry *entry;
2062 struct sysfs_ioapic_data *data;
2063 unsigned long flags;
2064 int i;
2066 data = container_of(dev, struct sysfs_ioapic_data, dev);
2067 entry = data->entry;
2068 spin_lock_irqsave(&ioapic_lock, flags);
2069 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2070 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2071 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2073 spin_unlock_irqrestore(&ioapic_lock, flags);
2075 return 0;
2078 static int ioapic_resume(struct sys_device *dev)
2080 struct IO_APIC_route_entry *entry;
2081 struct sysfs_ioapic_data *data;
2082 unsigned long flags;
2083 union IO_APIC_reg_00 reg_00;
2084 int i;
2086 data = container_of(dev, struct sysfs_ioapic_data, dev);
2087 entry = data->entry;
2089 spin_lock_irqsave(&ioapic_lock, flags);
2090 reg_00.raw = io_apic_read(dev->id, 0);
2091 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2092 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2093 io_apic_write(dev->id, 0, reg_00.raw);
2095 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2096 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2097 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2099 spin_unlock_irqrestore(&ioapic_lock, flags);
2101 return 0;
2104 static struct sysdev_class ioapic_sysdev_class = {
2105 set_kset_name("ioapic"),
2106 .suspend = ioapic_suspend,
2107 .resume = ioapic_resume,
2108 };
2110 static int __init ioapic_init_sysfs(void)
2112 struct sys_device * dev;
2113 int i, size, error = 0;
2115 error = sysdev_class_register(&ioapic_sysdev_class);
2116 if (error)
2117 return error;
2119 for (i = 0; i < nr_ioapics; i++ ) {
2120 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2121 * sizeof(struct IO_APIC_route_entry);
2122 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2123 if (!mp_ioapic_data[i]) {
2124 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2125 continue;
2127 memset(mp_ioapic_data[i], 0, size);
2128 dev = &mp_ioapic_data[i]->dev;
2129 dev->id = i;
2130 dev->cls = &ioapic_sysdev_class;
2131 error = sysdev_register(dev);
2132 if (error) {
2133 kfree(mp_ioapic_data[i]);
2134 mp_ioapic_data[i] = NULL;
2135 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2136 continue;
2140 return 0;
2143 device_initcall(ioapic_init_sysfs);
2145 /* --------------------------------------------------------------------------
2146 ACPI-based IOAPIC Configuration
2147 -------------------------------------------------------------------------- */
2149 #ifdef CONFIG_ACPI
2151 #define IO_APIC_MAX_ID 0xFE
2153 int __init io_apic_get_version (int ioapic)
2155 union IO_APIC_reg_01 reg_01;
2156 unsigned long flags;
2158 spin_lock_irqsave(&ioapic_lock, flags);
2159 reg_01.raw = io_apic_read(ioapic, 1);
2160 spin_unlock_irqrestore(&ioapic_lock, flags);
2162 return reg_01.bits.version;
2166 int __init io_apic_get_redir_entries (int ioapic)
2168 union IO_APIC_reg_01 reg_01;
2169 unsigned long flags;
2171 spin_lock_irqsave(&ioapic_lock, flags);
2172 reg_01.raw = io_apic_read(ioapic, 1);
2173 spin_unlock_irqrestore(&ioapic_lock, flags);
2175 return reg_01.bits.entries;
2179 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2181 struct IO_APIC_route_entry entry;
2182 unsigned long flags;
2184 if (!IO_APIC_IRQ(irq)) {
2185 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2186 ioapic);
2187 return -EINVAL;
2190 /*
2191 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2192 * Note that we mask (disable) IRQs now -- these get enabled when the
2193 * corresponding device driver registers for this IRQ.
2194 */
2196 memset(&entry,0,sizeof(entry));
2198 entry.delivery_mode = INT_DELIVERY_MODE;
2199 entry.dest_mode = INT_DEST_MODE;
2200 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2201 entry.trigger = edge_level;
2202 entry.polarity = active_high_low;
2203 entry.mask = 1; /* Disabled (masked) */
2205 irq = gsi_irq_sharing(irq);
2206 /*
2207 * IRQs < 16 are already in the irq_2_pin[] map
2208 */
2209 if (irq >= 16)
2210 add_pin_to_irq(irq, ioapic, pin);
2212 entry.vector = assign_irq_vector(irq);
2214 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2215 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2216 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2217 edge_level, active_high_low);
2219 ioapic_register_intr(irq, entry.vector, edge_level);
2221 if (!ioapic && (irq < 16))
2222 disable_8259A_irq(irq);
2224 spin_lock_irqsave(&ioapic_lock, flags);
2225 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2226 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2227 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2228 spin_unlock_irqrestore(&ioapic_lock, flags);
2230 return 0;
2233 #endif /* CONFIG_ACPI */
2236 #ifndef CONFIG_XEN
2237 /*
2238 * This function currently is only a helper for the i386 smp boot process where
2239 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2240 * so mask in all cases should simply be TARGET_CPUS
2241 */
2242 #ifdef CONFIG_SMP
2243 void __init setup_ioapic_dest(void)
2245 int pin, ioapic, irq, irq_entry;
2247 if (skip_ioapic_setup == 1)
2248 return;
2250 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2251 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2252 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2253 if (irq_entry == -1)
2254 continue;
2255 irq = pin_2_irq(irq_entry, ioapic, pin);
2256 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2261 #endif
2262 #endif /* !CONFIG_XEN */